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From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH i-g-t 5/8] tools/intel_watermark: TGL+ can have 4 pipes
Date: Fri, 14 May 2021 12:53:35 +0300	[thread overview]
Message-ID: <20210514095335.GE8652@intel.com> (raw)
In-Reply-To: <20210414022754.31710-6-ville.syrjala@linux.intel.com>

On Wed, Apr 14, 2021 at 05:27:51AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Decode pipe D watermark stuff too.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  tools/intel_watermark.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index ff373fdb0c6d..657fff20ec7a 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -131,6 +131,11 @@ static char endis_ast(bool enabled)
>  	return enabled ? '*' : ' ';
>  }
>  
> +static int skl_num_pipes(uint32_t d)
> +{
> +	return intel_gen(d) >= 12 ? 4 : 3;
> +}
> +
>  static int skl_num_planes(uint32_t d, int pipe)
>  {
>  	int gen = intel_gen(d);
> @@ -269,7 +274,7 @@ static void skl_wm_dump(void)
>  {
>  	struct intel_mmio_data mmio_data;
>  	int pipe, plane, level;
> -	int num_pipes = 3;
> +	int num_pipes = skl_num_pipes(devid);
>  	int max_planes = skl_max_planes(devid);
>  	int num_levels = 8;
>  	uint32_t base_addr = 0x70000, addr, wm_offset;
> -- 
> 2.26.3
> 
> _______________________________________________
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> igt-dev@lists.freedesktop.org
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  reply	other threads:[~2021-05-14  9:50 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-14  2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 1/8] tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues Ville Syrjala
2021-05-14  9:31   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 2/8] tools/intel_watermark: Use WM_SR_CNT to observe SR residency Ville Syrjala
2021-05-14  9:36   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 3/8] tools/intel_watermark: Deal with TGL planes Ville Syrjala
2021-05-14  9:47   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 4/8] tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp Ville Syrjala
2021-05-14  9:53   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 5/8] tools/intel_watermark: TGL+ can have 4 pipes Ville Syrjala
2021-05-14  9:53   ` Lisovskiy, Stanislav [this message]
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 6/8] tools/intel_watermark: Make reg dump section less wide Ville Syrjala
2021-05-14  9:50   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 7/8] tools/intel_watermark: Handle ADL-P dedicated SAGV watermarks Ville Syrjala
2021-05-14  9:51   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 8/8] tools/intel_watermark: Widen register bitfields Ville Syrjala
2021-05-14  9:51   ` Lisovskiy, Stanislav
2021-04-14  3:04 ` [igt-dev] ✓ Fi.CI.BAT: success for tools/intel_watermark: Support new platofrms Patchwork
2021-04-14  4:01 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork

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