[igt-dev] [PATCH i-g-t 00/10] Tile 4 plane format support

[igt-dev] [PATCH i-g-t 00/10] Tile 4 plane format support

[Jeevan B]

Added DG2 platform definition with PCI IDS.
Also introduce support for the new Tile4 format, which is
4K column-major tiles consisting of 64B row-major subtiles,
with same base structure as Y Tile(16B OWords * 4)

v3: Remove DG2 platform definition patch and
    Add check for tile4 support in kms_draw_crc patch.
v4: Split second patch
    Kernel patch yet to be merged to add in commit. (Petri)
v5: place I915_TILING_4 location

Jeevan B (6):
  include/drm-uapi: Introduce new Tile 4 format
  igt/lib: Add tile 4(F-tile) format support
  igt/tests: Add support for Tile4(TileF) format to
    tests/kms_plane_multiple
  igt/tests: Add support for Tile4(TileF) format to
    tests/kms_plane_lowres
  igt/tests: Add support for Tile4(TileF) format to tests/kms_big_fb
  igt/tests: Add support for Tile4(TileF) format to kms_rotation_crc

Matt Roper (2):
  lib/igt_draw: Add pixel math for tile-4
  igt/tests: Add support for Tile4(TileF) format to testdisplay

Mika Kahola (1):
  lib/intel_device_info: Add a flag to indicate tiling 4 support

Stanislav Lisovskiy (1):
  igt/tests: Add support for Tile4(TileF) format to kms_draw_crc

 include/drm-uapi/drm_fourcc.h |  11 ++++
 lib/gpu_cmds.c                |   4 +-
 lib/igt_draw.c                | 116 +++++++++++++++++++++++++++++++++-
 lib/igt_fb.c                  |   7 ++
 lib/intel_batchbuffer.c       |   8 ++-
 lib/intel_batchbuffer.h       |   7 +-
 lib/intel_chipset.h           |   3 +
 lib/intel_device_info.c       |   1 +
 tests/i915/kms_big_fb.c       |   1 +
 tests/i915/kms_draw_crc.c     |  18 ++++--
 tests/kms_plane_lowres.c      |   3 +
 tests/kms_plane_multiple.c    |   3 +
 tests/kms_rotation_crc.c      |   4 ++
 tests/testdisplay.c           |   6 +-
 14 files changed, 176 insertions(+), 16 deletions(-)

-- 
2.17.1

[igt-dev] [PATCH i-g-t 01/10] lib/intel_device_info: Add a flag to indicate tiling 4 support

[Jeevan B]

From: Mika Kahola <mika.kahola@intel.com>

Add tiling 4 support flag for DG2 platform. This is similar that
we have defined in kernel i915_pci.c intel_device_info() for DG2.

v2: rebase

Signed-off-by: Jeevan B <jeevan.b@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_chipset.h     | 3 +++
 lib/intel_device_info.c | 1 +
 2 files changed, 4 insertions(+)

diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index e27b9aab..db75a829 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -40,6 +40,7 @@ struct intel_device_info {
 	unsigned graphics_ver;
 	unsigned display_ver;
 	unsigned gt; /* 0 if unknown */
+	bool has_4tile : 1;
 	bool has_flatccs;
 	bool is_mobile : 1;
 	bool is_whitney : 1;
@@ -216,6 +217,8 @@ void intel_check_pch(void);
 				   IS_CHERRYVIEW(devid) || \
 				   IS_BROXTON(devid)))
 
+#define HAS_4TILE(devid)	(intel_get_device_info(devid)->has_4tile)
+
 #define HAS_FLATCCS(devid)	(intel_get_device_info(devid)->has_flatccs)
 
 #endif /* _INTEL_CHIPSET_H */
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 9f191367..e55841df 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -393,6 +393,7 @@ static const struct intel_device_info intel_dg1_info = {
 static const struct intel_device_info intel_dg2_info = {
 	.graphics_ver = 12,
 	.display_ver = 13,
+	.has_4tile = true,
 	.is_dg2 = true,
 	.codename = "dg2",
 	.has_flatccs = true,
-- 
2.17.1

[igt-dev] [PATCH i-g-t 02/10] include/drm-uapi: Introduce new Tile 4 format

[Jeevan B]

This tiling layout uses 4KB tiles in a row-major layout. It has the same
shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
only differs from Tile Y at the 256B granularity in between. At this
granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
of 64B x 8 rows.

Reference:
https://cgit.freedesktop.org/drm/drm-tip/commit/?id=c6e7deb0f092616bd8cb19e8c436b212c64daaab

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 include/drm-uapi/drm_fourcc.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index 91b6a0fd..318b50fa 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -559,6 +559,17 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
 
+/*
+ * Intel Tile 4 layout
+ *
+ * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
+ * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
+ * only differs from Tile Y at the 256B granularity in between. At this
+ * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
+ * of 64B x 8 rows.
+ */
+#define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.17.1

Re: [igt-dev] [PATCH i-g-t 02/10] include/drm-uapi: Introduce new Tile 4 format

[Zbigniew Kempczyński]

On Fri, Feb 25, 2022 at 10:38:45AM +0530, Jeevan B wrote:
> This tiling layout uses 4KB tiles in a row-major layout. It has the same
> shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> only differs from Tile Y at the 256B granularity in between. At this
> granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> of 64B x 8 rows.
> 
> Reference:
> https://cgit.freedesktop.org/drm/drm-tip/commit/?id=c6e7deb0f092616bd8cb19e8c436b212c64daaab
> 
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
>  include/drm-uapi/drm_fourcc.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
> index 91b6a0fd..318b50fa 100644
> --- a/include/drm-uapi/drm_fourcc.h
> +++ b/include/drm-uapi/drm_fourcc.h
> @@ -559,6 +559,17 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
>  
> +/*
> + * Intel Tile 4 layout
> + *
> + * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
> + * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> + * only differs from Tile Y at the 256B granularity in between. At this
> + * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> + * of 64B x 8 rows.
> + */
> +#define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
> -- 
> 2.17.1
> 

I think you should sync this file, not only apply this change.

--
Zbigniew

Re: [igt-dev] [PATCH i-g-t 02/10] include/drm-uapi: Introduce new Tile 4 format

[B, Jeevan]

>-----Original Message-----
>From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
>Sent: Friday, February 25, 2022 11:48 AM
>To: B, Jeevan <jeevan.b@intel.com>
>Cc: igt-dev@lists.freedesktop.org; Heikkila, Juha-pekka <juha-
>pekka.heikkila@intel.com>; Latvala, Petri <petri.latvala@intel.com>; Lisovskiy,
>Stanislav <stanislav.lisovskiy@intel.com>
>Subject: Re: [PATCH i-g-t 02/10] include/drm-uapi: Introduce new Tile 4 format
>
>On Fri, Feb 25, 2022 at 10:38:45AM +0530, Jeevan B wrote:
>> This tiling layout uses 4KB tiles in a row-major layout. It has the
>> same shape as Tile Y at two granularities: 4KB (128B x 32) and 64B
>> (16B x 4). It only differs from Tile Y at the 256B granularity in
>> between. At this granularity, Tile Y has a shape of 16B x 32 rows, but
>> this tiling has a shape of 64B x 8 rows.
>>
>> Reference:
>> https://cgit.freedesktop.org/drm/drm-tip/commit/?id=c6e7deb0f092616bd8
>> cb19e8c436b212c64daaab
>>
>> Signed-off-by: Jeevan B <jeevan.b@intel.com>
>> ---
>>  include/drm-uapi/drm_fourcc.h | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>>
>> diff --git a/include/drm-uapi/drm_fourcc.h
>> b/include/drm-uapi/drm_fourcc.h index 91b6a0fd..318b50fa 100644
>> --- a/include/drm-uapi/drm_fourcc.h
>> +++ b/include/drm-uapi/drm_fourcc.h
>> @@ -559,6 +559,17 @@ extern "C" {
>>   */
>>  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
>> fourcc_mod_code(INTEL, 8)
>>
>> +/*
>> + * Intel Tile 4 layout
>> + *
>> + * This is a tiled layout using 4KB tiles in a row-major layout. It
>> +has the same
>> + * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B
>> +x 4). It
>> + * only differs from Tile Y at the 256B granularity in between. At
>> +this
>> + * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling
>> +has a shape
>> + * of 64B x 8 rows.
>> + */
>> +#define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
>> +
>>  /*
>>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>>   *
>> --
>> 2.17.1
>>
>
>I think you should sync this file, not only apply this change.
Sure will do this. 

Thanks 
Jeevan B
>
>--
>Zbigniew

[igt-dev] [PATCH i-g-t 03/10] igt/lib: Add tile 4(F-tile) format support

[Jeevan B]

Introduce support for the new Tile4 format, which is
4K column-major tiles consisting of 64B row-major subtiles,
with same base structure as Y Tile(16B OWords * 4)

v2: place I915_TILING_4 correctly.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 lib/gpu_cmds.c          | 4 ++--
 lib/igt_draw.c          | 7 ++++++-
 lib/igt_fb.c            | 7 +++++++
 lib/intel_batchbuffer.c | 8 ++++++--
 lib/intel_batchbuffer.h | 7 ++++---
 5 files changed, 25 insertions(+), 8 deletions(-)

diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index a45a9048..c31b51f7 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -156,7 +156,7 @@ gen8_fill_surface_state(struct intel_bb *ibb,
 
 	if (buf->tiling == I915_TILING_X)
 		ss->ss0.tiled_mode = 2;
-	else if (buf->tiling == I915_TILING_Y)
+	else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
 		ss->ss0.tiled_mode = 3;
 
 	address = intel_bb_offset_reloc(ibb, buf->handle,
@@ -211,7 +211,7 @@ gen11_fill_surface_state(struct intel_bb *ibb,
 
 	if (buf->tiling == I915_TILING_X)
 		ss->ss0.tiled_mode = 2;
-	else if (buf->tiling == I915_TILING_Y)
+	else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
 		ss->ss0.tiled_mode = 3;
 	else
 		ss->ss0.tiled_mode = 0;
diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 2af27b11..0ca43deb 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -271,7 +271,7 @@ static void switch_blt_tiling(struct intel_bb *ibb, uint32_t tiling, bool on)
 	uint32_t bcs_swctrl;
 
 	/* Default is X-tile */
-	if (tiling != I915_TILING_Y)
+	if (tiling != I915_TILING_Y && tiling != I915_TILING_4)
 		return;
 
 	igt_require(ibb->gen >= 6);
@@ -318,6 +318,7 @@ static void draw_rect_ptr_tiled(void *ptr, uint32_t stride, uint32_t tiling,
 							       swizzle, bpp);
 				break;
 			case I915_TILING_Y:
+			case I915_TILING_4:
 				pos = linear_x_y_to_ytiled_pos(x, y, stride,
 							       swizzle, bpp);
 				break;
@@ -350,6 +351,7 @@ static void draw_rect_mmap_cpu(int fd, struct buf_data *buf, struct rect *rect,
 		break;
 	case I915_TILING_X:
 	case I915_TILING_Y:
+	case I915_TILING_4:
 		draw_rect_ptr_tiled(ptr, buf->stride, tiling, swizzle, rect,
 				    color, buf->bpp);
 		break;
@@ -409,6 +411,7 @@ static void draw_rect_mmap_wc(int fd, struct buf_data *buf, struct rect *rect,
 		break;
 	case I915_TILING_X:
 	case I915_TILING_Y:
+	case I915_TILING_4:
 		draw_rect_ptr_tiled(ptr, buf->stride, tiling, swizzle, rect,
 				    color, buf->bpp);
 		break;
@@ -467,6 +470,7 @@ static void draw_rect_pwrite_tiled(int fd, struct buf_data *buf,
 						 swizzle, buf->bpp, &x, &y);
 			break;
 		case I915_TILING_Y:
+		case I915_TILING_4:
 			ytiled_pos_to_x_y_linear(tiled_pos, buf->stride,
 						 swizzle, buf->bpp, &x, &y);
 			break;
@@ -507,6 +511,7 @@ static void draw_rect_pwrite(int fd, struct buf_data *buf,
 		break;
 	case I915_TILING_X:
 	case I915_TILING_Y:
+	case I915_TILING_4:
 		draw_rect_pwrite_tiled(fd, buf, tiling, rect, color, swizzle);
 		break;
 	default:
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 1530b960..74ca5eec 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -456,6 +456,7 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+	case I915_FORMAT_MOD_4_TILED:
 		igt_require_intel(fd);
 		if (intel_display_ver(intel_get_drm_devid(fd)) == 2) {
 			*width_ret = 128;
@@ -964,6 +965,8 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return I915_TILING_Y;
+	case I915_FORMAT_MOD_4_TILED:
+		return I915_TILING_4;
 	case I915_FORMAT_MOD_Yf_TILED:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
 		return I915_TILING_Yf;
@@ -991,6 +994,8 @@ uint64_t igt_fb_tiling_to_mod(uint64_t tiling)
 		return I915_FORMAT_MOD_X_TILED;
 	case I915_TILING_Y:
 		return I915_FORMAT_MOD_Y_TILED;
+	case I915_TILING_4:
+		return I915_FORMAT_MOD_4_TILED;
 	case I915_TILING_Yf:
 		return I915_FORMAT_MOD_Yf_TILED;
 	default:
@@ -4398,6 +4403,8 @@ const char *igt_fb_modifier_name(uint64_t modifier)
 		return "Y-RC_CCS-CC";
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return "Y-MC_CCS";
+	case I915_FORMAT_MOD_4_TILED:
+		return "4";
 	default:
 		return "?";
 	}
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index e5666cd4..b4761e44 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -617,6 +617,7 @@ static uint32_t fast_copy_dword0(unsigned int src_tiling,
 		dword0 |= XY_FAST_COPY_SRC_TILING_X;
 		break;
 	case I915_TILING_Y:
+	case I915_TILING_4:
 	case I915_TILING_Yf:
 		dword0 |= XY_FAST_COPY_SRC_TILING_Yb_Yf;
 		break;
@@ -633,6 +634,7 @@ static uint32_t fast_copy_dword0(unsigned int src_tiling,
 		dword0 |= XY_FAST_COPY_DST_TILING_X;
 		break;
 	case I915_TILING_Y:
+	case I915_TILING_4:
 	case I915_TILING_Yf:
 		dword0 |= XY_FAST_COPY_DST_TILING_Yb_Yf;
 		break;
@@ -653,9 +655,11 @@ static uint32_t fast_copy_dword1(unsigned int src_tiling,
 {
 	uint32_t dword1 = 0;
 
-	if (src_tiling == I915_TILING_Yf)
+	if (src_tiling == I915_TILING_Yf || src_tiling == I915_TILING_4)
+		/* Repurposed as Tile-4 on DG2 */
 		dword1 |= XY_FAST_COPY_SRC_TILING_Yf;
-	if (dst_tiling == I915_TILING_Yf)
+	if (dst_tiling == I915_TILING_Yf || src_tiling == I915_TILING_4)
+		/* Repurposed as Tile-4 on DG2 */
 		dword1 |= XY_FAST_COPY_DST_TILING_Yf;
 
 	switch (bpp) {
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index a488f9cf..75d41ea3 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -202,7 +202,7 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
 		   long int size);
 
 /*
- * Yf/Ys tiling
+ * Yf/Ys/4 tiling
  *
  * Tiling mode in the I915_TILING_... namespace for new tiling modes which are
  * defined in the kernel. (They are not fenceable so the kernel does not need
@@ -210,8 +210,9 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
  *
  * They are to be used the the blitting routines below.
  */
-#define I915_TILING_Yf	3
-#define I915_TILING_Ys	4
+#define I915_TILING_4	(I915_TILING_LAST + 1)
+#define I915_TILING_Yf	(I915_TILING_LAST + 2)
+#define I915_TILING_Ys	(I915_TILING_LAST + 3)
 
 enum i915_compression {
 	I915_COMPRESSION_NONE,
-- 
2.17.1

Re: [igt-dev] [PATCH i-g-t 03/10] igt/lib: Add tile 4(F-tile) format support

[Lisovskiy, Stanislav]

On Fri, Feb 25, 2022 at 10:38:46AM +0530, Jeevan B wrote:
> Introduce support for the new Tile4 format, which is
> 4K column-major tiles consisting of 64B row-major subtiles,
> with same base structure as Y Tile(16B OWords * 4)
> 
> v2: place I915_TILING_4 correctly.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  lib/gpu_cmds.c          | 4 ++--
>  lib/igt_draw.c          | 7 ++++++-
>  lib/igt_fb.c            | 7 +++++++
>  lib/intel_batchbuffer.c | 8 ++++++--
>  lib/intel_batchbuffer.h | 7 ++++---
>  5 files changed, 25 insertions(+), 8 deletions(-)
> 
> diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
> index a45a9048..c31b51f7 100644
> --- a/lib/gpu_cmds.c
> +++ b/lib/gpu_cmds.c
> @@ -156,7 +156,7 @@ gen8_fill_surface_state(struct intel_bb *ibb,
>  
>  	if (buf->tiling == I915_TILING_X)
>  		ss->ss0.tiled_mode = 2;
> -	else if (buf->tiling == I915_TILING_Y)
> +	else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
>  		ss->ss0.tiled_mode = 3;
>  
>  	address = intel_bb_offset_reloc(ibb, buf->handle,
> @@ -211,7 +211,7 @@ gen11_fill_surface_state(struct intel_bb *ibb,
>  
>  	if (buf->tiling == I915_TILING_X)
>  		ss->ss0.tiled_mode = 2;
> -	else if (buf->tiling == I915_TILING_Y)
> +	else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4)
>  		ss->ss0.tiled_mode = 3;
>  	else
>  		ss->ss0.tiled_mode = 0;
> diff --git a/lib/igt_draw.c b/lib/igt_draw.c
> index 2af27b11..0ca43deb 100644
> --- a/lib/igt_draw.c
> +++ b/lib/igt_draw.c
> @@ -271,7 +271,7 @@ static void switch_blt_tiling(struct intel_bb *ibb, uint32_t tiling, bool on)
>  	uint32_t bcs_swctrl;
>  
>  	/* Default is X-tile */
> -	if (tiling != I915_TILING_Y)
> +	if (tiling != I915_TILING_Y && tiling != I915_TILING_4)
>  		return;
>  
>  	igt_require(ibb->gen >= 6);
> @@ -318,6 +318,7 @@ static void draw_rect_ptr_tiled(void *ptr, uint32_t stride, uint32_t tiling,
>  							       swizzle, bpp);
>  				break;
>  			case I915_TILING_Y:
> +			case I915_TILING_4:
>  				pos = linear_x_y_to_ytiled_pos(x, y, stride,
>  							       swizzle, bpp);
>  				break;
> @@ -350,6 +351,7 @@ static void draw_rect_mmap_cpu(int fd, struct buf_data *buf, struct rect *rect,
>  		break;
>  	case I915_TILING_X:
>  	case I915_TILING_Y:
> +	case I915_TILING_4:
>  		draw_rect_ptr_tiled(ptr, buf->stride, tiling, swizzle, rect,
>  				    color, buf->bpp);
>  		break;
> @@ -409,6 +411,7 @@ static void draw_rect_mmap_wc(int fd, struct buf_data *buf, struct rect *rect,
>  		break;
>  	case I915_TILING_X:
>  	case I915_TILING_Y:
> +	case I915_TILING_4:
>  		draw_rect_ptr_tiled(ptr, buf->stride, tiling, swizzle, rect,
>  				    color, buf->bpp);
>  		break;
> @@ -467,6 +470,7 @@ static void draw_rect_pwrite_tiled(int fd, struct buf_data *buf,
>  						 swizzle, buf->bpp, &x, &y);
>  			break;
>  		case I915_TILING_Y:
> +		case I915_TILING_4:
>  			ytiled_pos_to_x_y_linear(tiled_pos, buf->stride,
>  						 swizzle, buf->bpp, &x, &y);
>  			break;
> @@ -507,6 +511,7 @@ static void draw_rect_pwrite(int fd, struct buf_data *buf,
>  		break;
>  	case I915_TILING_X:
>  	case I915_TILING_Y:
> +	case I915_TILING_4:
>  		draw_rect_pwrite_tiled(fd, buf, tiling, rect, color, swizzle);
>  		break;
>  	default:
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 1530b960..74ca5eec 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -456,6 +456,7 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +	case I915_FORMAT_MOD_4_TILED:
>  		igt_require_intel(fd);
>  		if (intel_display_ver(intel_get_drm_devid(fd)) == 2) {
>  			*width_ret = 128;
> @@ -964,6 +965,8 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return I915_TILING_Y;
> +	case I915_FORMAT_MOD_4_TILED:
> +		return I915_TILING_4;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
>  		return I915_TILING_Yf;
> @@ -991,6 +994,8 @@ uint64_t igt_fb_tiling_to_mod(uint64_t tiling)
>  		return I915_FORMAT_MOD_X_TILED;
>  	case I915_TILING_Y:
>  		return I915_FORMAT_MOD_Y_TILED;
> +	case I915_TILING_4:
> +		return I915_FORMAT_MOD_4_TILED;
>  	case I915_TILING_Yf:
>  		return I915_FORMAT_MOD_Yf_TILED;
>  	default:
> @@ -4398,6 +4403,8 @@ const char *igt_fb_modifier_name(uint64_t modifier)
>  		return "Y-RC_CCS-CC";
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return "Y-MC_CCS";
> +	case I915_FORMAT_MOD_4_TILED:
> +		return "4";
>  	default:
>  		return "?";
>  	}
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index e5666cd4..b4761e44 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -617,6 +617,7 @@ static uint32_t fast_copy_dword0(unsigned int src_tiling,
>  		dword0 |= XY_FAST_COPY_SRC_TILING_X;
>  		break;
>  	case I915_TILING_Y:
> +	case I915_TILING_4:
>  	case I915_TILING_Yf:
>  		dword0 |= XY_FAST_COPY_SRC_TILING_Yb_Yf;
>  		break;
> @@ -633,6 +634,7 @@ static uint32_t fast_copy_dword0(unsigned int src_tiling,
>  		dword0 |= XY_FAST_COPY_DST_TILING_X;
>  		break;
>  	case I915_TILING_Y:
> +	case I915_TILING_4:
>  	case I915_TILING_Yf:
>  		dword0 |= XY_FAST_COPY_DST_TILING_Yb_Yf;
>  		break;
> @@ -653,9 +655,11 @@ static uint32_t fast_copy_dword1(unsigned int src_tiling,
>  {
>  	uint32_t dword1 = 0;
>  
> -	if (src_tiling == I915_TILING_Yf)
> +	if (src_tiling == I915_TILING_Yf || src_tiling == I915_TILING_4)
> +		/* Repurposed as Tile-4 on DG2 */
>  		dword1 |= XY_FAST_COPY_SRC_TILING_Yf;
> -	if (dst_tiling == I915_TILING_Yf)
> +	if (dst_tiling == I915_TILING_Yf || src_tiling == I915_TILING_4)
> +		/* Repurposed as Tile-4 on DG2 */
>  		dword1 |= XY_FAST_COPY_DST_TILING_Yf;
>  
>  	switch (bpp) {
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
> index a488f9cf..75d41ea3 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -202,7 +202,7 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
>  		   long int size);
>  
>  /*
> - * Yf/Ys tiling
> + * Yf/Ys/4 tiling
>   *
>   * Tiling mode in the I915_TILING_... namespace for new tiling modes which are
>   * defined in the kernel. (They are not fenceable so the kernel does not need
> @@ -210,8 +210,9 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
>   *
>   * They are to be used the the blitting routines below.
>   */
> -#define I915_TILING_Yf	3
> -#define I915_TILING_Ys	4
> +#define I915_TILING_4	(I915_TILING_LAST + 1)
> +#define I915_TILING_Yf	(I915_TILING_LAST + 2)
> +#define I915_TILING_Ys	(I915_TILING_LAST + 3)
>  
>  enum i915_compression {
>  	I915_COMPRESSION_NONE,
> -- 
> 2.17.1
> 

[igt-dev] [PATCH i-g-t 04/10] lib/igt_draw: Add pixel math for tile-4

[Jeevan B]

From: Matt Roper <matthew.d.roper@intel.com>

We need to implement the tile-4 math to convert x,y coordinates to
buffer offsets and vice versa for cases where we're using the CPU to
tile/detile rather than a GPU engine (e.g., the mmap_cpu and pwrite
subtests for kms_draw_crc).

The bspec description of tiling-4 is very confusing/misleading, but the
implementation here does match the tile-4 content generated by GPU
engines and recognized properly by the display controller.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 lib/igt_draw.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 111 insertions(+), 2 deletions(-)

diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 0ca43deb..d78ecdf0 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -226,6 +226,71 @@ static int linear_x_y_to_ytiled_pos(int x, int y, uint32_t stride, int swizzle,
 	return pos / pixel_size;
 }
 
+#define OW_SIZE 16			/* in bytes */
+#define TILE_4_SUBTILE_SIZE 64		/* in bytes */
+#define TILE_4_WIDTH 128		/* in bytes */
+#define TILE_4_HEIGHT 32		/* in pixels */
+#define TILE_4_SUBTILE_WIDTH  OW_SIZE	/* in bytes */
+#define TILE_4_SUBTILE_HEIGHT 4		/* in pixels */
+
+/*
+ * Subtile remapping for tile 4.  Note that map[a]==b implies map[b]==a
+ * so we can use the same table to tile and until.
+ */
+static const int tile4_subtile_map[] = {
+	0,  1,  2,  3,  8,  9, 10, 11,
+	4,  5,  6,  7, 12, 13, 14, 15,
+	16, 17, 18, 19, 24, 25, 26, 27,
+	20, 21, 22, 23, 28, 29, 30, 31,
+	32, 33, 34, 35, 40, 41, 42, 43,
+	36, 37, 38, 39, 44, 45, 46, 47,
+	48, 49, 50, 51, 56, 57, 58, 59,
+	52, 53, 54, 55, 60, 61, 62, 63
+};
+
+static int linear_x_y_to_4tiled_pos(int x, int y, uint32_t stride, int swizzle,
+				    int bpp)
+{
+	int tile_base_pos;
+	int tile_x, tile_y;
+	int subtile_col, subtile_row, subtile_num, new_subtile_num;
+	int pixel_size = bpp / 8;
+	int byte_x = x * pixel_size;
+	int pos;
+
+	/* Modern platforms that have 4-tiling don't use old bit 6 swizzling */
+	igt_assert_eq(swizzle, I915_BIT_6_SWIZZLE_NONE);
+
+	/*
+	* Where does the 4k tile start (in bytes)?  This is the same for Y and
+	* F so we can use the Y-tile algorithm to get to that point.
+	*/
+	tile_base_pos = (y / TILE_4_HEIGHT) * stride * TILE_4_HEIGHT +
+		4096 * (byte_x / TILE_4_WIDTH);
+
+	/* Find pixel within tile */
+	tile_x = (byte_x % TILE_4_WIDTH);
+	tile_y = y % TILE_4_HEIGHT;
+
+	/* And figure out the subtile within the 4k tile */
+	subtile_col = tile_x / TILE_4_SUBTILE_WIDTH;
+	subtile_row = tile_y / TILE_4_SUBTILE_HEIGHT;
+	subtile_num = subtile_row * 8 + subtile_col;
+
+	/* Swizzle the subtile number according to the bspec diagram */
+	new_subtile_num = tile4_subtile_map[subtile_num];
+
+	/* Calculate new position */
+	pos = tile_base_pos +
+		new_subtile_num * TILE_4_SUBTILE_SIZE +
+		(tile_y % TILE_4_SUBTILE_HEIGHT) * OW_SIZE +
+		tile_x % TILE_4_SUBTILE_WIDTH;
+	igt_assert(pos % pixel_size == 0);
+	pos /= pixel_size;
+
+	return pos;
+}
+
 static void xtiled_pos_to_x_y_linear(int tiled_pos, uint32_t stride,
 				     int swizzle, int bpp, int *x, int *y)
 {
@@ -253,6 +318,44 @@ static void ytiled_pos_to_x_y_linear(int tiled_pos, uint32_t stride,
 	*x /= pixel_size;
 }
 
+static void tile4_pos_to_x_y_linear(int tiled_pos, uint32_t stride,
+				    int swizzle, int bpp, int *x, int *y)
+{
+	int pixel_size = bpp / 8;
+	int tiles_per_line = stride / TILE_4_WIDTH;
+	int tile_num, tile_offset, tile_row, tile_col;
+	int tile_origin_x, tile_origin_y;
+	int subtile_num, subtile_offset, subtile_row, subtile_col;
+	int subtile_origin_x, subtile_origin_y;
+	int oword_num, byte_num;
+
+	/* Modern platforms that have 4-tiling don't use old bit 6 swizzling */
+	igt_assert_eq(swizzle, I915_BIT_6_SWIZZLE_NONE);
+
+	/* Calculate the x,y of the start of the 4k tile */
+	tile_num = tiled_pos / 4096;
+	tile_row = tile_num / tiles_per_line;
+	tile_col = tile_num % tiles_per_line;
+	tile_origin_x = tile_col * TILE_4_WIDTH;
+	tile_origin_y = tile_row * TILE_4_HEIGHT;
+
+	/* Now calculate the x,y offset of the start of the subtile */
+	tile_offset = tiled_pos % 4096;
+	subtile_num = tile4_subtile_map[tile_offset / TILE_4_SUBTILE_SIZE];
+	subtile_row = subtile_num / 8;
+	subtile_col = subtile_num % 8;
+	subtile_origin_x = subtile_col * TILE_4_SUBTILE_WIDTH;
+	subtile_origin_y = subtile_row * TILE_4_SUBTILE_HEIGHT;
+
+	/* Next the oword and byte within the subtile */
+	subtile_offset = tiled_pos % TILE_4_SUBTILE_SIZE;
+	oword_num = subtile_offset / OW_SIZE;
+	byte_num = subtile_offset % OW_SIZE;
+
+	*x = (tile_origin_x + subtile_origin_x + byte_num) / pixel_size;
+	*y = tile_origin_y + subtile_origin_y + oword_num;
+}
+
 static void set_pixel(void *_ptr, int index, uint32_t color, int bpp)
 {
 	if (bpp == 16) {
@@ -318,10 +421,13 @@ static void draw_rect_ptr_tiled(void *ptr, uint32_t stride, uint32_t tiling,
 							       swizzle, bpp);
 				break;
 			case I915_TILING_Y:
-			case I915_TILING_4:
 				pos = linear_x_y_to_ytiled_pos(x, y, stride,
 							       swizzle, bpp);
 				break;
+			case I915_TILING_4:
+				pos = linear_x_y_to_4tiled_pos(x, y, stride,
+							       swizzle, bpp);
+				break;
 			default:
 				igt_assert(false);
 			}
@@ -470,10 +576,13 @@ static void draw_rect_pwrite_tiled(int fd, struct buf_data *buf,
 						 swizzle, buf->bpp, &x, &y);
 			break;
 		case I915_TILING_Y:
-		case I915_TILING_4:
 			ytiled_pos_to_x_y_linear(tiled_pos, buf->stride,
 						 swizzle, buf->bpp, &x, &y);
 			break;
+		case I915_TILING_4:
+			tile4_pos_to_x_y_linear(tiled_pos, buf->stride,
+						swizzle, buf->bpp, &x, &y);
+			break;
 		default:
 			igt_assert(false);
 		}
-- 
2.17.1

Re: [igt-dev] [PATCH i-g-t 04/10] lib/igt_draw: Add pixel math for tile-4

[Lisovskiy, Stanislav]

On Fri, Feb 25, 2022 at 10:38:47AM +0530, Jeevan B wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> We need to implement the tile-4 math to convert x,y coordinates to
> buffer offsets and vice versa for cases where we're using the CPU to
> tile/detile rather than a GPU engine (e.g., the mmap_cpu and pwrite
> subtests for kms_draw_crc).
> 
> The bspec description of tiling-4 is very confusing/misleading, but the
> implementation here does match the tile-4 content generated by GPU
> engines and recognized properly by the display controller.
> 
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  lib/igt_draw.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 111 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/igt_draw.c b/lib/igt_draw.c
> index 0ca43deb..d78ecdf0 100644
> --- a/lib/igt_draw.c
> +++ b/lib/igt_draw.c
> @@ -226,6 +226,71 @@ static int linear_x_y_to_ytiled_pos(int x, int y, uint32_t stride, int swizzle,
>  	return pos / pixel_size;
>  }
>  
> +#define OW_SIZE 16			/* in bytes */
> +#define TILE_4_SUBTILE_SIZE 64		/* in bytes */
> +#define TILE_4_WIDTH 128		/* in bytes */
> +#define TILE_4_HEIGHT 32		/* in pixels */
> +#define TILE_4_SUBTILE_WIDTH  OW_SIZE	/* in bytes */
> +#define TILE_4_SUBTILE_HEIGHT 4		/* in pixels */
> +
> +/*
> + * Subtile remapping for tile 4.  Note that map[a]==b implies map[b]==a
> + * so we can use the same table to tile and until.
> + */
> +static const int tile4_subtile_map[] = {
> +	0,  1,  2,  3,  8,  9, 10, 11,
> +	4,  5,  6,  7, 12, 13, 14, 15,
> +	16, 17, 18, 19, 24, 25, 26, 27,
> +	20, 21, 22, 23, 28, 29, 30, 31,
> +	32, 33, 34, 35, 40, 41, 42, 43,
> +	36, 37, 38, 39, 44, 45, 46, 47,
> +	48, 49, 50, 51, 56, 57, 58, 59,
> +	52, 53, 54, 55, 60, 61, 62, 63
> +};
> +
> +static int linear_x_y_to_4tiled_pos(int x, int y, uint32_t stride, int swizzle,
> +				    int bpp)
> +{
> +	int tile_base_pos;
> +	int tile_x, tile_y;
> +	int subtile_col, subtile_row, subtile_num, new_subtile_num;
> +	int pixel_size = bpp / 8;
> +	int byte_x = x * pixel_size;
> +	int pos;
> +
> +	/* Modern platforms that have 4-tiling don't use old bit 6 swizzling */
> +	igt_assert_eq(swizzle, I915_BIT_6_SWIZZLE_NONE);
> +
> +	/*
> +	* Where does the 4k tile start (in bytes)?  This is the same for Y and
> +	* F so we can use the Y-tile algorithm to get to that point.
> +	*/
> +	tile_base_pos = (y / TILE_4_HEIGHT) * stride * TILE_4_HEIGHT +
> +		4096 * (byte_x / TILE_4_WIDTH);
> +
> +	/* Find pixel within tile */
> +	tile_x = (byte_x % TILE_4_WIDTH);
> +	tile_y = y % TILE_4_HEIGHT;
> +
> +	/* And figure out the subtile within the 4k tile */
> +	subtile_col = tile_x / TILE_4_SUBTILE_WIDTH;
> +	subtile_row = tile_y / TILE_4_SUBTILE_HEIGHT;
> +	subtile_num = subtile_row * 8 + subtile_col;
> +
> +	/* Swizzle the subtile number according to the bspec diagram */
> +	new_subtile_num = tile4_subtile_map[subtile_num];
> +
> +	/* Calculate new position */
> +	pos = tile_base_pos +
> +		new_subtile_num * TILE_4_SUBTILE_SIZE +
> +		(tile_y % TILE_4_SUBTILE_HEIGHT) * OW_SIZE +
> +		tile_x % TILE_4_SUBTILE_WIDTH;
> +	igt_assert(pos % pixel_size == 0);
> +	pos /= pixel_size;
> +
> +	return pos;
> +}
> +
>  static void xtiled_pos_to_x_y_linear(int tiled_pos, uint32_t stride,
>  				     int swizzle, int bpp, int *x, int *y)
>  {
> @@ -253,6 +318,44 @@ static void ytiled_pos_to_x_y_linear(int tiled_pos, uint32_t stride,
>  	*x /= pixel_size;
>  }
>  
> +static void tile4_pos_to_x_y_linear(int tiled_pos, uint32_t stride,
> +				    int swizzle, int bpp, int *x, int *y)
> +{
> +	int pixel_size = bpp / 8;
> +	int tiles_per_line = stride / TILE_4_WIDTH;
> +	int tile_num, tile_offset, tile_row, tile_col;
> +	int tile_origin_x, tile_origin_y;
> +	int subtile_num, subtile_offset, subtile_row, subtile_col;
> +	int subtile_origin_x, subtile_origin_y;
> +	int oword_num, byte_num;
> +
> +	/* Modern platforms that have 4-tiling don't use old bit 6 swizzling */
> +	igt_assert_eq(swizzle, I915_BIT_6_SWIZZLE_NONE);
> +
> +	/* Calculate the x,y of the start of the 4k tile */
> +	tile_num = tiled_pos / 4096;
> +	tile_row = tile_num / tiles_per_line;
> +	tile_col = tile_num % tiles_per_line;
> +	tile_origin_x = tile_col * TILE_4_WIDTH;
> +	tile_origin_y = tile_row * TILE_4_HEIGHT;
> +
> +	/* Now calculate the x,y offset of the start of the subtile */
> +	tile_offset = tiled_pos % 4096;
> +	subtile_num = tile4_subtile_map[tile_offset / TILE_4_SUBTILE_SIZE];
> +	subtile_row = subtile_num / 8;
> +	subtile_col = subtile_num % 8;
> +	subtile_origin_x = subtile_col * TILE_4_SUBTILE_WIDTH;
> +	subtile_origin_y = subtile_row * TILE_4_SUBTILE_HEIGHT;
> +
> +	/* Next the oword and byte within the subtile */
> +	subtile_offset = tiled_pos % TILE_4_SUBTILE_SIZE;
> +	oword_num = subtile_offset / OW_SIZE;
> +	byte_num = subtile_offset % OW_SIZE;
> +
> +	*x = (tile_origin_x + subtile_origin_x + byte_num) / pixel_size;
> +	*y = tile_origin_y + subtile_origin_y + oword_num;
> +}
> +
>  static void set_pixel(void *_ptr, int index, uint32_t color, int bpp)
>  {
>  	if (bpp == 16) {
> @@ -318,10 +421,13 @@ static void draw_rect_ptr_tiled(void *ptr, uint32_t stride, uint32_t tiling,
>  							       swizzle, bpp);
>  				break;
>  			case I915_TILING_Y:
> -			case I915_TILING_4:
>  				pos = linear_x_y_to_ytiled_pos(x, y, stride,
>  							       swizzle, bpp);
>  				break;
> +			case I915_TILING_4:
> +				pos = linear_x_y_to_4tiled_pos(x, y, stride,
> +							       swizzle, bpp);
> +				break;
>  			default:
>  				igt_assert(false);
>  			}
> @@ -470,10 +576,13 @@ static void draw_rect_pwrite_tiled(int fd, struct buf_data *buf,
>  						 swizzle, buf->bpp, &x, &y);
>  			break;
>  		case I915_TILING_Y:
> -		case I915_TILING_4:
>  			ytiled_pos_to_x_y_linear(tiled_pos, buf->stride,
>  						 swizzle, buf->bpp, &x, &y);
>  			break;
> +		case I915_TILING_4:
> +			tile4_pos_to_x_y_linear(tiled_pos, buf->stride,
> +						swizzle, buf->bpp, &x, &y);
> +			break;
>  		default:
>  			igt_assert(false);
>  		}
> -- 
> 2.17.1
> 

[igt-dev] [PATCH i-g-t 05/10] igt/tests: Add support for Tile4(TileF) format to kms_draw_crc

[Jeevan B]

From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

kms_draw_crc would be the first sample test to support new
format.

v2: add check for tile-4 support

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/kms_draw_crc.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/tests/i915/kms_draw_crc.c b/tests/i915/kms_draw_crc.c
index 82c368e1..33b7bdf4 100644
--- a/tests/i915/kms_draw_crc.c
+++ b/tests/i915/kms_draw_crc.c
@@ -41,25 +41,24 @@ drmModeConnectorPtr drm_connectors[MAX_CONNECTORS];
 struct buf_ops *bops;
 igt_pipe_crc_t *pipe_crc;
 
-#define N_FORMATS 3
-static const uint32_t formats[N_FORMATS] = {
+static const uint32_t formats[] = {
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_XRGB2101010,
 };
 
-#define N_MODIFIER_METHODS 3
-static const uint64_t modifiers[N_MODIFIER_METHODS] = {
+static const uint64_t modifiers[] = {
 	DRM_FORMAT_MOD_LINEAR,
 	I915_FORMAT_MOD_X_TILED,
 	I915_FORMAT_MOD_Y_TILED,
+	I915_FORMAT_MOD_4_TILED,
 };
 
 struct base_crc {
 	bool set;
 	igt_crc_t crc;
 };
-struct base_crc base_crcs[N_FORMATS];
+struct base_crc base_crcs[ARRAY_SIZE(formats)];
 
 struct modeset_params ms;
 
@@ -178,6 +177,9 @@ static void draw_method_subtest(enum igt_draw_method method,
 {
 	igt_crc_t crc;
 
+	igt_skip_on(modifier == I915_FORMAT_MOD_4_TILED &&
+		    !HAS_4TILE(intel_get_drm_devid(drm_fd)));
+
 	igt_skip_on(method == IGT_DRAW_MMAP_WC && !gem_mmap__has_wc(drm_fd));
 	igt_skip_on(method == IGT_DRAW_MMAP_GTT &&
 		    !gem_has_mappable_ggtt(drm_fd));
@@ -315,6 +317,8 @@ static const char *modifier_str(int modifier_index)
 		return "xtiled";
 	case I915_FORMAT_MOD_Y_TILED:
 		return "ytiled";
+	case I915_FORMAT_MOD_4_TILED:
+		return "4tiled";
 	default:
 		igt_assert(false);
 	}
@@ -328,9 +332,9 @@ igt_main
 	igt_fixture
 		setup_environment();
 
-	for (format_idx = 0; format_idx < N_FORMATS; format_idx++) {
+	for (format_idx = 0; format_idx < ARRAY_SIZE(formats); format_idx++) {
 	for (method = 0; method < IGT_DRAW_METHOD_COUNT; method++) {
-	for (modifier_idx = 0; modifier_idx < N_MODIFIER_METHODS; modifier_idx++) {
+	for (modifier_idx = 0; modifier_idx < ARRAY_SIZE(modifiers); modifier_idx++) {
 		igt_describe("This subtest verfies igt_draw library works "
 			     "with different modifiers, DRM_FORMATS, DRAW_METHODS.");
 		igt_subtest_f("draw-method-%s-%s-%s",
-- 
2.17.1

Re: [igt-dev] [PATCH i-g-t 05/10] igt/tests: Add support for Tile4(TileF) format to kms_draw_crc

[Lisovskiy, Stanislav]

On Fri, Feb 25, 2022 at 10:38:48AM +0530, Jeevan B wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> kms_draw_crc would be the first sample test to support new
> format.
> 
> v2: add check for tile-4 support
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  tests/i915/kms_draw_crc.c | 18 +++++++++++-------
>  1 file changed, 11 insertions(+), 7 deletions(-)
> 
> diff --git a/tests/i915/kms_draw_crc.c b/tests/i915/kms_draw_crc.c
> index 82c368e1..33b7bdf4 100644
> --- a/tests/i915/kms_draw_crc.c
> +++ b/tests/i915/kms_draw_crc.c
> @@ -41,25 +41,24 @@ drmModeConnectorPtr drm_connectors[MAX_CONNECTORS];
>  struct buf_ops *bops;
>  igt_pipe_crc_t *pipe_crc;
>  
> -#define N_FORMATS 3
> -static const uint32_t formats[N_FORMATS] = {
> +static const uint32_t formats[] = {
>  	DRM_FORMAT_XRGB8888,
>  	DRM_FORMAT_RGB565,
>  	DRM_FORMAT_XRGB2101010,
>  };
>  
> -#define N_MODIFIER_METHODS 3
> -static const uint64_t modifiers[N_MODIFIER_METHODS] = {
> +static const uint64_t modifiers[] = {
>  	DRM_FORMAT_MOD_LINEAR,
>  	I915_FORMAT_MOD_X_TILED,
>  	I915_FORMAT_MOD_Y_TILED,
> +	I915_FORMAT_MOD_4_TILED,
>  };
>  
>  struct base_crc {
>  	bool set;
>  	igt_crc_t crc;
>  };
> -struct base_crc base_crcs[N_FORMATS];
> +struct base_crc base_crcs[ARRAY_SIZE(formats)];
>  
>  struct modeset_params ms;
>  
> @@ -178,6 +177,9 @@ static void draw_method_subtest(enum igt_draw_method method,
>  {
>  	igt_crc_t crc;
>  
> +	igt_skip_on(modifier == I915_FORMAT_MOD_4_TILED &&
> +		    !HAS_4TILE(intel_get_drm_devid(drm_fd)));
> +
>  	igt_skip_on(method == IGT_DRAW_MMAP_WC && !gem_mmap__has_wc(drm_fd));
>  	igt_skip_on(method == IGT_DRAW_MMAP_GTT &&
>  		    !gem_has_mappable_ggtt(drm_fd));
> @@ -315,6 +317,8 @@ static const char *modifier_str(int modifier_index)
>  		return "xtiled";
>  	case I915_FORMAT_MOD_Y_TILED:
>  		return "ytiled";
> +	case I915_FORMAT_MOD_4_TILED:
> +		return "4tiled";
>  	default:
>  		igt_assert(false);
>  	}
> @@ -328,9 +332,9 @@ igt_main
>  	igt_fixture
>  		setup_environment();
>  
> -	for (format_idx = 0; format_idx < N_FORMATS; format_idx++) {
> +	for (format_idx = 0; format_idx < ARRAY_SIZE(formats); format_idx++) {
>  	for (method = 0; method < IGT_DRAW_METHOD_COUNT; method++) {
> -	for (modifier_idx = 0; modifier_idx < N_MODIFIER_METHODS; modifier_idx++) {
> +	for (modifier_idx = 0; modifier_idx < ARRAY_SIZE(modifiers); modifier_idx++) {
>  		igt_describe("This subtest verfies igt_draw library works "
>  			     "with different modifiers, DRM_FORMATS, DRAW_METHODS.");
>  		igt_subtest_f("draw-method-%s-%s-%s",
> -- 
> 2.17.1
> 

[igt-dev] [PATCH i-g-t 06/10] igt/tests: Add support for Tile4(TileF) format to tests/kms_plane_multiple

[Jeevan B]

Adding subtest to test new tiling format.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_plane_multiple.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
index ebadc14b..1679f7ce 100644
--- a/tests/kms_plane_multiple.c
+++ b/tests/kms_plane_multiple.c
@@ -398,6 +398,9 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
 	igt_subtest_f("atomic-pipe-%s-tiling-yf", kmstest_pipe_name(pipe))
 		test_plane_position(data, pipe, I915_FORMAT_MOD_Yf_TILED);
 
+	igt_subtest_f("atomic-pipe-%s-tiling-4", kmstest_pipe_name(pipe))
+		test_plane_position(data, pipe, I915_FORMAT_MOD_4_TILED);
+
 	igt_subtest_f("atomic-pipe-%s-tiling-none", kmstest_pipe_name(pipe))
 		test_plane_position(data, pipe, DRM_FORMAT_MOD_LINEAR);
 }
-- 
2.17.1

Re: [igt-dev] [PATCH i-g-t 06/10] igt/tests: Add support for Tile4(TileF) format to tests/kms_plane_multiple

[Lisovskiy, Stanislav]

On Fri, Feb 25, 2022 at 10:38:49AM +0530, Jeevan B wrote:
> Adding subtest to test new tiling format.
> 
> Signed-off-by: Jeevan B <jeevan.b@intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  tests/kms_plane_multiple.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
> index ebadc14b..1679f7ce 100644
> --- a/tests/kms_plane_multiple.c
> +++ b/tests/kms_plane_multiple.c
> @@ -398,6 +398,9 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
>  	igt_subtest_f("atomic-pipe-%s-tiling-yf", kmstest_pipe_name(pipe))
>  		test_plane_position(data, pipe, I915_FORMAT_MOD_Yf_TILED);
>  
> +	igt_subtest_f("atomic-pipe-%s-tiling-4", kmstest_pipe_name(pipe))
> +		test_plane_position(data, pipe, I915_FORMAT_MOD_4_TILED);
> +
>  	igt_subtest_f("atomic-pipe-%s-tiling-none", kmstest_pipe_name(pipe))
>  		test_plane_position(data, pipe, DRM_FORMAT_MOD_LINEAR);
>  }
> -- 
> 2.17.1
> 

[igt-dev] [PATCH i-g-t 07/10] igt/tests: Add support for Tile4(TileF) format to tests/kms_plane_lowres

[Jeevan B]

Adding subtest to test new tiling format.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_plane_lowres.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/kms_plane_lowres.c b/tests/kms_plane_lowres.c
index 6c0fce86..3f3f77c8 100644
--- a/tests/kms_plane_lowres.c
+++ b/tests/kms_plane_lowres.c
@@ -314,6 +314,9 @@ igt_main
 			     "high and low resolution with yf-tiling.");
 		igt_subtest_f("pipe-%s-tiling-yf", kmstest_pipe_name(pipe))
 			test_planes_on_pipe(&data, I915_FORMAT_MOD_Yf_TILED);
+
+		igt_subtest_f("pipe-%s-tiling-4", kmstest_pipe_name(pipe))
+			test_planes_on_pipe(&data, I915_FORMAT_MOD_4_TILED);
 	}
 
 	igt_fixture {
-- 
2.17.1

Re: [igt-dev] [PATCH i-g-t 07/10] igt/tests: Add support for Tile4(TileF) format to tests/kms_plane_lowres

[Lisovskiy, Stanislav]

On Fri, Feb 25, 2022 at 10:38:50AM +0530, Jeevan B wrote:
> Adding subtest to test new tiling format.
> 
> Signed-off-by: Jeevan B <jeevan.b@intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  tests/kms_plane_lowres.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/tests/kms_plane_lowres.c b/tests/kms_plane_lowres.c
> index 6c0fce86..3f3f77c8 100644
> --- a/tests/kms_plane_lowres.c
> +++ b/tests/kms_plane_lowres.c
> @@ -314,6 +314,9 @@ igt_main
>  			     "high and low resolution with yf-tiling.");
>  		igt_subtest_f("pipe-%s-tiling-yf", kmstest_pipe_name(pipe))
>  			test_planes_on_pipe(&data, I915_FORMAT_MOD_Yf_TILED);
> +
> +		igt_subtest_f("pipe-%s-tiling-4", kmstest_pipe_name(pipe))
> +			test_planes_on_pipe(&data, I915_FORMAT_MOD_4_TILED);
>  	}
>  
>  	igt_fixture {
> -- 
> 2.17.1
> 

[igt-dev] [PATCH i-g-t 08/10] igt/tests: Add support for Tile4(TileF) format to tests/kms_big_fb

[Jeevan B]

Extending the test to support new Tiling format.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/i915/kms_big_fb.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/i915/kms_big_fb.c b/tests/i915/kms_big_fb.c
index 9ebf6155..8724d606 100644
--- a/tests/i915/kms_big_fb.c
+++ b/tests/i915/kms_big_fb.c
@@ -784,6 +784,7 @@ static const struct {
 	{ I915_FORMAT_MOD_X_TILED, "x-tiled", },
 	{ I915_FORMAT_MOD_Y_TILED, "y-tiled", },
 	{ I915_FORMAT_MOD_Yf_TILED, "yf-tiled", },
+	{ I915_FORMAT_MOD_4_TILED, "4-tiled", },
 };
 
 static const struct {
-- 
2.17.1

Re: [igt-dev] [PATCH i-g-t 08/10] igt/tests: Add support for Tile4(TileF) format to tests/kms_big_fb

[Lisovskiy, Stanislav]

On Fri, Feb 25, 2022 at 10:38:51AM +0530, Jeevan B wrote:
> Extending the test to support new Tiling format.
> 
> Signed-off-by: Jeevan B <jeevan.b@intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  tests/i915/kms_big_fb.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/tests/i915/kms_big_fb.c b/tests/i915/kms_big_fb.c
> index 9ebf6155..8724d606 100644
> --- a/tests/i915/kms_big_fb.c
> +++ b/tests/i915/kms_big_fb.c
> @@ -784,6 +784,7 @@ static const struct {
>  	{ I915_FORMAT_MOD_X_TILED, "x-tiled", },
>  	{ I915_FORMAT_MOD_Y_TILED, "y-tiled", },
>  	{ I915_FORMAT_MOD_Yf_TILED, "yf-tiled", },
> +	{ I915_FORMAT_MOD_4_TILED, "4-tiled", },
>  };
>  
>  static const struct {
> -- 
> 2.17.1
> 

[igt-dev] [PATCH i-g-t 09/10] igt/tests: Add support for Tile4(TileF) format to testdisplay

[Jeevan B]

From: Matt Roper <matthew.d.roper@intel.com>

testdisplay is a great test for manual testing/debug of Tile-4; we just
need an extra parameter to enable that tiling format.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/testdisplay.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/tests/testdisplay.c b/tests/testdisplay.c
index 54327761..e9fbd260 100644
--- a/tests/testdisplay.c
+++ b/tests/testdisplay.c
@@ -593,7 +593,7 @@ static void set_termio_mode(void)
 	tcsetattr(tio_fd, TCSANOW, &tio);
 }
 
-static char optstr[] = "3Aiaf:s:d:p:mrto:j:y";
+static char optstr[] = "3Aiaf:s:d:p:mrt4o:j:y";
 static struct option long_opts[] = {
 	{"yb", 0, 0, OPT_YB},
 	{"yf", 0, 0, OPT_YF},
@@ -612,6 +612,7 @@ static const char *help_str =
 	"  -t\tuse an X-tiled framebuffer\n"
 	"  -y, --yb\n"
 	"  \tuse a Y-tiled framebuffer\n"
+	"  -4\tuse an Tile-4 framebuffer\n"
 	"  --yf\tuse a Yf-tiled framebuffer\n"
 	"  -j\tdo dpms off, optional arg to select dpms level (1-3)\n"
 	"  -r\tprint a QR code on the screen whose content is \"pass\" for the automatic test\n"
@@ -680,6 +681,9 @@ static int opt_handler(int opt, int opt_index, void *data)
 	case OPT_YF:
 		modifier = I915_FORMAT_MOD_Yf_TILED;
 		break;
+	case '4':
+		modifier = I915_FORMAT_MOD_4_TILED;
+		break;
 	case 'r':
 		qr_code = 1;
 		break;
-- 
2.17.1

Re: [igt-dev] [PATCH i-g-t 09/10] igt/tests: Add support for Tile4(TileF) format to testdisplay

[Lisovskiy, Stanislav]

On Fri, Feb 25, 2022 at 10:38:52AM +0530, Jeevan B wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> testdisplay is a great test for manual testing/debug of Tile-4; we just
> need an extra parameter to enable that tiling format.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  tests/testdisplay.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/testdisplay.c b/tests/testdisplay.c
> index 54327761..e9fbd260 100644
> --- a/tests/testdisplay.c
> +++ b/tests/testdisplay.c
> @@ -593,7 +593,7 @@ static void set_termio_mode(void)
>  	tcsetattr(tio_fd, TCSANOW, &tio);
>  }
>  
> -static char optstr[] = "3Aiaf:s:d:p:mrto:j:y";
> +static char optstr[] = "3Aiaf:s:d:p:mrt4o:j:y";
>  static struct option long_opts[] = {
>  	{"yb", 0, 0, OPT_YB},
>  	{"yf", 0, 0, OPT_YF},
> @@ -612,6 +612,7 @@ static const char *help_str =
>  	"  -t\tuse an X-tiled framebuffer\n"
>  	"  -y, --yb\n"
>  	"  \tuse a Y-tiled framebuffer\n"
> +	"  -4\tuse an Tile-4 framebuffer\n"
>  	"  --yf\tuse a Yf-tiled framebuffer\n"
>  	"  -j\tdo dpms off, optional arg to select dpms level (1-3)\n"
>  	"  -r\tprint a QR code on the screen whose content is \"pass\" for the automatic test\n"
> @@ -680,6 +681,9 @@ static int opt_handler(int opt, int opt_index, void *data)
>  	case OPT_YF:
>  		modifier = I915_FORMAT_MOD_Yf_TILED;
>  		break;
> +	case '4':
> +		modifier = I915_FORMAT_MOD_4_TILED;
> +		break;
>  	case 'r':
>  		qr_code = 1;
>  		break;
> -- 
> 2.17.1
> 

[igt-dev] [PATCH i-g-t 10/10] igt/tests: Add support for Tile4(TileF) format to kms_rotation_crc

[Jeevan B]

Adding subtest to test new tiling format.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_rotation_crc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 3f716002..50869a08 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -983,6 +983,8 @@ static const char *modifier_test_str(uint64_t modifier)
 		return "y-tiled";
 	case I915_FORMAT_MOD_Yf_TILED:
 		return "yf-tiled";
+	case I915_FORMAT_MOD_4_TILED:
+		return "4-tiled";
 	default:
 		igt_assert(0);
 	}
@@ -1041,6 +1043,8 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
 		{ I915_FORMAT_MOD_Yf_TILED, IGT_ROTATION_90 },
 		{ I915_FORMAT_MOD_Yf_TILED, IGT_ROTATION_180 },
 		{ I915_FORMAT_MOD_Yf_TILED, IGT_ROTATION_270 },
+		{ I915_FORMAT_MOD_4_TILED, IGT_ROTATION_0 },
+		{ I915_FORMAT_MOD_4_TILED, IGT_ROTATION_180 },
 		{ 0, 0 }
 	};
 
-- 
2.17.1

Re: [igt-dev] [PATCH i-g-t 10/10] igt/tests: Add support for Tile4(TileF) format to kms_rotation_crc

[Lisovskiy, Stanislav]

On Fri, Feb 25, 2022 at 10:38:53AM +0530, Jeevan B wrote:
> Adding subtest to test new tiling format.
> 
> Signed-off-by: Jeevan B <jeevan.b@intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  tests/kms_rotation_crc.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
> index 3f716002..50869a08 100644
> --- a/tests/kms_rotation_crc.c
> +++ b/tests/kms_rotation_crc.c
> @@ -983,6 +983,8 @@ static const char *modifier_test_str(uint64_t modifier)
>  		return "y-tiled";
>  	case I915_FORMAT_MOD_Yf_TILED:
>  		return "yf-tiled";
> +	case I915_FORMAT_MOD_4_TILED:
> +		return "4-tiled";
>  	default:
>  		igt_assert(0);
>  	}
> @@ -1041,6 +1043,8 @@ igt_main_args("", long_opts, help_str, opt_handler, &data)
>  		{ I915_FORMAT_MOD_Yf_TILED, IGT_ROTATION_90 },
>  		{ I915_FORMAT_MOD_Yf_TILED, IGT_ROTATION_180 },
>  		{ I915_FORMAT_MOD_Yf_TILED, IGT_ROTATION_270 },
> +		{ I915_FORMAT_MOD_4_TILED, IGT_ROTATION_0 },
> +		{ I915_FORMAT_MOD_4_TILED, IGT_ROTATION_180 },
>  		{ 0, 0 }
>  	};
>  
> -- 
> 2.17.1
> 

[igt-dev] ✓ Fi.CI.BAT: success for Tile 4 plane format support

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9871 bytes --]

== Series Details ==

Series: Tile 4 plane format support
URL   : https://patchwork.freedesktop.org/series/100721/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11285 -> IGTPW_6702
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/index.html

Participating hosts (39 -> 40)
------------------------------

  Additional (2): fi-kbl-soraka fi-pnv-d510 
  Missing    (1): fi-bdw-samus 

Known issues
------------

  Here are the changes found in IGTPW_6702 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_flink_basic@bad-flink:
    - fi-skl-6600u:       NOTRUN -> [FAIL][2] ([i915#4547])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [PASS][6] -> [INCOMPLETE][7] ([i915#3921])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@requests:
    - fi-blb-e6850:       [PASS][8] -> [DMESG-FAIL][9] ([i915#5026])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-blb-e6850/igt@i915_selftest@live@requests.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-blb-e6850/igt@i915_selftest@live@requests.html
    - fi-pnv-d510:        NOTRUN -> [DMESG-FAIL][10] ([i915#2927] / [i915#4528])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-pnv-d510/igt@i915_selftest@live@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
    - fi-cfl-8109u:       [PASS][12] -> [DMESG-WARN][13] ([i915#295]) +11 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
    - fi-pnv-d510:        NOTRUN -> [SKIP][15] ([fdo#109271]) +39 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-pnv-d510/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-pnv-d510:        NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#2403] / [i915#4312])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-pnv-d510/igt@runner@aborted.html
    - fi-blb-e6850:       NOTRUN -> [FAIL][17] ([fdo#109271] / [i915#2403] / [i915#2426] / [i915#4312])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/fi-blb-e6850/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
    - {bat-adlp-6}:       [DMESG-WARN][18] ([i915#3576]) -> [PASS][19] +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
  [i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6357 -> IGTPW_6702

  CI-20190529: 20190529
  CI_DRM_11285: 937927c7022766ecf991e0071ae055412fb3805f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6702: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/index.html
  IGT_6357: 6546304ecf053b9c5ec278ee3c210d2c6d50a3a6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@kms_big_fb@4-tiled-8bpp-rotate-0
+igt@kms_big_fb@4-tiled-8bpp-rotate-90
+igt@kms_big_fb@4-tiled-8bpp-rotate-180
+igt@kms_big_fb@4-tiled-8bpp-rotate-270
+igt@kms_big_fb@4-tiled-16bpp-rotate-0
+igt@kms_big_fb@4-tiled-16bpp-rotate-90
+igt@kms_big_fb@4-tiled-16bpp-rotate-180
+igt@kms_big_fb@4-tiled-16bpp-rotate-270
+igt@kms_big_fb@4-tiled-32bpp-rotate-0
+igt@kms_big_fb@4-tiled-32bpp-rotate-90
+igt@kms_big_fb@4-tiled-32bpp-rotate-180
+igt@kms_big_fb@4-tiled-32bpp-rotate-270
+igt@kms_big_fb@4-tiled-64bpp-rotate-0
+igt@kms_big_fb@4-tiled-64bpp-rotate-90
+igt@kms_big_fb@4-tiled-64bpp-rotate-180
+igt@kms_big_fb@4-tiled-64bpp-rotate-270
+igt@kms_big_fb@4-tiled-addfb
+igt@kms_big_fb@4-tiled-addfb-size-offset-overflow
+igt@kms_big_fb@4-tiled-addfb-size-overflow
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip
+igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip
+igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip
+igt@kms_draw_crc@draw-method-rgb565-blt-4tiled
+igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-4tiled
+igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled
+igt@kms_draw_crc@draw-method-rgb565-mmap-wc-4tiled
+igt@kms_draw_crc@draw-method-rgb565-pwrite-4tiled
+igt@kms_draw_crc@draw-method-rgb565-render-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-blt-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-pwrite-4tiled
+igt@kms_draw_crc@draw-method-xrgb8888-render-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-blt-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-4tiled
+igt@kms_draw_crc@draw-method-xrgb2101010-render-4tiled
+igt@kms_plane_lowres@pipe-a-tiling-4
+igt@kms_plane_lowres@pipe-b-tiling-4
+igt@kms_plane_lowres@pipe-c-tiling-4
+igt@kms_plane_lowres@pipe-d-tiling-4
+igt@kms_plane_lowres@pipe-e-tiling-4
+igt@kms_plane_lowres@pipe-f-tiling-4
+igt@kms_plane_multiple@atomic-pipe-a-tiling-4
+igt@kms_plane_multiple@atomic-pipe-b-tiling-4
+igt@kms_plane_multiple@atomic-pipe-c-tiling-4
+igt@kms_plane_multiple@atomic-pipe-d-tiling-4
+igt@kms_plane_multiple@atomic-pipe-e-tiling-4
+igt@kms_plane_multiple@atomic-pipe-f-tiling-4
+igt@kms_rotation_crc@primary-4-tiled-reflect-x-0
+igt@kms_rotation_crc@primary-4-tiled-reflect-x-180

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/index.html

[-- Attachment #2: Type: text/html, Size: 11752 bytes --]

[igt-dev] ✗ Fi.CI.IGT: failure for Tile 4 plane format support

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30246 bytes --]

== Series Details ==

Series: Tile 4 plane format support
URL   : https://patchwork.freedesktop.org/series/100721/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11285_full -> IGTPW_6702_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_6702_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_6702_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/index.html

Participating hosts (11 -> 8)
------------------------------

  Missing    (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6702_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-apl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-apl8/igt@gem_ctx_isolation@preservation-s3@bcs0.html

  * {igt@kms_draw_crc@draw-method-rgb565-blt-4tiled} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][3] +45 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb7/igt@kms_draw_crc@draw-method-rgb565-blt-4tiled.html

  * {igt@kms_draw_crc@draw-method-xrgb8888-pwrite-4tiled} (NEW):
    - {shard-tglu}:       NOTRUN -> [SKIP][4] +37 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglu-3/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-4tiled.html

  * {igt@kms_rotation_crc@primary-4-tiled-reflect-x-180} (NEW):
    - shard-tglb:         NOTRUN -> [SKIP][5] +44 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb3/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  
New tests
---------

  New tests have been introduced between CI_DRM_11285_full and IGTPW_6702_full:

### New IGT tests (63) ###

  * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-16bpp-rotate-180:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-16bpp-rotate-270:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-32bpp-rotate-180:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - Statuses : 7 skip(s)
    - Exec time: [0.0, 0.00] s

  * igt@kms_big_fb@4-tiled-8bpp-rotate-0:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-8bpp-rotate-180:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-8bpp-rotate-270:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_big_fb@4-tiled-addfb:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-rgb565-blt-4tiled:
    - Statuses : 5 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-4tiled:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-4tiled:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_draw_crc@draw-method-rgb565-pwrite-4tiled:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_draw_crc@draw-method-rgb565-render-4tiled:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_draw_crc@draw-method-xrgb2101010-blt-4tiled:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-4tiled:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled:
    - Statuses : 3 skip(s)
    - Exec time: [0.0, 0.00] s

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-4tiled:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-xrgb2101010-render-4tiled:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-xrgb8888-blt-4tiled:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-4tiled:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-4tiled:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-4tiled:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-xrgb8888-pwrite-4tiled:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_draw_crc@draw-method-xrgb8888-render-4tiled:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@kms_plane_lowres@pipe-a-tiling-4:
    - Statuses : 7 skip(s)
    - Exec time: [0.0] s

  * igt@kms_plane_lowres@pipe-b-tiling-4:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@kms_plane_lowres@pipe-c-tiling-4:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@kms_plane_lowres@pipe-d-tiling-4:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-4:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-4:
    - Statuses : 5 skip(s)
    - Exec time: [0.0, 0.00] s

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-4:
    - Statuses : 7 skip(s)
    - Exec time: [0.0, 0.00] s

  * igt@kms_plane_multiple@atomic-pipe-d-tiling-4:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - Statuses : 7 skip(s)
    - Exec time: [0.0, 0.09] s

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - Statuses : 7 skip(s)
    - Exec time: [0.0, 0.11] s

  

Known issues
------------

  Here are the changes found in IGTPW_6702_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@chamelium:
    - shard-tglb:         NOTRUN -> [SKIP][6] ([fdo#111827])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb7/igt@feature_discovery@chamelium.html

  * igt@feature_discovery@display-4x:
    - shard-iclb:         NOTRUN -> [SKIP][7] ([i915#1839])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb1/igt@feature_discovery@display-4x.html
    - shard-tglb:         NOTRUN -> [SKIP][8] ([i915#1839])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb6/igt@feature_discovery@display-4x.html

  * igt@gem_create@create-massive:
    - shard-apl:          NOTRUN -> [DMESG-WARN][9] ([i915#4991])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-apl3/igt@gem_create@create-massive.html
    - shard-iclb:         NOTRUN -> [DMESG-WARN][10] ([i915#4991])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb5/igt@gem_create@create-massive.html
    - shard-snb:          NOTRUN -> [DMESG-WARN][11] ([i915#4991])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-snb4/igt@gem_create@create-massive.html
    - shard-glk:          NOTRUN -> [DMESG-WARN][12] ([i915#4991])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-glk9/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@legacy-engines-queued:
    - shard-snb:          NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +3 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-snb6/igt@gem_ctx_persistence@legacy-engines-queued.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         NOTRUN -> [FAIL][14] ([i915#232])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb3/igt@gem_eio@unwedge-stress.html
    - shard-snb:          NOTRUN -> [FAIL][15] ([i915#3354])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-snb2/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-apl:          [PASS][16] -> [FAIL][17] ([i915#2842])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
    - shard-kbl:          NOTRUN -> [FAIL][18] ([i915#2842]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][19] -> [FAIL][20] ([i915#2842]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][21] ([i915#2842]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
    - shard-iclb:         NOTRUN -> [FAIL][22] ([i915#2842])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb8/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-kbl:          [PASS][23] -> [FAIL][24] ([i915#2842]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-iclb:         [PASS][25] -> [FAIL][26] ([i915#2842])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][27] ([i915#2842]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html
    - shard-iclb:         NOTRUN -> [FAIL][28] ([i915#2849])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_params@secure-non-master:
    - shard-iclb:         NOTRUN -> [SKIP][29] ([fdo#112283])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb3/igt@gem_exec_params@secure-non-master.html

  * igt@gem_exec_whisper@basic-queues-forked:
    - shard-glk:          [PASS][30] -> [DMESG-WARN][31] ([i915#118])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11285/shard-glk2/igt@gem_exec_whisper@basic-queues-forked.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-glk6/igt@gem_exec_whisper@basic-queues-forked.html

  * igt@gem_huc_copy@huc-copy:
    - shard-kbl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#2190])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl4/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#4613]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-apl8/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([i915#4613]) +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb7/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-kbl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#4613]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl7/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_pread@exhaustion:
    - shard-apl:          NOTRUN -> [WARN][36] ([i915#2658])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-apl3/igt@gem_pread@exhaustion.html
    - shard-kbl:          NOTRUN -> [WARN][37] ([i915#2658]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl7/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-tglb:         NOTRUN -> [WARN][38] ([i915#2658])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb7/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - shard-tglb:         NOTRUN -> [SKIP][39] ([i915#4270]) +3 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb1/igt@gem_pxp@regular-baseline-src-copy-readible.html
    - shard-iclb:         NOTRUN -> [SKIP][40] ([i915#4270])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb4/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_render_copy@linear-to-vebox-y-tiled:
    - shard-apl:          NOTRUN -> [SKIP][41] ([fdo#109271]) +200 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-apl7/igt@gem_render_copy@linear-to-vebox-y-tiled.html

  * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
    - shard-kbl:          NOTRUN -> [SKIP][42] ([fdo#109271]) +317 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl7/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([i915#768]) +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb8/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-tglb:         NOTRUN -> [SKIP][44] ([i915#3323])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb6/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-kbl:          NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3323])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl7/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-iclb:         NOTRUN -> [SKIP][46] ([i915#3323])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb1/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][47] ([i915#3297])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb5/igt@gem_userptr_blits@dmabuf-unsync.html
    - shard-iclb:         NOTRUN -> [SKIP][48] ([i915#3297])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb1/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-kbl:          NOTRUN -> [FAIL][49] ([i915#3318])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl4/igt@gem_userptr_blits@vma-merge.html
    - shard-tglb:         NOTRUN -> [FAIL][50] ([i915#3318])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb2/igt@gem_userptr_blits@vma-merge.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([i915#2856]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb6/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-tglb:         NOTRUN -> [SKIP][52] ([i915#2527] / [i915#2856]) +4 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb7/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-kbl:          NOTRUN -> [FAIL][53] ([i915#454])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl7/igt@i915_pm_dc@dc6-dpms.html
    - shard-tglb:         NOTRUN -> [FAIL][54] ([i915#454])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb5/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_lpsp@screens-disabled:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([i915#1902])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb2/igt@i915_pm_lpsp@screens-disabled.html
    - shard-iclb:         NOTRUN -> [SKIP][56] ([i915#1902])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb2/igt@i915_pm_lpsp@screens-disabled.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglb:         NOTRUN -> [WARN][57] ([i915#2681] / [i915#2684])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb2/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-tglb:         NOTRUN -> [SKIP][58] ([fdo#111644] / [i915#1397] / [i915#2411])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb6/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@i915_pm_rpm@modeset-pc8-residency-stress:
    - shard-tglb:         NOTRUN -> [SKIP][59] ([fdo#109506] / [i915#2411]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html

  * igt@i915_pm_rpm@pc8-residency:
    - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109293] / [fdo#109506]) +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb5/igt@i915_pm_rpm@pc8-residency.html

  * igt@i915_query@query-topology-unsupported:
    - shard-iclb:         NOTRUN -> [SKIP][61] ([fdo#109302])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb6/igt@i915_query@query-topology-unsupported.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-tglb:         NOTRUN -> [SKIP][62] ([i915#1769])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb7/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * {igt@kms_big_fb@4-tiled-8bpp-rotate-0} (NEW):
    - shard-snb:          NOTRUN -> [SKIP][63] ([fdo#109271]) +208 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-snb6/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html

  * {igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip} (NEW):
    - shard-glk:          NOTRUN -> [SKIP][64] ([fdo#109271]) +107 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-glk7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][65] ([fdo#111614]) +5 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb1/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][66] ([fdo#110725] / [fdo#111614]) +1 similar issue
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb1/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-apl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#3777]) +8 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-apl8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#3777]) +6 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
    - shard-glk:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#3777]) +5 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-glk6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][70] ([i915#3689] / [i915#3886]) +4 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb3/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][71] ([fdo#111615] / [i915#3689]) +7 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb7/igt@kms_ccs@pipe-b-bad-pixel-format-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#3886]) +12 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-apl3/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#3886]) +18 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl3/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][74] ([fdo#109278] / [i915#3886]) +6 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb8/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3886]) +4 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-glk6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][76] ([i915#3689]) +7 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb2/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-iclb:         NOTRUN -> [SKIP][77] ([i915#3742])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb8/igt@kms_cdclk@mode-transition.html
    - shard-tglb:         NOTRUN -> [SKIP][78] ([i915#3742])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb1/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium@dp-crc-fast:
    - shard-glk:          NOTRUN -> [SKIP][79] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-glk2/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@dp-hpd-storm:
    - shard-iclb:         NOTRUN -> [SKIP][80] ([fdo#109284] / [fdo#111827]) +13 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb7/igt@kms_chamelium@dp-hpd-storm.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +15 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-apl4/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-aspect-ratio:
    - shard-tglb:         NOTRUN -> [SKIP][82] ([fdo#109284] / [fdo#111827]) +24 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb1/igt@kms_chamelium@hdmi-aspect-ratio.html

  * igt@kms_chamelium@vga-hpd-without-ddc:
    - shard-kbl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [fdo#111827]) +23 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl1/igt@kms_chamelium@vga-hpd-without-ddc.html

  * igt@kms_color@pipe-d-ctm-blue-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][84] ([fdo#109278] / [i915#1149])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb8/igt@kms_color@pipe-d-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-c-ctm-limited-range:
    - shard-snb:          NOTRUN -> [SKIP][85] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-snb7/igt@kms_color_chamelium@pipe-c-ctm-limited-range.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-iclb:         NOTRUN -> [SKIP][86] ([i915#3116])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb5/igt@kms_content_protection@dp-mst-type-1.html
    - shard-tglb:         NOTRUN -> [SKIP][87] ([i915#3116] / [i915#3299])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb1/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@legacy:
    - shard-kbl:          NOTRUN -> [TIMEOUT][88] ([i915#1319]) +2 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl1/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@srm:
    - shard-iclb:         NOTRUN -> [SKIP][89] ([fdo#109300] / [fdo#111066])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb1/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@uevent:
    - shard-tglb:         NOTRUN -> [SKIP][90] ([i915#1063]) +3 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb1/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][91] ([i915#3319]) +7 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x170-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([fdo#109279] / [i915#3359]) +3 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-512x170-onscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][93] ([i915#180]) +2 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-512x512-random:
    - shard-iclb:         NOTRUN -> [SKIP][94] ([fdo#109278] / [fdo#109279])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb1/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html

  * igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement:
    - shard-iclb:         NOTRUN -> [SKIP][95] ([fdo#109278]) +31 similar issues
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb2/igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][96] ([i915#3359]) +9 similar issues
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-iclb:         NOTRUN -> [SKIP][97] ([fdo#109274] / [fdo#109278]) +4 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-iclb2/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-tglb:         NOTRUN -> [SKIP][98] ([i915#4103])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/shard-tglb2/igt@kms_cursor_legacy@short-busy-flip-before-cur

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6702/index.html

[-- Attachment #2: Type: text/html, Size: 35231 bytes --]