[igt-dev] [PATCH i-g-t 0/2] Add PVC support for gpgpu fill

[igt-dev] [PATCH i-g-t 0/2] Add PVC support for gpgpu fill

[Zbigniew Kempczyński]

Used both for i915 and xe.

Dominik Grzegorzek (1):
  lib/gpgpu_fill/xehpc: Adjust gpgpu_fillfunc for PVC

Zbigniew Kempczyński (1):
  lib/intel_batchbuffer: Use COMPUTE instead RENDER engine for Xe on PVC

 lib/gpgpu_fill.c                              | 23 +++++++++++++++++++
 lib/gpgpu_fill.h                              |  8 +++++++
 lib/gpu_cmds.c                                |  3 ++-
 .../shaders/gpgpu/gen12p72_gpgpu_kernel.asm   | 12 ++++++++++
 lib/intel_batchbuffer.c                       |  9 ++++++--
 5 files changed, 52 insertions(+), 3 deletions(-)
 create mode 100644 lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm

-- 
2.34.1

[igt-dev] [PATCH i-g-t 1/2] lib/gpgpu_fill/xehpc: Adjust gpgpu_fillfunc for PVC

[Zbigniew Kempczyński]

From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>

gpgpu_fillfunc for XEHPSDV can be reused for PVC with minor changes.
PVC COMPUTE_WALKER instruction has additional restriction. Message
SIMD(dw4:17) has to be equal to Thread SIMD.(SIMD16 in our case).
PVC also required a kernel recompilation.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Christoph Manszewski <christoph.manszewski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 lib/gpgpu_fill.c                              | 23 +++++++++++++++++++
 lib/gpgpu_fill.h                              |  8 +++++++
 lib/gpu_cmds.c                                |  3 ++-
 .../shaders/gpgpu/gen12p72_gpgpu_kernel.asm   | 12 ++++++++++
 lib/intel_batchbuffer.c                       |  4 +++-
 5 files changed, 48 insertions(+), 2 deletions(-)
 create mode 100644 lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm

diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
index 4db8775145..d854fbf7a0 100644
--- a/lib/gpgpu_fill.c
+++ b/lib/gpgpu_fill.c
@@ -112,6 +112,18 @@ static const uint32_t xehp_gpgpu_kernel[][4] = {
 	{ 0x00030031, 0x00000004, 0x3000500c, 0x00000000 },
 };
 
+static const uint32_t xehpc_gpgpu_kernel[][4] = {
+	{ 0x00080061, 0x01050000, 0x00000104, 0x00000000 },
+	{ 0x00000069, 0x02058220, 0x02000014, 0x00000004 },
+	{ 0x00000061, 0x02150220, 0x00000064, 0x00000000 },
+	{ 0x000c0061, 0x04050220, 0x00460005, 0x00000000 },
+	{ 0x00041a61, 0x04050220, 0x00220205, 0x00000000 },
+	{ 0x00000061, 0x04254220, 0x00000000, 0x0000000f },
+	{ 0x00101e61, 0x05050220, 0x00000104, 0x00000000 },
+	{ 0x00132031, 0x00000000, 0xc0000414, 0x02a00000 },
+	{ 0x000c0031, 0x00000004, 0x3000500c, 0x00000000 },
+};
+
 /*
  * This sets up the gpgpu pipeline,
  *
@@ -377,3 +389,14 @@ void xehp_gpgpu_fillfunc(int i915,
 			      xehp_gpgpu_kernel,
 			      sizeof(xehp_gpgpu_kernel));
 }
+
+void xehpc_gpgpu_fillfunc(int i915,
+			  struct intel_buf *buf,
+			  unsigned int x, unsigned int y,
+			  unsigned int width, unsigned int height,
+			  uint8_t color)
+{
+	__xehp_gpgpu_fillfunc(i915, buf, x, y, width, height, color,
+			      xehpc_gpgpu_kernel,
+			      sizeof(xehpc_gpgpu_kernel));
+}
diff --git a/lib/gpgpu_fill.h b/lib/gpgpu_fill.h
index 3d199acd63..f81cd0b53c 100644
--- a/lib/gpgpu_fill.h
+++ b/lib/gpgpu_fill.h
@@ -67,4 +67,12 @@ xehp_gpgpu_fillfunc(int i915,
 		    unsigned int x, unsigned int y,
 		    unsigned int width, unsigned int height,
 		    uint8_t color);
+
+void
+xehpc_gpgpu_fillfunc(int i915,
+		     struct intel_buf *dst,
+		     unsigned int x, unsigned int y,
+		     unsigned int width, unsigned int height,
+		     uint8_t color);
+
 #endif /* GPGPU_FILL_H */
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index afb26d2990..1f321ae4a0 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -975,7 +975,8 @@ xehp_emit_compute_walk(struct intel_bb *ibb,
 	intel_bb_out(ibb, 0); /* indirect data offset */	//dw3
 
 	/* SIMD size */
-	intel_bb_out(ibb, 1 << 30 | 1 << 25); /* SIMD16 | enable inline */ //dw4
+	/* SIMD16 | enable inline | Message SIMD16 */
+	intel_bb_out(ibb, 1 << 30 | 1 << 25 | 1 << 17);		//dw4
 
 	/* Execution mask */
 	intel_bb_out(ibb, 0xffffffff);				//dw5
diff --git a/lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm b/lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm
new file mode 100644
index 0000000000..52699a475e
--- /dev/null
+++ b/lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm
@@ -0,0 +1,12 @@
+L0:
+         mov (4|M0)               r1.0<1>:ub    r1.0<0;1,0>:ub
+         shl (1|M0)               r2.0<1>:ud    r0.1<0;1,0>:ud    0x4:ud
+         mov (1|M0)               r2.1<1>:ud    r0.6<0;1,0>:ud
+         mov (8|M0)               r4.0<1>:ud    r0.0<8;8,1>:ud
+         mov (2|M0)               r4.0<1>:ud    r2.0<2;2,1>:ud                   {I@2}
+         mov (1|M0)               r4.2<1>:ud    0xF:ud
+         mov (16|M0)              r5.0<1>:ud    r1.0<0;1,0>:ud                   {I@6}
+(W)      sync.nop                             null                             {I@1}
+         send.dc1 (16|M0)         null     r4      null:0    0x0         0x40A8000  {$0} //    wr:2h+0, rd:0, Media Block Write msc:0, to #0
+         send.gtwy (8|M0)         null     r80     null:0    0x0         0x02000000 {EOT}
+L176:
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index dfccc4f4ac..9f65536173 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -755,7 +755,9 @@ igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid)
 {
 	igt_fillfunc_t fill = NULL;
 
-	if (intel_graphics_ver(devid) >= IP_VER(12, 50))
+	if (intel_graphics_ver(devid) >= IP_VER(12, 60))
+		fill = xehpc_gpgpu_fillfunc;
+	else if (intel_graphics_ver(devid) >= IP_VER(12, 50))
 		fill = xehp_gpgpu_fillfunc;
 	else if (IS_GEN12(devid))
 		fill = gen12_gpgpu_fillfunc;
-- 
2.34.1

Re: [igt-dev] [PATCH i-g-t 1/2] lib/gpgpu_fill/xehpc: Adjust gpgpu_fillfunc for PVC

[Manszewski, Christoph]

Hi Zbigniew,

On 29.05.2023 18:54, Zbigniew Kempczyński wrote:
> From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> 
> gpgpu_fillfunc for XEHPSDV can be reused for PVC with minor changes.
> PVC COMPUTE_WALKER instruction has additional restriction. Message
> SIMD(dw4:17) has to be equal to Thread SIMD.(SIMD16 in our case).
> PVC also required a kernel recompilation.
> 
> Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Christoph Manszewski <christoph.manszewski@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
>   lib/gpgpu_fill.c                              | 23 +++++++++++++++++++
>   lib/gpgpu_fill.h                              |  8 +++++++
>   lib/gpu_cmds.c                                |  3 ++-
>   .../shaders/gpgpu/gen12p72_gpgpu_kernel.asm   | 12 ++++++++++
>   lib/intel_batchbuffer.c                       |  4 +++-
>   5 files changed, 48 insertions(+), 2 deletions(-)
>   create mode 100644 lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm
> 
> diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
> index 4db8775145..d854fbf7a0 100644
> --- a/lib/gpgpu_fill.c
> +++ b/lib/gpgpu_fill.c
> @@ -112,6 +112,18 @@ static const uint32_t xehp_gpgpu_kernel[][4] = {
>   	{ 0x00030031, 0x00000004, 0x3000500c, 0x00000000 },
>   };
>   
> +static const uint32_t xehpc_gpgpu_kernel[][4] = {
> +	{ 0x00080061, 0x01050000, 0x00000104, 0x00000000 },
> +	{ 0x00000069, 0x02058220, 0x02000014, 0x00000004 },
> +	{ 0x00000061, 0x02150220, 0x00000064, 0x00000000 },
> +	{ 0x000c0061, 0x04050220, 0x00460005, 0x00000000 },
> +	{ 0x00041a61, 0x04050220, 0x00220205, 0x00000000 },
> +	{ 0x00000061, 0x04254220, 0x00000000, 0x0000000f },
> +	{ 0x00101e61, 0x05050220, 0x00000104, 0x00000000 },
> +	{ 0x00132031, 0x00000000, 0xc0000414, 0x02a00000 },
> +	{ 0x000c0031, 0x00000004, 0x3000500c, 0x00000000 },
> +};
> +
>   /*
>    * This sets up the gpgpu pipeline,
>    *
> @@ -377,3 +389,14 @@ void xehp_gpgpu_fillfunc(int i915,
>   			      xehp_gpgpu_kernel,
>   			      sizeof(xehp_gpgpu_kernel));
>   }
> +
> +void xehpc_gpgpu_fillfunc(int i915,
> +			  struct intel_buf *buf,
> +			  unsigned int x, unsigned int y,
> +			  unsigned int width, unsigned int height,
> +			  uint8_t color)
> +{
> +	__xehp_gpgpu_fillfunc(i915, buf, x, y, width, height, color,
> +			      xehpc_gpgpu_kernel,
> +			      sizeof(xehpc_gpgpu_kernel));
> +}
> diff --git a/lib/gpgpu_fill.h b/lib/gpgpu_fill.h
> index 3d199acd63..f81cd0b53c 100644
> --- a/lib/gpgpu_fill.h
> +++ b/lib/gpgpu_fill.h
> @@ -67,4 +67,12 @@ xehp_gpgpu_fillfunc(int i915,
>   		    unsigned int x, unsigned int y,
>   		    unsigned int width, unsigned int height,
>   		    uint8_t color);
> +
> +void
> +xehpc_gpgpu_fillfunc(int i915,
> +		     struct intel_buf *dst,
> +		     unsigned int x, unsigned int y,
> +		     unsigned int width, unsigned int height,
> +		     uint8_t color);
> +
>   #endif /* GPGPU_FILL_H */
> diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
> index afb26d2990..1f321ae4a0 100644
> --- a/lib/gpu_cmds.c
> +++ b/lib/gpu_cmds.c
> @@ -975,7 +975,8 @@ xehp_emit_compute_walk(struct intel_bb *ibb,
>   	intel_bb_out(ibb, 0); /* indirect data offset */	//dw3
>   
>   	/* SIMD size */
> -	intel_bb_out(ibb, 1 << 30 | 1 << 25); /* SIMD16 | enable inline */ //dw4
> +	/* SIMD16 | enable inline | Message SIMD16 */
> +	intel_bb_out(ibb, 1 << 30 | 1 << 25 | 1 << 17);		//dw4
>   
>   	/* Execution mask */
>   	intel_bb_out(ibb, 0xffffffff);				//dw5
> diff --git a/lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm b/lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm
> new file mode 100644
> index 0000000000..52699a475e
> --- /dev/null
> +++ b/lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm

Nit: shouldn't this be called 'xehpc_gpgpu_kernel'?

Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>

Christoph


> @@ -0,0 +1,12 @@
> +L0:
> +         mov (4|M0)               r1.0<1>:ub    r1.0<0;1,0>:ub
> +         shl (1|M0)               r2.0<1>:ud    r0.1<0;1,0>:ud    0x4:ud
> +         mov (1|M0)               r2.1<1>:ud    r0.6<0;1,0>:ud
> +         mov (8|M0)               r4.0<1>:ud    r0.0<8;8,1>:ud
> +         mov (2|M0)               r4.0<1>:ud    r2.0<2;2,1>:ud                   {I@2}
> +         mov (1|M0)               r4.2<1>:ud    0xF:ud
> +         mov (16|M0)              r5.0<1>:ud    r1.0<0;1,0>:ud                   {I@6}
> +(W)      sync.nop                             null                             {I@1}
> +         send.dc1 (16|M0)         null     r4      null:0    0x0         0x40A8000  {$0} //    wr:2h+0, rd:0, Media Block Write msc:0, to #0
> +         send.gtwy (8|M0)         null     r80     null:0    0x0         0x02000000 {EOT}
> +L176:
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index dfccc4f4ac..9f65536173 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -755,7 +755,9 @@ igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid)
>   {
>   	igt_fillfunc_t fill = NULL;
>   
> -	if (intel_graphics_ver(devid) >= IP_VER(12, 50))
> +	if (intel_graphics_ver(devid) >= IP_VER(12, 60))
> +		fill = xehpc_gpgpu_fillfunc;
> +	else if (intel_graphics_ver(devid) >= IP_VER(12, 50))
>   		fill = xehp_gpgpu_fillfunc;
>   	else if (IS_GEN12(devid))
>   		fill = gen12_gpgpu_fillfunc;

Re: [igt-dev] [PATCH i-g-t 1/2] lib/gpgpu_fill/xehpc: Adjust gpgpu_fillfunc for PVC

[Zbigniew Kempczyński]

On Tue, May 30, 2023 at 04:53:05PM +0200, Manszewski, Christoph wrote:
> Hi Zbigniew,
> 
> On 29.05.2023 18:54, Zbigniew Kempczyński wrote:
> > From: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> > 
> > gpgpu_fillfunc for XEHPSDV can be reused for PVC with minor changes.
> > PVC COMPUTE_WALKER instruction has additional restriction. Message
> > SIMD(dw4:17) has to be equal to Thread SIMD.(SIMD16 in our case).
> > PVC also required a kernel recompilation.
> > 
> > Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Cc: Christoph Manszewski <christoph.manszewski@intel.com>
> > Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> > ---
> >   lib/gpgpu_fill.c                              | 23 +++++++++++++++++++
> >   lib/gpgpu_fill.h                              |  8 +++++++
> >   lib/gpu_cmds.c                                |  3 ++-
> >   .../shaders/gpgpu/gen12p72_gpgpu_kernel.asm   | 12 ++++++++++
> >   lib/intel_batchbuffer.c                       |  4 +++-
> >   5 files changed, 48 insertions(+), 2 deletions(-)
> >   create mode 100644 lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm
> > 
> > diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
> > index 4db8775145..d854fbf7a0 100644
> > --- a/lib/gpgpu_fill.c
> > +++ b/lib/gpgpu_fill.c
> > @@ -112,6 +112,18 @@ static const uint32_t xehp_gpgpu_kernel[][4] = {
> >   	{ 0x00030031, 0x00000004, 0x3000500c, 0x00000000 },
> >   };
> > +static const uint32_t xehpc_gpgpu_kernel[][4] = {
> > +	{ 0x00080061, 0x01050000, 0x00000104, 0x00000000 },
> > +	{ 0x00000069, 0x02058220, 0x02000014, 0x00000004 },
> > +	{ 0x00000061, 0x02150220, 0x00000064, 0x00000000 },
> > +	{ 0x000c0061, 0x04050220, 0x00460005, 0x00000000 },
> > +	{ 0x00041a61, 0x04050220, 0x00220205, 0x00000000 },
> > +	{ 0x00000061, 0x04254220, 0x00000000, 0x0000000f },
> > +	{ 0x00101e61, 0x05050220, 0x00000104, 0x00000000 },
> > +	{ 0x00132031, 0x00000000, 0xc0000414, 0x02a00000 },
> > +	{ 0x000c0031, 0x00000004, 0x3000500c, 0x00000000 },
> > +};
> > +
> >   /*
> >    * This sets up the gpgpu pipeline,
> >    *
> > @@ -377,3 +389,14 @@ void xehp_gpgpu_fillfunc(int i915,
> >   			      xehp_gpgpu_kernel,
> >   			      sizeof(xehp_gpgpu_kernel));
> >   }
> > +
> > +void xehpc_gpgpu_fillfunc(int i915,
> > +			  struct intel_buf *buf,
> > +			  unsigned int x, unsigned int y,
> > +			  unsigned int width, unsigned int height,
> > +			  uint8_t color)
> > +{
> > +	__xehp_gpgpu_fillfunc(i915, buf, x, y, width, height, color,
> > +			      xehpc_gpgpu_kernel,
> > +			      sizeof(xehpc_gpgpu_kernel));
> > +}
> > diff --git a/lib/gpgpu_fill.h b/lib/gpgpu_fill.h
> > index 3d199acd63..f81cd0b53c 100644
> > --- a/lib/gpgpu_fill.h
> > +++ b/lib/gpgpu_fill.h
> > @@ -67,4 +67,12 @@ xehp_gpgpu_fillfunc(int i915,
> >   		    unsigned int x, unsigned int y,
> >   		    unsigned int width, unsigned int height,
> >   		    uint8_t color);
> > +
> > +void
> > +xehpc_gpgpu_fillfunc(int i915,
> > +		     struct intel_buf *dst,
> > +		     unsigned int x, unsigned int y,
> > +		     unsigned int width, unsigned int height,
> > +		     uint8_t color);
> > +
> >   #endif /* GPGPU_FILL_H */
> > diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
> > index afb26d2990..1f321ae4a0 100644
> > --- a/lib/gpu_cmds.c
> > +++ b/lib/gpu_cmds.c
> > @@ -975,7 +975,8 @@ xehp_emit_compute_walk(struct intel_bb *ibb,
> >   	intel_bb_out(ibb, 0); /* indirect data offset */	//dw3
> >   	/* SIMD size */
> > -	intel_bb_out(ibb, 1 << 30 | 1 << 25); /* SIMD16 | enable inline */ //dw4
> > +	/* SIMD16 | enable inline | Message SIMD16 */
> > +	intel_bb_out(ibb, 1 << 30 | 1 << 25 | 1 << 17);		//dw4
> >   	/* Execution mask */
> >   	intel_bb_out(ibb, 0xffffffff);				//dw5
> > diff --git a/lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm b/lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm
> > new file mode 100644
> > index 0000000000..52699a475e
> > --- /dev/null
> > +++ b/lib/i915/shaders/gpgpu/gen12p72_gpgpu_kernel.asm
> 
> Nit: shouldn't this be called 'xehpc_gpgpu_kernel'?

Definitely. Thanks for spotting this. Thank you for the review.

--
Zbigniew

> 
> Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>
> 
> Christoph
> 
> 
> > @@ -0,0 +1,12 @@
> > +L0:
> > +         mov (4|M0)               r1.0<1>:ub    r1.0<0;1,0>:ub
> > +         shl (1|M0)               r2.0<1>:ud    r0.1<0;1,0>:ud    0x4:ud
> > +         mov (1|M0)               r2.1<1>:ud    r0.6<0;1,0>:ud
> > +         mov (8|M0)               r4.0<1>:ud    r0.0<8;8,1>:ud
> > +         mov (2|M0)               r4.0<1>:ud    r2.0<2;2,1>:ud                   {I@2}
> > +         mov (1|M0)               r4.2<1>:ud    0xF:ud
> > +         mov (16|M0)              r5.0<1>:ud    r1.0<0;1,0>:ud                   {I@6}
> > +(W)      sync.nop                             null                             {I@1}
> > +         send.dc1 (16|M0)         null     r4      null:0    0x0         0x40A8000  {$0} //    wr:2h+0, rd:0, Media Block Write msc:0, to #0
> > +         send.gtwy (8|M0)         null     r80     null:0    0x0         0x02000000 {EOT}
> > +L176:
> > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> > index dfccc4f4ac..9f65536173 100644
> > --- a/lib/intel_batchbuffer.c
> > +++ b/lib/intel_batchbuffer.c
> > @@ -755,7 +755,9 @@ igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid)
> >   {
> >   	igt_fillfunc_t fill = NULL;
> > -	if (intel_graphics_ver(devid) >= IP_VER(12, 50))
> > +	if (intel_graphics_ver(devid) >= IP_VER(12, 60))
> > +		fill = xehpc_gpgpu_fillfunc;
> > +	else if (intel_graphics_ver(devid) >= IP_VER(12, 50))
> >   		fill = xehp_gpgpu_fillfunc;
> >   	else if (IS_GEN12(devid))
> >   		fill = gen12_gpgpu_fillfunc;

[igt-dev] [PATCH i-g-t 2/2] lib/intel_batchbuffer: Use COMPUTE instead RENDER engine for Xe on PVC

[Zbigniew Kempczyński]

For gpgpu fill currently we select I915_EXEC_RENDER which is correct
as pipeline selection allows to submit compute job on it. However
newer platforms like PVC have no render engine so replacing to compute
engine is necessary. At the moment this is workaround - more rework
in intel-bb is necessary to better support both - i915 and xe.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 lib/intel_batchbuffer.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 9f65536173..71f62973c8 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -2315,7 +2315,10 @@ __xe_bb_exec(struct intel_bb *ibb, uint64_t flags, bool sync)
 			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
 			break;
 		case I915_EXEC_RENDER:
-			inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
+			if (IS_PONTEVECCHIO(xe_dev_id(ibb->fd)))
+				inst.engine_class = DRM_XE_ENGINE_CLASS_COMPUTE;
+			else
+				inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
 			break;
 		case I915_EXEC_VEBOX:
 			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;
-- 
2.34.1

Re: [igt-dev] [PATCH i-g-t 2/2] lib/intel_batchbuffer: Use COMPUTE instead RENDER engine for Xe on PVC

[Manszewski, Christoph]

Hi Zbigniew,

On 29.05.2023 18:54, Zbigniew Kempczyński wrote:
> For gpgpu fill currently we select I915_EXEC_RENDER which is correct
> as pipeline selection allows to submit compute job on it. However
> newer platforms like PVC have no render engine so replacing to compute
> engine is necessary. At the moment this is workaround - more rework
> in intel-bb is necessary to better support both - i915 and xe.

[PATCH i-g-t v3] lib/intel_bb: Enable custom engine support for xe
makes it possible to provide custom engines. Let me know what you think.

Christoph


> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
>   lib/intel_batchbuffer.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index 9f65536173..71f62973c8 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -2315,7 +2315,10 @@ __xe_bb_exec(struct intel_bb *ibb, uint64_t flags, bool sync)
>   			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
>   			break;
>   		case I915_EXEC_RENDER:
> -			inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
> +			if (IS_PONTEVECCHIO(xe_dev_id(ibb->fd)))
> +				inst.engine_class = DRM_XE_ENGINE_CLASS_COMPUTE;
> +			else
> +				inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
>   			break;
>   		case I915_EXEC_VEBOX:
>   			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;

Re: [igt-dev] [PATCH i-g-t 2/2] lib/intel_batchbuffer: Use COMPUTE instead RENDER engine for Xe on PVC

[Zbigniew Kempczyński]

On Tue, May 30, 2023 at 09:13:39AM +0200, Manszewski, Christoph wrote:
> Hi Zbigniew,
> 
> On 29.05.2023 18:54, Zbigniew Kempczyński wrote:
> > For gpgpu fill currently we select I915_EXEC_RENDER which is correct
> > as pipeline selection allows to submit compute job on it. However
> > newer platforms like PVC have no render engine so replacing to compute
> > engine is necessary. At the moment this is workaround - more rework
> > in intel-bb is necessary to better support both - i915 and xe.
> 
> [PATCH i-g-t v3] lib/intel_bb: Enable custom engine support for xe
> makes it possible to provide custom engines. Let me know what you think.

Still we're using intel_bb_exec(I915_EXEC_RENDER, ...) on gpgpu what
means we need to do conditionals there or introduce engine translation
layer in intel-bb. I'm going to convert current argument passing model
to designated initializers used in igt spin factory. But this doesn't
conflict your change which I'm going to review today.

--
Zbigniew

> 
> Christoph
> 
> 
> > 
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> > ---
> >   lib/intel_batchbuffer.c | 5 ++++-
> >   1 file changed, 4 insertions(+), 1 deletion(-)
> > 
> > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> > index 9f65536173..71f62973c8 100644
> > --- a/lib/intel_batchbuffer.c
> > +++ b/lib/intel_batchbuffer.c
> > @@ -2315,7 +2315,10 @@ __xe_bb_exec(struct intel_bb *ibb, uint64_t flags, bool sync)
> >   			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
> >   			break;
> >   		case I915_EXEC_RENDER:
> > -			inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
> > +			if (IS_PONTEVECCHIO(xe_dev_id(ibb->fd)))
> > +				inst.engine_class = DRM_XE_ENGINE_CLASS_COMPUTE;
> > +			else
> > +				inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
> >   			break;
> >   		case I915_EXEC_VEBOX:
> >   			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;

Re: [igt-dev] [PATCH i-g-t 2/2] lib/intel_batchbuffer: Use COMPUTE instead RENDER engine for Xe on PVC

[Manszewski, Christoph]

On 30.05.2023 14:25, Zbigniew Kempczyński wrote:
> On Tue, May 30, 2023 at 09:13:39AM +0200, Manszewski, Christoph wrote:
>> Hi Zbigniew,
>>
>> On 29.05.2023 18:54, Zbigniew Kempczyński wrote:
>>> For gpgpu fill currently we select I915_EXEC_RENDER which is correct
>>> as pipeline selection allows to submit compute job on it. However
>>> newer platforms like PVC have no render engine so replacing to compute
>>> engine is necessary. At the moment this is workaround - more rework
>>> in intel-bb is necessary to better support both - i915 and xe.
>>
>> [PATCH i-g-t v3] lib/intel_bb: Enable custom engine support for xe
>> makes it possible to provide custom engines. Let me know what you think.
> 
> Still we're using intel_bb_exec(I915_EXEC_RENDER, ...) on gpgpu what

True.


> means we need to do conditionals there or introduce engine translation
> layer in intel-bb. I'm going to convert current argument passing model
> to designated initializers used in igt spin factory. But this doesn't
> conflict your change which I'm going to review today.

Agreed, moreover having these two changes coexisting leaves the choice 
to the user, whether he wants to provide a custom engine, or rely on 
legacy mode.

Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>

Christoph


> 
> --
> Zbigniew
> 
>>
>> Christoph
>>
>>
>>>
>>> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>>> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
>>> ---
>>>    lib/intel_batchbuffer.c | 5 ++++-
>>>    1 file changed, 4 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
>>> index 9f65536173..71f62973c8 100644
>>> --- a/lib/intel_batchbuffer.c
>>> +++ b/lib/intel_batchbuffer.c
>>> @@ -2315,7 +2315,10 @@ __xe_bb_exec(struct intel_bb *ibb, uint64_t flags, bool sync)
>>>    			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
>>>    			break;
>>>    		case I915_EXEC_RENDER:
>>> -			inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
>>> +			if (IS_PONTEVECCHIO(xe_dev_id(ibb->fd)))
>>> +				inst.engine_class = DRM_XE_ENGINE_CLASS_COMPUTE;
>>> +			else
>>> +				inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
>>>    			break;
>>>    		case I915_EXEC_VEBOX:
>>>    			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;

Re: [igt-dev] [PATCH i-g-t 2/2] lib/intel_batchbuffer: Use COMPUTE instead RENDER engine for Xe on PVC

[Zbigniew Kempczyński]

On Tue, May 30, 2023 at 04:50:35PM +0200, Manszewski, Christoph wrote:
> 
> 
> On 30.05.2023 14:25, Zbigniew Kempczyński wrote:
> > On Tue, May 30, 2023 at 09:13:39AM +0200, Manszewski, Christoph wrote:
> > > Hi Zbigniew,
> > > 
> > > On 29.05.2023 18:54, Zbigniew Kempczyński wrote:
> > > > For gpgpu fill currently we select I915_EXEC_RENDER which is correct
> > > > as pipeline selection allows to submit compute job on it. However
> > > > newer platforms like PVC have no render engine so replacing to compute
> > > > engine is necessary. At the moment this is workaround - more rework
> > > > in intel-bb is necessary to better support both - i915 and xe.
> > > 
> > > [PATCH i-g-t v3] lib/intel_bb: Enable custom engine support for xe
> > > makes it possible to provide custom engines. Let me know what you think.
> > 
> > Still we're using intel_bb_exec(I915_EXEC_RENDER, ...) on gpgpu what
> 
> True.
> 
> 
> > means we need to do conditionals there or introduce engine translation
> > layer in intel-bb. I'm going to convert current argument passing model
> > to designated initializers used in igt spin factory. But this doesn't
> > conflict your change which I'm going to review today.
> 
> Agreed, moreover having these two changes coexisting leaves the choice to
> the user, whether he wants to provide a custom engine, or rely on legacy
> mode.

Yes, but I think this needs some rework in this area.

Thank you for the review.

--
Zbigniew

> 
> Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com>
> 
> Christoph
> 
> 
> > 
> > --
> > Zbigniew
> > 
> > > 
> > > Christoph
> > > 
> > > 
> > > > 
> > > > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > > Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> > > > ---
> > > >    lib/intel_batchbuffer.c | 5 ++++-
> > > >    1 file changed, 4 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> > > > index 9f65536173..71f62973c8 100644
> > > > --- a/lib/intel_batchbuffer.c
> > > > +++ b/lib/intel_batchbuffer.c
> > > > @@ -2315,7 +2315,10 @@ __xe_bb_exec(struct intel_bb *ibb, uint64_t flags, bool sync)
> > > >    			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
> > > >    			break;
> > > >    		case I915_EXEC_RENDER:
> > > > -			inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
> > > > +			if (IS_PONTEVECCHIO(xe_dev_id(ibb->fd)))
> > > > +				inst.engine_class = DRM_XE_ENGINE_CLASS_COMPUTE;
> > > > +			else
> > > > +				inst.engine_class = DRM_XE_ENGINE_CLASS_RENDER;
> > > >    			break;
> > > >    		case I915_EXEC_VEBOX:
> > > >    			inst.engine_class = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;

[igt-dev] ✓ Fi.CI.BAT: success for Add PVC support for gpgpu fill

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3781 bytes --]

== Series Details ==

Series: Add PVC support for gpgpu fill
URL   : https://patchwork.freedesktop.org/series/118520/
State : success

== Summary ==

CI Bug Log - changes from IGT_7310 -> IGTPW_9065
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/index.html

Participating hosts (38 -> 35)
------------------------------

  Missing    (3): fi-kbl-soraka fi-kbl-8809g bat-dg1-5 

Known issues
------------

  Here are the changes found in IGTPW_9065 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - bat-jsl-3:          [PASS][1] -> [ABORT][2] ([i915#5122])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_selftest@live@requests:
    - bat-rpls-1:         [PASS][3] -> [ABORT][4] ([i915#7911] / [i915#7920])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/bat-rpls-1/igt@i915_selftest@live@requests.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/bat-rpls-1/igt@i915_selftest@live@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-jsl-3:          [PASS][5] -> [FAIL][6] ([fdo#103375])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - {bat-mtlp-6}:       [ABORT][7] ([i915#8180]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/bat-mtlp-6/igt@core_hotunplug@unbind-rebind.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/bat-mtlp-6/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_selftest@live@mman:
    - bat-rpls-2:         [TIMEOUT][9] ([i915#6794] / [i915#7392]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/bat-rpls-2/igt@i915_selftest@live@mman.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/bat-rpls-2/igt@i915_selftest@live@mman.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
  [i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
  [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
  [i915#8180]: https://gitlab.freedesktop.org/drm/intel/issues/8180


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7310 -> IGTPW_9065

  CI-20190529: 20190529
  CI_DRM_13200: 0ae4ee2c735979030a0219218081eee661606921 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9065: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/index.html
  IGT_7310: 2f9acfea5e3a93303f71cbda6e80ba64b8d75a4d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/index.html

[-- Attachment #2: Type: text/html, Size: 4159 bytes --]

[igt-dev] ✓ Fi.CI.IGT: success for Add PVC support for gpgpu fill

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 16366 bytes --]

== Series Details ==

Series: Add PVC support for gpgpu fill
URL   : https://patchwork.freedesktop.org/series/118520/
State : success

== Summary ==

CI Bug Log - changes from IGT_7310_full -> IGTPW_9065_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/index.html

Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts

New tests
---------

  New tests have been introduced between IGT_7310_full and IGTPW_9065_full:

### New IGT tests (2) ###

  * igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_9065_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][1] -> [FAIL][2] ([i915#2846])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-glk8/igt@gem_exec_fair@basic-deadline.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-glk8/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-glk:          [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-glk9/igt@gem_exec_fair@basic-pace@vcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-glk5/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [PASS][5] -> [FAIL][6] ([IGT#6] / [i915#2346])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
    - shard-glk:          [PASS][7] -> [FAIL][8] ([i915#79])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html

  * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2 (NEW):
    - {shard-rkl}:        NOTRUN -> [SKIP][9] ([i915#5176])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-rkl-4/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-vga-1:
    - shard-snb:          NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4579]) +9 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-snb6/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-vga-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-vga-1:
    - shard-snb:          NOTRUN -> [SKIP][11] ([fdo#109271]) +14 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-snb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-vga-1.html

  
#### Possible fixes ####

  * igt@gem_barrier_race@remote-request@rcs0:
    - {shard-tglu}:       [ABORT][12] ([i915#8211] / [i915#8234]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-tglu-10/igt@gem_barrier_race@remote-request@rcs0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-tglu-9/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - {shard-tglu}:       [FAIL][14] ([i915#6268]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-tglu-9/igt@gem_ctx_exec@basic-nohangcheck.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-tglu-4/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [FAIL][16] ([i915#2842]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none@bcs0:
    - {shard-rkl}:        [FAIL][18] ([i915#2842]) -> [PASS][19] +4 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-rkl-6/igt@gem_exec_fair@basic-none@bcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-rkl-2/igt@gem_exec_fair@basic-none@bcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-glk:          [FAIL][20] ([i915#2842]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - {shard-dg1}:        [FAIL][22] ([i915#3591]) -> [PASS][23] +1 similar issue
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - {shard-rkl}:        [SKIP][24] ([i915#1397]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-rkl-6/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_selftest@live@workarounds:
    - {shard-dg1}:        [ABORT][26] ([i915#4983]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-dg1-16/igt@i915_selftest@live@workarounds.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-dg1-16/igt@i915_selftest@live@workarounds.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - {shard-rkl}:        [FAIL][28] ([i915#3743]) -> [PASS][29] +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-rkl-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@perf_pmu@busy-double-start@vecs0:
    - {shard-dg1}:        [FAIL][30] ([i915#4349]) -> [PASS][31] +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-dg1-14/igt@perf_pmu@busy-double-start@vecs0.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-dg1-15/igt@perf_pmu@busy-double-start@vecs0.html

  
#### Warnings ####

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - shard-apl:          [SKIP][32] ([fdo#109271]) -> [SKIP][33] ([IGT#6] / [fdo#109271]) +2 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-apl1/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-apl3/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - shard-glk:          [SKIP][34] ([fdo#109271]) -> [SKIP][35] ([IGT#6] / [fdo#109271]) +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-glk8/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-glk2/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_content_protection@legacy@pipe-a-dp-1:
    - shard-apl:          [TIMEOUT][36] ([i915#7173]) -> [FAIL][37] ([fdo#110321] / [i915#7173])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7310/shard-apl1/igt@kms_content_protection@legacy@pipe-a-dp-1.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/shard-apl2/igt@kms_content_protection@legacy@pipe-a-dp-1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
  [i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
  [i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7310 -> IGTPW_9065

  CI-20190529: 20190529
  CI_DRM_13200: 0ae4ee2c735979030a0219218081eee661606921 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_9065: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/index.html
  IGT_7310: 2f9acfea5e3a93303f71cbda6e80ba64b8d75a4d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9065/index.html

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