* [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2
@ 2023-10-11 14:18 Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 01/20] drm-uapi/xe: Add documentation for query Francois Dugast
` (20 more replies)
0 siblings, 21 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
This is the second take of uAPI updates that would lead to
breakage in the compatibility, which it is not acceptable after
we are merged upstream. So, let's break it before it is too late,
and start upstreaming a good, reliable and clean uapi.
This series is not complete yet but it is sent for early review
as some patches are already a few weeks old.
It is intended to be applied after take 1 [1] which is not
merged yet, so it will break CI.
The matching kernel series is [2].
[1] https://patchwork.freedesktop.org/series/124710/
[2] https://patchwork.freedesktop.org/series/124977/
Francois Dugast (11):
drm-uapi/xe: Add documentation for query
drm-uapi/xe: Extend drm_xe_vm_bind_op
drm-uapi/xe: Add uAPI to query micro-controler firmware version
drm-uapi/xe: Document DRM_XE_DEVICE_QUERY_HWCONFIG
drm-uapi/xe: Extend uAPI to query HuC micro-controler firmware version
drm-uapi/xe: Remove useless query config num_params
drm-uapi/xe: Add missing DRM_ prefix in uAPI constants
drm-uapi/xe: Add _FLAG to uAPI constants usable for flags
drm-uapi/xe: Make constant comments visible in kernel doc
fixup! tests/intel/xe_query: Add a test for querying engine cycles
drm-uapi/xe: Remove unused inaccessible memory region
Rodrigo Vivi (9):
drm-uapi/xe: Remove GT_TYPE_REMOTE.
drm-uapi/xe: Kill VM_MADVISE IOCTL and the atomic tests
drm/xe_query: Remove backward compatibility of vram_visible_size.
xe_ioctl: Converge bo_create to the most used version
xe_ioctl: Rename *xe_bo_create_flags to simply xe_bo_create
xe_query: Add missing include.
xe_query: Kill visible_vram_if_possible
drm-uapi/xe: Separate bo_create placement from flags
drm-uapi/xe: Align with GuC version type update
include/drm-uapi/xe_drm.h | 478 ++++++++++++++++-------------
lib/igt_draw.c | 7 +-
lib/igt_fb.c | 9 +-
lib/intel_batchbuffer.c | 28 +-
lib/intel_blt.c | 2 +-
lib/intel_bufops.c | 2 +-
lib/intel_compute.c | 6 +-
lib/intel_ctx.c | 4 +-
lib/xe/xe_ioctl.c | 86 +++---
lib/xe/xe_ioctl.h | 10 +-
lib/xe/xe_query.c | 83 +----
lib/xe/xe_query.h | 8 +-
lib/xe/xe_spin.c | 13 +-
lib/xe/xe_util.c | 14 +-
lib/xe/xe_util.h | 4 +-
tests/intel/api_intel_allocator.c | 4 +-
tests/intel/kms_big_fb.c | 22 +-
tests/intel/xe_ccs.c | 20 +-
tests/intel/xe_create.c | 10 +-
tests/intel/xe_debugfs.c | 14 +-
tests/intel/xe_dma_buf_sync.c | 9 +-
tests/intel/xe_drm_fdinfo.c | 24 +-
tests/intel/xe_evict.c | 70 +++--
tests/intel/xe_exec_balancer.c | 43 +--
tests/intel/xe_exec_basic.c | 30 +-
tests/intel/xe_exec_compute_mode.c | 11 +-
tests/intel/xe_exec_fault_mode.c | 198 ++----------
tests/intel/xe_exec_reset.c | 83 ++---
tests/intel/xe_exec_store.c | 26 +-
tests/intel/xe_exec_threads.c | 63 ++--
tests/intel/xe_exercise_blt.c | 10 +-
tests/intel/xe_guc_pc.c | 17 +-
tests/intel/xe_huc_copy.c | 4 +-
tests/intel/xe_intel_bb.c | 4 +-
tests/intel/xe_mmap.c | 49 +--
tests/intel/xe_noexec_ping_pong.c | 6 +-
tests/intel/xe_pm.c | 27 +-
tests/intel/xe_pm_residency.c | 7 +-
tests/intel/xe_prime_self_import.c | 37 ++-
tests/intel/xe_query.c | 52 ++--
tests/intel/xe_spin_batch.c | 4 +-
tests/intel/xe_vm.c | 171 ++++++-----
tests/intel/xe_waitfence.c | 20 +-
tests/kms_addfb_basic.c | 2 +-
tests/kms_getfb.c | 2 +-
45 files changed, 826 insertions(+), 967 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 01/20] drm-uapi/xe: Add documentation for query
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 02/20] drm-uapi/xe: Extend drm_xe_vm_bind_op Francois Dugast
` (19 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
Align with commit ("Add documentation for query")
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
include/drm-uapi/xe_drm.h | 41 ++++++++++++++++++++++++++++++++++++---
1 file changed, 38 insertions(+), 3 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 6ff1106e4..ddc227f5a 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -321,14 +321,43 @@ struct drm_xe_query_config {
/** @pad: MBZ */
__u32 pad;
+ /*
+ * Device ID (lower 16 bits) and the device revision (next
+ * 8 bits)
+ */
#define XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
+ /*
+ * Flags describing the device configuration, see list below
+ */
#define XE_QUERY_CONFIG_FLAGS 1
+ /*
+ * Flag is set if the device has usable VRAM
+ */
#define XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0)
+ /*
+ * Minimal memory alignment required by this device,
+ * typically SZ_4K or SZ_64K
+ */
#define XE_QUERY_CONFIG_MIN_ALIGNMENT 2
+ /*
+ * Maximum bits of a virtual address
+ */
#define XE_QUERY_CONFIG_VA_BITS 3
+ /*
+ * Total number of GTs for the entire device
+ */
#define XE_QUERY_CONFIG_GT_COUNT 4
+ /*
+ * Total number of accessible memory regions
+ */
#define XE_QUERY_CONFIG_MEM_REGION_COUNT 5
+ /*
+ * Value of the highest available exec queue priority
+ */
#define XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 6
+ /*
+ * Number of elements in the info array
+ */
#define XE_QUERY_CONFIG_NUM_PARAM (XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY + 1)
/** @info: array of elements containing the config info */
__u64 info[];
@@ -440,9 +469,15 @@ struct drm_xe_query_topology_mask {
/**
* struct drm_xe_device_query - main structure to query device information
*
- * If size is set to 0, the driver fills it with the required size for the
- * requested type of data to query. If size is equal to the required size,
- * the queried information is copied into data.
+ * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_*
+ * and sets the value in the query member. This determines the type of
+ * the structure provided by the driver in data, among struct drm_xe_query_*.
+ *
+ * If size is set to 0, the driver fills it with the required size for
+ * the requested type of data to query. If size is equal to the required
+ * size, the queried information is copied into data. If size is set to
+ * a value different from 0 and different from the required size, the
+ * IOCTL call returns -EINVAL.
*
* For example the following code snippet allows retrieving and printing
* information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 02/20] drm-uapi/xe: Extend drm_xe_vm_bind_op
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 01/20] drm-uapi/xe: Add documentation for query Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 03/20] drm-uapi/xe: Add uAPI to query micro-controler firmware version Francois Dugast
` (18 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
Align with commit ("Extend drm_xe_vm_bind_op")
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
include/drm-uapi/xe_drm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index ddc227f5a..3d123fc95 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -656,6 +656,9 @@ struct drm_xe_vm_destroy {
};
struct drm_xe_vm_bind_op {
+ /** @extensions: Pointer to the first extension struct, if any */
+ __u64 extensions;
+
/**
* @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 03/20] drm-uapi/xe: Add uAPI to query micro-controler firmware version
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 01/20] drm-uapi/xe: Add documentation for query Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 02/20] drm-uapi/xe: Extend drm_xe_vm_bind_op Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 04/20] drm-uapi/xe: Document DRM_XE_DEVICE_QUERY_HWCONFIG Francois Dugast
` (17 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
Align with commit ("Add uAPI to query micro-controler firmware version ")
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
include/drm-uapi/xe_drm.h | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 3d123fc95..8f8fd5ecc 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -466,6 +466,36 @@ struct drm_xe_query_topology_mask {
__u8 mask[];
};
+/**
+ * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version
+ *
+ * Given a uc_type this will return the major, minor, patch and branch version
+ * of the micro-controller firmware.
+ */
+struct drm_xe_query_uc_fw_version {
+ /** @uc: The micro-controller type to query firmware version */
+#define XE_QUERY_UC_TYPE_GUC 0
+ __u16 uc_type;
+
+ /** @pad: MBZ */
+ __u16 pad;
+
+ /* @major_ver: major uc fw version */
+ __u32 major_ver;
+ /* @minor_ver: minor uc fw version */
+ __u32 minor_ver;
+ /* @patch_ver: patch uc fw version */
+ __u32 patch_ver;
+ /* @branch_ver: branch uc fw version */
+ __u32 branch_ver;
+
+ /** @pad2: MBZ */
+ __u32 pad2;
+
+ /** @reserved: Reserved */
+ __u64 reserved;
+};
+
/**
* struct drm_xe_device_query - main structure to query device information
*
@@ -518,6 +548,7 @@ struct drm_xe_device_query {
#define DRM_XE_DEVICE_QUERY_HWCONFIG 4
#define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
#define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6
+#define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7
/** @query: The type of data to query */
__u32 query;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 04/20] drm-uapi/xe: Document DRM_XE_DEVICE_QUERY_HWCONFIG
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (2 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 03/20] drm-uapi/xe: Add uAPI to query micro-controler firmware version Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 05/20] drm-uapi/xe: Extend uAPI to query HuC micro-controler firmware version Francois Dugast
` (16 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
Align with commit ("Document DRM_XE_DEVICE_QUERY_HWCONFIG")
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
include/drm-uapi/xe_drm.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 8f8fd5ecc..6cf2375eb 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -545,6 +545,11 @@ struct drm_xe_device_query {
#define DRM_XE_DEVICE_QUERY_MEM_USAGE 1
#define DRM_XE_DEVICE_QUERY_CONFIG 2
#define DRM_XE_DEVICE_QUERY_GT_LIST 3
+ /*
+ * Query type to retrieve the hardware configuration of the device
+ * such as information on slices, memory, caches, and so on. It is
+ * provided as a table of attributes (key / value).
+ */
#define DRM_XE_DEVICE_QUERY_HWCONFIG 4
#define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
#define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 05/20] drm-uapi/xe: Extend uAPI to query HuC micro-controler firmware version
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (3 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 04/20] drm-uapi/xe: Document DRM_XE_DEVICE_QUERY_HWCONFIG Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 06/20] drm-uapi/xe: Remove useless query config num_params Francois Dugast
` (15 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
Align with commit ("Extend uAPI to query HuC micro-controler firmware
version")
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
include/drm-uapi/xe_drm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 6cf2375eb..3eef48f10 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -475,6 +475,7 @@ struct drm_xe_query_topology_mask {
struct drm_xe_query_uc_fw_version {
/** @uc: The micro-controller type to query firmware version */
#define XE_QUERY_UC_TYPE_GUC 0
+#define XE_QUERY_UC_TYPE_HUC 1
__u16 uc_type;
/** @pad: MBZ */
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 06/20] drm-uapi/xe: Remove useless query config num_params
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (4 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 05/20] drm-uapi/xe: Extend uAPI to query HuC micro-controler firmware version Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 07/20] drm-uapi/xe: Add missing DRM_ prefix in uAPI constants Francois Dugast
` (14 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
Align with commit ("Remove useless query config num_params")
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
include/drm-uapi/xe_drm.h | 7 -------
lib/xe/xe_query.c | 2 --
tests/intel/xe_query.c | 2 --
3 files changed, 11 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 3eef48f10..7a1b75a60 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -315,9 +315,6 @@ struct drm_xe_query_mem_usage {
* struct drm_xe_query_config in .data.
*/
struct drm_xe_query_config {
- /** @num_params: number of parameters returned in info */
- __u32 num_params;
-
/** @pad: MBZ */
__u32 pad;
@@ -355,10 +352,6 @@ struct drm_xe_query_config {
* Value of the highest available exec queue priority
*/
#define XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 6
- /*
- * Number of elements in the info array
- */
-#define XE_QUERY_CONFIG_NUM_PARAM (XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY + 1)
/** @info: array of elements containing the config info */
__u64 info[];
};
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 986a3a0c1..cd0e29dcc 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -34,8 +34,6 @@ static struct drm_xe_query_config *xe_query_config_new(int fd)
query.data = to_user_pointer(config);
igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query), 0);
- igt_assert(config->num_params > 0);
-
return config;
}
diff --git a/tests/intel/xe_query.c b/tests/intel/xe_query.c
index 2cff75414..dc19a9d32 100644
--- a/tests/intel/xe_query.c
+++ b/tests/intel/xe_query.c
@@ -359,8 +359,6 @@ test_query_config(int fd)
query.data = to_user_pointer(config);
igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query), 0);
- igt_assert(config->num_params > 0);
-
igt_info("XE_QUERY_CONFIG_REV_AND_DEVICE_ID\t%#llx\n",
config->info[XE_QUERY_CONFIG_REV_AND_DEVICE_ID]);
igt_info(" REV_ID\t\t\t\t%#llx\n",
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 07/20] drm-uapi/xe: Add missing DRM_ prefix in uAPI constants
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (5 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 06/20] drm-uapi/xe: Remove useless query config num_params Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 08/20] drm-uapi/xe: Add _FLAG to uAPI constants usable for flags Francois Dugast
` (13 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
Align with commit ("Add missing DRM_ prefix in uAPI constants")
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
include/drm-uapi/xe_drm.h | 140 +++++++++++++++----------------
lib/intel_batchbuffer.c | 8 +-
lib/xe/xe_ioctl.c | 22 ++---
lib/xe/xe_query.c | 14 ++--
lib/xe/xe_query.h | 4 +-
lib/xe/xe_util.c | 10 +--
lib/xe/xe_util.h | 4 +-
tests/intel/xe_ccs.c | 4 +-
tests/intel/xe_debugfs.c | 14 ++--
tests/intel/xe_exec_basic.c | 8 +-
tests/intel/xe_exec_fault_mode.c | 4 +-
tests/intel/xe_exec_reset.c | 20 ++---
tests/intel/xe_exec_threads.c | 4 +-
tests/intel/xe_exercise_blt.c | 4 +-
tests/intel/xe_pm.c | 2 +-
tests/intel/xe_query.c | 48 +++++------
tests/intel/xe_vm.c | 10 +--
17 files changed, 160 insertions(+), 160 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 7a1b75a60..05e644fb3 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -19,12 +19,12 @@ extern "C" {
/**
* DOC: uevent generated by xe on it's pci node.
*
- * XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt
+ * DRM_XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt
* fails. The value supplied with the event is always "NEEDS_RESET".
* Additional information supplied is tile id and gt id of the gt unit for
* which reset has failed.
*/
-#define XE_RESET_FAILED_UEVENT "DEVICE_STATUS"
+#define DRM_XE_RESET_FAILED_UEVENT "DEVICE_STATUS"
/**
* struct xe_user_extension - Base class for defining a chain of extensions
@@ -103,8 +103,8 @@ struct xe_user_extension {
#define DRM_XE_VM_CREATE 0x03
#define DRM_XE_VM_DESTROY 0x04
#define DRM_XE_VM_BIND 0x05
-#define DRM_XE_EXEC_QUEUE_CREATE 0x06
-#define DRM_XE_EXEC_QUEUE_DESTROY 0x07
+#define DRM_XE_EXEC_QUEUE_CREATE 0x06
+#define DRM_XE_EXEC_QUEUE_DESTROY 0x07
#define DRM_XE_EXEC 0x08
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x09
#define DRM_XE_WAIT_USER_FENCE 0x0a
@@ -150,14 +150,14 @@ struct drm_xe_engine_class_instance {
* enum drm_xe_memory_class - Supported memory classes.
*/
enum drm_xe_memory_class {
- /** @XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */
- XE_MEM_REGION_CLASS_SYSMEM = 0,
+ /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */
+ DRM_XE_MEM_REGION_CLASS_SYSMEM = 0,
/**
- * @XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this
+ * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this
* represents the memory that is local to the device, which we
* call VRAM. Not valid on integrated platforms.
*/
- XE_MEM_REGION_CLASS_VRAM
+ DRM_XE_MEM_REGION_CLASS_VRAM
};
/**
@@ -217,7 +217,7 @@ struct drm_xe_query_mem_region {
* always equal the @total_size, since all of it will be CPU
* accessible.
*
- * Note this is only tracked for XE_MEM_REGION_CLASS_VRAM
+ * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM
* regions (for other types the value here will always equal
* zero).
*/
@@ -229,7 +229,7 @@ struct drm_xe_query_mem_region {
* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
* accounting. Without this the value here will always equal
* zero. Note this is only currently tracked for
- * XE_MEM_REGION_CLASS_VRAM regions (for other types the value
+ * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value
* here will always be zero).
*/
__u64 cpu_visible_used;
@@ -322,36 +322,36 @@ struct drm_xe_query_config {
* Device ID (lower 16 bits) and the device revision (next
* 8 bits)
*/
-#define XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
+#define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
/*
* Flags describing the device configuration, see list below
*/
-#define XE_QUERY_CONFIG_FLAGS 1
+#define DRM_XE_QUERY_CONFIG_FLAGS 1
/*
* Flag is set if the device has usable VRAM
*/
- #define XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0)
+ #define DRM_XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0)
/*
* Minimal memory alignment required by this device,
* typically SZ_4K or SZ_64K
*/
-#define XE_QUERY_CONFIG_MIN_ALIGNMENT 2
+#define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
/*
* Maximum bits of a virtual address
*/
-#define XE_QUERY_CONFIG_VA_BITS 3
+#define DRM_XE_QUERY_CONFIG_VA_BITS 3
/*
* Total number of GTs for the entire device
*/
-#define XE_QUERY_CONFIG_GT_COUNT 4
+#define DRM_XE_QUERY_CONFIG_GT_COUNT 4
/*
* Total number of accessible memory regions
*/
-#define XE_QUERY_CONFIG_MEM_REGION_COUNT 5
+#define DRM_XE_QUERY_CONFIG_MEM_REGION_COUNT 5
/*
* Value of the highest available exec queue priority
*/
-#define XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 6
+#define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 6
/** @info: array of elements containing the config info */
__u64 info[];
};
@@ -365,9 +365,9 @@ struct drm_xe_query_config {
* implementing graphics and/or media operations.
*/
struct drm_xe_query_gt {
-#define XE_QUERY_GT_TYPE_MAIN 0
-#define XE_QUERY_GT_TYPE_REMOTE 1
-#define XE_QUERY_GT_TYPE_MEDIA 2
+#define DRM_XE_QUERY_GT_TYPE_MAIN 0
+#define DRM_XE_QUERY_GT_TYPE_REMOTE 1
+#define DRM_XE_QUERY_GT_TYPE_MEDIA 2
/** @type: GT type: Main, Remote, or Media */
__u16 type;
/** @gt_id: Unique ID of this GT within the PCI Device */
@@ -432,7 +432,7 @@ struct drm_xe_query_topology_mask {
* DSS_GEOMETRY ff ff ff ff 00 00 00 00
* means 32 DSS are available for geometry.
*/
-#define XE_TOPO_DSS_GEOMETRY (1 << 0)
+#define DRM_XE_TOPO_DSS_GEOMETRY (1 << 0)
/*
* To query the mask of Dual Sub Slices (DSS) available for compute
* operations. For example a query response containing the following
@@ -440,7 +440,7 @@ struct drm_xe_query_topology_mask {
* DSS_COMPUTE ff ff ff ff 00 00 00 00
* means 32 DSS are available for compute.
*/
-#define XE_TOPO_DSS_COMPUTE (1 << 1)
+#define DRM_XE_TOPO_DSS_COMPUTE (1 << 1)
/*
* To query the mask of Execution Units (EU) available per Dual Sub
* Slices (DSS). For example a query response containing the following
@@ -448,7 +448,7 @@ struct drm_xe_query_topology_mask {
* EU_PER_DSS ff ff 00 00 00 00 00 00
* means each DSS has 16 EU.
*/
-#define XE_TOPO_EU_PER_DSS (1 << 2)
+#define DRM_XE_TOPO_EU_PER_DSS (1 << 2)
/** @type: type of mask */
__u16 type;
@@ -467,8 +467,8 @@ struct drm_xe_query_topology_mask {
*/
struct drm_xe_query_uc_fw_version {
/** @uc: The micro-controller type to query firmware version */
-#define XE_QUERY_UC_TYPE_GUC 0
-#define XE_QUERY_UC_TYPE_HUC 1
+#define DRM_XE_QUERY_UC_TYPE_GUC 0
+#define DRM_XE_QUERY_UC_TYPE_HUC 1
__u16 uc_type;
/** @pad: MBZ */
@@ -572,8 +572,8 @@ struct drm_xe_gem_create {
*/
__u64 size;
-#define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
-#define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
+#define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
+#define DRM_XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
/*
* When using VRAM as a possible placement, ensure that the corresponding VRAM
* allocation will always use the CPU accessible part of VRAM. This is important
@@ -589,7 +589,7 @@ struct drm_xe_gem_create {
* display surfaces, therefore the kernel requires setting this flag for such
* objects, otherwise an error is thrown on small-bar systems.
*/
-#define XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26)
+#define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26)
/**
* @flags: Flags, currently a mask of memory instances of where BO can
* be placed
@@ -656,14 +656,14 @@ struct drm_xe_ext_set_property {
};
struct drm_xe_vm_create {
-#define XE_VM_EXTENSION_SET_PROPERTY 0
+#define DRM_XE_VM_EXTENSION_SET_PROPERTY 0
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
-#define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0)
-#define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1)
-#define DRM_XE_VM_CREATE_ASYNC_DEFAULT (0x1 << 2)
-#define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3)
+#define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0)
+#define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1)
+#define DRM_XE_VM_CREATE_ASYNC_DEFAULT (0x1 << 2)
+#define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3)
/** @flags: Flags */
__u32 flags;
@@ -722,29 +722,29 @@ struct drm_xe_vm_bind_op {
*/
__u64 tile_mask;
-#define XE_VM_BIND_OP_MAP 0x0
-#define XE_VM_BIND_OP_UNMAP 0x1
-#define XE_VM_BIND_OP_MAP_USERPTR 0x2
-#define XE_VM_BIND_OP_UNMAP_ALL 0x3
-#define XE_VM_BIND_OP_PREFETCH 0x4
+#define DRM_XE_VM_BIND_OP_MAP 0x0
+#define DRM_XE_VM_BIND_OP_UNMAP 0x1
+#define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2
+#define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3
+#define DRM_XE_VM_BIND_OP_PREFETCH 0x4
/** @op: Bind operation to perform */
__u32 op;
-#define XE_VM_BIND_FLAG_READONLY (0x1 << 0)
-#define XE_VM_BIND_FLAG_ASYNC (0x1 << 1)
+#define DRM_XE_VM_BIND_FLAG_READONLY (0x1 << 0)
+#define DRM_XE_VM_BIND_FLAG_ASYNC (0x1 << 1)
/*
* Valid on a faulting VM only, do the MAP operation immediately rather
* than deferring the MAP to the page fault handler.
*/
-#define XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 2)
+#define DRM_XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 2)
/*
* When the NULL flag is set, the page tables are setup with a special
* bit which indicates writes are dropped and all reads return zero. In
- * the future, the NULL flags will only be valid for XE_VM_BIND_OP_MAP
+ * the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP
* operations, the BO handle MBZ, and the BO offset MBZ. This flag is
* intended to implement VK sparse bindings.
*/
-#define XE_VM_BIND_FLAG_NULL (0x1 << 3)
+#define DRM_XE_VM_BIND_FLAG_NULL (0x1 << 3)
/** @flags: Bind flags */
__u32 flags;
@@ -811,14 +811,14 @@ struct drm_xe_exec_queue_set_property {
/** @exec_queue_id: Exec queue ID */
__u32 exec_queue_id;
-#define XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0
-#define XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1
-#define XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2
-#define XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 3
-#define XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 4
-#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 5
-#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 6
-#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 7
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 3
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 4
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 5
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 6
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 7
/** @property: property to set */
__u32 property;
@@ -830,7 +830,7 @@ struct drm_xe_exec_queue_set_property {
};
struct drm_xe_exec_queue_create {
-#define XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0
+#define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
@@ -869,7 +869,7 @@ struct drm_xe_exec_queue_get_property {
/** @exec_queue_id: Exec queue ID */
__u32 exec_queue_id;
-#define XE_EXEC_QUEUE_GET_PROPERTY_BAN 0
+#define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0
/** @property: property to get */
__u32 property;
@@ -1058,8 +1058,8 @@ struct drm_xe_vm_madvise {
* For DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS usage, see enum
* drm_xe_memory_class.
*/
-#define DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS 0
-#define DRM_XE_VM_MADVISE_PREFERRED_GT 1
+#define DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS 0
+#define DRM_XE_VM_MADVISE_PREFERRED_GT 1
/*
* In this case lower 32 bits are mem class, upper 32 are GT.
* Combination provides a single IOCTL plus migrate VMA to preferred
@@ -1070,25 +1070,25 @@ struct drm_xe_vm_madvise {
* The CPU will do atomic memory operations to this VMA. Must be set on
* some devices for atomics to behave correctly.
*/
-#define DRM_XE_VM_MADVISE_CPU_ATOMIC 3
+#define DRM_XE_VM_MADVISE_CPU_ATOMIC 3
/*
* The device will do atomic memory operations to this VMA. Must be set
* on some devices for atomics to behave correctly.
*/
-#define DRM_XE_VM_MADVISE_DEVICE_ATOMIC 4
+#define DRM_XE_VM_MADVISE_DEVICE_ATOMIC 4
/*
* Priority WRT to eviction (moving from preferred memory location due
* to memory pressure). The lower the priority, the more likely to be
* evicted.
*/
-#define DRM_XE_VM_MADVISE_PRIORITY 5
-#define DRM_XE_VMA_PRIORITY_LOW 0
+#define DRM_XE_VM_MADVISE_PRIORITY 5
+#define DRM_XE_VMA_PRIORITY_LOW 0
/* Default */
-#define DRM_XE_VMA_PRIORITY_NORMAL 1
+#define DRM_XE_VMA_PRIORITY_NORMAL 1
/* Must be user with elevated privileges */
-#define DRM_XE_VMA_PRIORITY_HIGH 2
+#define DRM_XE_VMA_PRIORITY_HIGH 2
/* Pin the VMA in memory, must be user with elevated privileges */
-#define DRM_XE_VM_MADVISE_PIN 6
+#define DRM_XE_VM_MADVISE_PIN 6
/** @property: property to set */
__u32 property;
@@ -1109,7 +1109,7 @@ struct drm_xe_vm_madvise {
* in 'struct perf_event_attr' as part of perf_event_open syscall to read a
* particular event.
*
- * For example to open the XE_PMU_INTERRUPTS(0):
+ * For example to open the DRM_XE_PMU_INTERRUPTS(0):
*
* .. code-block:: C
*
@@ -1123,7 +1123,7 @@ struct drm_xe_vm_madvise {
* attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED;
* attr.use_clockid = 1;
* attr.clockid = CLOCK_MONOTONIC;
- * attr.config = XE_PMU_INTERRUPTS(0);
+ * attr.config = DRM_XE_PMU_INTERRUPTS(0);
*
* fd = syscall(__NR_perf_event_open, &attr, -1, cpu, -1, 0);
*/
@@ -1136,11 +1136,11 @@ struct drm_xe_vm_madvise {
#define ___XE_PMU_OTHER(gt, x) \
(((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
-#define XE_PMU_INTERRUPTS(gt) ___XE_PMU_OTHER(gt, 0)
-#define XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1)
-#define XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2)
-#define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
-#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 4)
+#define DRM_XE_PMU_INTERRUPTS(gt) ___XE_PMU_OTHER(gt, 0)
+#define DRM_XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1)
+#define DRM_XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2)
+#define DRM_XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
+#define DRM_XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 4)
#if defined(__cplusplus)
}
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index df82ef5f5..bea03ff39 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1286,7 +1286,7 @@ static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(struct intel_bb *ibb,
{
struct drm_i915_gem_exec_object2 **objects = ibb->objects;
struct drm_xe_vm_bind_op *bind_ops, *ops;
- bool set_obj = (op & 0xffff) == XE_VM_BIND_OP_MAP;
+ bool set_obj = (op & 0xffff) == DRM_XE_VM_BIND_OP_MAP;
bind_ops = calloc(ibb->num_objects, sizeof(*bind_ops));
igt_assert(bind_ops);
@@ -1325,8 +1325,8 @@ static void __unbind_xe_objects(struct intel_bb *ibb)
if (ibb->num_objects > 1) {
struct drm_xe_vm_bind_op *bind_ops;
- uint32_t op = XE_VM_BIND_OP_UNMAP;
- uint32_t flags = XE_VM_BIND_FLAG_ASYNC;
+ uint32_t op = DRM_XE_VM_BIND_OP_UNMAP;
+ uint32_t flags = DRM_XE_VM_BIND_FLAG_ASYNC;
bind_ops = xe_alloc_bind_ops(ibb, op, flags, 0);
xe_vm_bind_array(ibb->fd, ibb->vm_id, 0, bind_ops,
@@ -2357,7 +2357,7 @@ __xe_bb_exec(struct intel_bb *ibb, uint64_t flags, bool sync)
syncs[0].handle = syncobj_create(ibb->fd, 0);
if (ibb->num_objects > 1) {
- bind_ops = xe_alloc_bind_ops(ibb, XE_VM_BIND_OP_MAP, XE_VM_BIND_FLAG_ASYNC, 0);
+ bind_ops = xe_alloc_bind_ops(ibb, DRM_XE_VM_BIND_OP_MAP, DRM_XE_VM_BIND_FLAG_ASYNC, 0);
xe_vm_bind_array(ibb->fd, ibb->vm_id, 0, bind_ops,
ibb->num_objects, syncs, 1);
free(bind_ops);
diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 895e3bd4e..21a85225f 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -67,7 +67,7 @@ void xe_vm_unbind_all_async(int fd, uint32_t vm, uint32_t exec_queue,
uint32_t num_syncs)
{
__xe_vm_bind_assert(fd, vm, exec_queue, bo, 0, 0, 0,
- XE_VM_BIND_OP_UNMAP_ALL, XE_VM_BIND_FLAG_ASYNC,
+ DRM_XE_VM_BIND_OP_UNMAP_ALL, DRM_XE_VM_BIND_FLAG_ASYNC,
sync, num_syncs, 0, 0);
}
@@ -130,7 +130,7 @@ void xe_vm_bind(int fd, uint32_t vm, uint32_t bo, uint64_t offset,
struct drm_xe_sync *sync, uint32_t num_syncs)
{
__xe_vm_bind_assert(fd, vm, 0, bo, offset, addr, size,
- XE_VM_BIND_OP_MAP, 0, sync, num_syncs, 0, 0);
+ DRM_XE_VM_BIND_OP_MAP, 0, sync, num_syncs, 0, 0);
}
void xe_vm_unbind(int fd, uint32_t vm, uint64_t offset,
@@ -138,7 +138,7 @@ void xe_vm_unbind(int fd, uint32_t vm, uint64_t offset,
struct drm_xe_sync *sync, uint32_t num_syncs)
{
__xe_vm_bind_assert(fd, vm, 0, 0, offset, addr, size,
- XE_VM_BIND_OP_UNMAP, 0, sync, num_syncs, 0, 0);
+ DRM_XE_VM_BIND_OP_UNMAP, 0, sync, num_syncs, 0, 0);
}
void xe_vm_prefetch_async(int fd, uint32_t vm, uint32_t exec_queue, uint64_t offset,
@@ -147,7 +147,7 @@ void xe_vm_prefetch_async(int fd, uint32_t vm, uint32_t exec_queue, uint64_t off
uint32_t region)
{
__xe_vm_bind_assert(fd, vm, exec_queue, 0, offset, addr, size,
- XE_VM_BIND_OP_PREFETCH, XE_VM_BIND_FLAG_ASYNC,
+ DRM_XE_VM_BIND_OP_PREFETCH, DRM_XE_VM_BIND_FLAG_ASYNC,
sync, num_syncs, region, 0);
}
@@ -156,7 +156,7 @@ void xe_vm_bind_async(int fd, uint32_t vm, uint32_t exec_queue, uint32_t bo,
struct drm_xe_sync *sync, uint32_t num_syncs)
{
__xe_vm_bind_assert(fd, vm, exec_queue, bo, offset, addr, size,
- XE_VM_BIND_OP_MAP, XE_VM_BIND_FLAG_ASYNC, sync,
+ DRM_XE_VM_BIND_OP_MAP, DRM_XE_VM_BIND_FLAG_ASYNC, sync,
num_syncs, 0, 0);
}
@@ -166,7 +166,7 @@ void xe_vm_bind_async_flags(int fd, uint32_t vm, uint32_t exec_queue, uint32_t b
uint32_t flags)
{
__xe_vm_bind_assert(fd, vm, exec_queue, bo, offset, addr, size,
- XE_VM_BIND_OP_MAP, XE_VM_BIND_FLAG_ASYNC | flags,
+ DRM_XE_VM_BIND_OP_MAP, DRM_XE_VM_BIND_FLAG_ASYNC | flags,
sync, num_syncs, 0, 0);
}
@@ -175,7 +175,7 @@ void xe_vm_bind_userptr_async(int fd, uint32_t vm, uint32_t exec_queue,
struct drm_xe_sync *sync, uint32_t num_syncs)
{
__xe_vm_bind_assert(fd, vm, exec_queue, 0, userptr, addr, size,
- XE_VM_BIND_OP_MAP_USERPTR, XE_VM_BIND_FLAG_ASYNC,
+ DRM_XE_VM_BIND_OP_MAP_USERPTR, DRM_XE_VM_BIND_FLAG_ASYNC,
sync, num_syncs, 0, 0);
}
@@ -185,7 +185,7 @@ void xe_vm_bind_userptr_async_flags(int fd, uint32_t vm, uint32_t exec_queue,
uint32_t num_syncs, uint32_t flags)
{
__xe_vm_bind_assert(fd, vm, exec_queue, 0, userptr, addr, size,
- XE_VM_BIND_OP_MAP_USERPTR, XE_VM_BIND_FLAG_ASYNC |
+ DRM_XE_VM_BIND_OP_MAP_USERPTR, DRM_XE_VM_BIND_FLAG_ASYNC |
flags, sync, num_syncs, 0, 0);
}
@@ -194,7 +194,7 @@ void xe_vm_unbind_async(int fd, uint32_t vm, uint32_t exec_queue,
struct drm_xe_sync *sync, uint32_t num_syncs)
{
__xe_vm_bind_assert(fd, vm, exec_queue, 0, offset, addr, size,
- XE_VM_BIND_OP_UNMAP, XE_VM_BIND_FLAG_ASYNC, sync,
+ DRM_XE_VM_BIND_OP_UNMAP, DRM_XE_VM_BIND_FLAG_ASYNC, sync,
num_syncs, 0, 0);
}
@@ -208,13 +208,13 @@ static void __xe_vm_bind_sync(int fd, uint32_t vm, uint32_t bo, uint64_t offset,
void xe_vm_bind_sync(int fd, uint32_t vm, uint32_t bo, uint64_t offset,
uint64_t addr, uint64_t size)
{
- __xe_vm_bind_sync(fd, vm, bo, offset, addr, size, XE_VM_BIND_OP_MAP);
+ __xe_vm_bind_sync(fd, vm, bo, offset, addr, size, DRM_XE_VM_BIND_OP_MAP);
}
void xe_vm_unbind_sync(int fd, uint32_t vm, uint64_t offset,
uint64_t addr, uint64_t size)
{
- __xe_vm_bind_sync(fd, vm, 0, offset, addr, size, XE_VM_BIND_OP_UNMAP);
+ __xe_vm_bind_sync(fd, vm, 0, offset, addr, size, DRM_XE_VM_BIND_OP_UNMAP);
}
void xe_vm_destroy(int fd, uint32_t vm)
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index cd0e29dcc..bb54f0fd6 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -247,9 +247,9 @@ struct xe_device *xe_device_get(int fd)
xe_dev->fd = fd;
xe_dev->config = xe_query_config_new(fd);
- xe_dev->number_gt = xe_dev->config->info[XE_QUERY_CONFIG_GT_COUNT];
- xe_dev->va_bits = xe_dev->config->info[XE_QUERY_CONFIG_VA_BITS];
- xe_dev->dev_id = xe_dev->config->info[XE_QUERY_CONFIG_REV_AND_DEVICE_ID] & 0xffff;
+ xe_dev->number_gt = xe_dev->config->info[DRM_XE_QUERY_CONFIG_GT_COUNT];
+ xe_dev->va_bits = xe_dev->config->info[DRM_XE_QUERY_CONFIG_VA_BITS];
+ xe_dev->dev_id = xe_dev->config->info[DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID] & 0xffff;
xe_dev->gt_list = xe_query_gt_list_new(fd);
xe_dev->memory_regions = __memory_regions(xe_dev->gt_list);
xe_dev->hw_engines = xe_query_engines_new(fd, &xe_dev->number_hw_engines);
@@ -413,7 +413,7 @@ static uint64_t __xe_visible_vram_size(int fd, int gt)
* @gt: gt id
*
* Returns vram memory bitmask for xe device @fd and @gt id, with
- * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU access is
+ * DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU access is
* possible.
*/
uint64_t visible_vram_memory(int fd, int gt)
@@ -423,7 +423,7 @@ uint64_t visible_vram_memory(int fd, int gt)
* has landed.
*/
if (__xe_visible_vram_size(fd, gt))
- return vram_memory(fd, gt) | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
+ return vram_memory(fd, gt) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
else
return vram_memory(fd, gt); /* older kernel */
}
@@ -448,7 +448,7 @@ uint64_t vram_if_possible(int fd, int gt)
*
* Returns vram memory bitmask for xe device @fd and @gt id or system memory if
* there's no vram memory available for @gt. Also attaches the
- * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
+ * DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
* when using vram.
*/
uint64_t visible_vram_if_possible(int fd, int gt)
@@ -462,7 +462,7 @@ uint64_t visible_vram_if_possible(int fd, int gt)
* has landed.
*/
if (__xe_visible_vram_size(fd, gt))
- return vram ? vram | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
+ return vram ? vram | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
else
return vram ? vram : system_memory; /* older kernel */
}
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index da7deaf4c..8557bb4c5 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -76,8 +76,8 @@ struct xe_device {
for (uint64_t __i = 0; __i < igt_fls(__memreg); __i++) \
for_if(__r = (__memreg & (1ull << __i)))
-#define XE_IS_CLASS_SYSMEM(__region) ((__region)->mem_class == XE_MEM_REGION_CLASS_SYSMEM)
-#define XE_IS_CLASS_VRAM(__region) ((__region)->mem_class == XE_MEM_REGION_CLASS_VRAM)
+#define XE_IS_CLASS_SYSMEM(__region) ((__region)->mem_class == DRM_XE_MEM_REGION_CLASS_SYSMEM)
+#define XE_IS_CLASS_VRAM(__region) ((__region)->mem_class == DRM_XE_MEM_REGION_CLASS_VRAM)
unsigned int xe_number_gt(int fd);
uint64_t all_memory_regions(int fd);
diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
index 5fa4d4610..780125f92 100644
--- a/lib/xe/xe_util.c
+++ b/lib/xe/xe_util.c
@@ -134,12 +134,12 @@ static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(struct igt_list_head *obj_lis
ops = &bind_ops[i];
if (obj->bind_op == XE_OBJECT_BIND) {
- op = XE_VM_BIND_OP_MAP;
- flags = XE_VM_BIND_FLAG_ASYNC;
+ op = DRM_XE_VM_BIND_OP_MAP;
+ flags = DRM_XE_VM_BIND_FLAG_ASYNC;
ops->obj = obj->handle;
} else {
- op = XE_VM_BIND_OP_UNMAP;
- flags = XE_VM_BIND_FLAG_ASYNC;
+ op = DRM_XE_VM_BIND_OP_UNMAP;
+ flags = DRM_XE_VM_BIND_FLAG_ASYNC;
}
ops->op = op;
@@ -211,7 +211,7 @@ void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine,
tabsyncs[0].handle, tabsyncs[1].handle);
if (num_binds == 1) {
- if ((bind_ops[0].op & 0xffff) == XE_VM_BIND_OP_MAP)
+ if ((bind_ops[0].op & 0xffff) == DRM_XE_VM_BIND_OP_MAP)
xe_vm_bind_async(xe, vm, bind_engine, bind_ops[0].obj, 0,
bind_ops[0].addr, bind_ops[0].range,
syncs, num_syncs);
diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h
index e97d236b8..21b312071 100644
--- a/lib/xe/xe_util.h
+++ b/lib/xe/xe_util.h
@@ -13,9 +13,9 @@
#include <xe_drm.h>
#define XE_IS_SYSMEM_MEMORY_REGION(fd, region) \
- (xe_region_class(fd, region) == XE_MEM_REGION_CLASS_SYSMEM)
+ (xe_region_class(fd, region) == DRM_XE_MEM_REGION_CLASS_SYSMEM)
#define XE_IS_VRAM_MEMORY_REGION(fd, region) \
- (xe_region_class(fd, region) == XE_MEM_REGION_CLASS_VRAM)
+ (xe_region_class(fd, region) == DRM_XE_MEM_REGION_CLASS_VRAM)
struct igt_collection *
__xe_get_memory_region_set(int xe, uint32_t *mem_regions_type, int num_regions);
diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c
index 300b734c8..fa53c0279 100644
--- a/tests/intel/xe_ccs.c
+++ b/tests/intel/xe_ccs.c
@@ -634,8 +634,8 @@ igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
xe_device_get(xe);
set = xe_get_memory_region_set(xe,
- XE_MEM_REGION_CLASS_SYSMEM,
- XE_MEM_REGION_CLASS_VRAM);
+ DRM_XE_MEM_REGION_CLASS_SYSMEM,
+ DRM_XE_MEM_REGION_CLASS_VRAM);
}
igt_describe("Check block-copy uncompressed blit");
diff --git a/tests/intel/xe_debugfs.c b/tests/intel/xe_debugfs.c
index e5bbb364c..9ffc6f6d8 100644
--- a/tests/intel/xe_debugfs.c
+++ b/tests/intel/xe_debugfs.c
@@ -91,20 +91,20 @@ test_base(int fd, struct drm_xe_query_config *config)
igt_assert(config);
sprintf(reference, "devid 0x%llx",
- config->info[XE_QUERY_CONFIG_REV_AND_DEVICE_ID] & 0xffff);
+ config->info[DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID] & 0xffff);
igt_assert(igt_debugfs_search(fd, "info", reference));
sprintf(reference, "revid %lld",
- config->info[XE_QUERY_CONFIG_REV_AND_DEVICE_ID] >> 16);
+ config->info[DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID] >> 16);
igt_assert(igt_debugfs_search(fd, "info", reference));
- sprintf(reference, "is_dgfx %s", config->info[XE_QUERY_CONFIG_FLAGS] &
- XE_QUERY_CONFIG_FLAGS_HAS_VRAM ? "yes" : "no");
+ sprintf(reference, "is_dgfx %s", config->info[DRM_XE_QUERY_CONFIG_FLAGS] &
+ DRM_XE_QUERY_CONFIG_FLAGS_HAS_VRAM ? "yes" : "no");
igt_assert(igt_debugfs_search(fd, "info", reference));
if (!AT_LEAST_GEN(devid, 20)) {
- switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
+ switch (config->info[DRM_XE_QUERY_CONFIG_VA_BITS]) {
case 48:
val = 3;
break;
@@ -121,13 +121,13 @@ test_base(int fd, struct drm_xe_query_config *config)
igt_assert(igt_debugfs_search(fd, "info", reference));
igt_assert(igt_debugfs_exists(fd, "gt0", O_RDONLY));
- if (config->info[XE_QUERY_CONFIG_GT_COUNT] > 1)
+ if (config->info[DRM_XE_QUERY_CONFIG_GT_COUNT] > 1)
igt_assert(igt_debugfs_exists(fd, "gt1", O_RDONLY));
igt_assert(igt_debugfs_exists(fd, "gtt_mm", O_RDONLY));
igt_debugfs_dump(fd, "gtt_mm");
- if (config->info[XE_QUERY_CONFIG_FLAGS] & XE_QUERY_CONFIG_FLAGS_HAS_VRAM) {
+ if (config->info[DRM_XE_QUERY_CONFIG_FLAGS] & DRM_XE_QUERY_CONFIG_FLAGS_HAS_VRAM) {
igt_assert(igt_debugfs_exists(fd, "vram0_mm", O_RDONLY));
igt_debugfs_dump(fd, "vram0_mm");
}
diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c
index 8dbce524d..232ddde8e 100644
--- a/tests/intel/xe_exec_basic.c
+++ b/tests/intel/xe_exec_basic.c
@@ -138,7 +138,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
bo_flags = visible_vram_if_possible(fd, eci->gt_id);
if (flags & DEFER_ALLOC)
- bo_flags |= XE_GEM_CREATE_FLAG_DEFER_BACKING;
+ bo_flags |= DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING;
bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
bo_size, bo_flags);
@@ -172,9 +172,9 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
if (flags & SPARSE)
__xe_vm_bind_assert(fd, vm[i], bind_exec_queues[i],
0, 0, sparse_addr[i], bo_size,
- XE_VM_BIND_OP_MAP,
- XE_VM_BIND_FLAG_ASYNC |
- XE_VM_BIND_FLAG_NULL, sync,
+ DRM_XE_VM_BIND_OP_MAP,
+ DRM_XE_VM_BIND_FLAG_ASYNC |
+ DRM_XE_VM_BIND_FLAG_NULL, sync,
1, 0, 0);
}
diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c
index 92d8690a1..92359d1a7 100644
--- a/tests/intel/xe_exec_fault_mode.c
+++ b/tests/intel/xe_exec_fault_mode.c
@@ -175,12 +175,12 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
if (bo)
xe_vm_bind_async_flags(fd, vm, bind_exec_queues[0], bo, 0,
addr, bo_size, sync, 1,
- XE_VM_BIND_FLAG_IMMEDIATE);
+ DRM_XE_VM_BIND_FLAG_IMMEDIATE);
else
xe_vm_bind_userptr_async_flags(fd, vm, bind_exec_queues[0],
to_user_pointer(data),
addr, bo_size, sync, 1,
- XE_VM_BIND_FLAG_IMMEDIATE);
+ DRM_XE_VM_BIND_FLAG_IMMEDIATE);
} else {
if (bo)
xe_vm_bind_async(fd, vm, bind_exec_queues[0], bo, 0, addr,
diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
index 44248776b..39647b736 100644
--- a/tests/intel/xe_exec_reset.c
+++ b/tests/intel/xe_exec_reset.c
@@ -187,14 +187,14 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs,
for (i = 0; i < n_exec_queues; i++) {
struct drm_xe_ext_set_property job_timeout = {
.base.next_extension = 0,
- .base.name = XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
- .property = XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT,
+ .base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+ .property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT,
.value = 50,
};
struct drm_xe_ext_set_property preempt_timeout = {
.base.next_extension = 0,
- .base.name = XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
- .property = XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT,
+ .base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+ .property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT,
.value = 1000,
};
struct drm_xe_exec_queue_create create = {
@@ -374,14 +374,14 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
for (i = 0; i < n_exec_queues; i++) {
struct drm_xe_ext_set_property job_timeout = {
.base.next_extension = 0,
- .base.name = XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
- .property = XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT,
+ .base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+ .property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT,
.value = 50,
};
struct drm_xe_ext_set_property preempt_timeout = {
.base.next_extension = 0,
- .base.name = XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
- .property = XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT,
+ .base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+ .property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT,
.value = 1000,
};
uint64_t ext = 0;
@@ -542,8 +542,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
for (i = 0; i < n_exec_queues; i++) {
struct drm_xe_ext_set_property preempt_timeout = {
.base.next_extension = 0,
- .base.name = XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
- .property = XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT,
+ .base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+ .property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT,
.value = 1000,
};
uint64_t ext = 0;
diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c
index bb16bdd88..ccbfc4723 100644
--- a/tests/intel/xe_exec_threads.c
+++ b/tests/intel/xe_exec_threads.c
@@ -520,8 +520,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
for (i = 0; i < n_exec_queues; i++) {
struct drm_xe_ext_set_property preempt_timeout = {
.base.next_extension = 0,
- .base.name = XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
- .property = XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT,
+ .base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+ .property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT,
.value = 1000,
};
uint64_t ext = to_user_pointer(&preempt_timeout);
diff --git a/tests/intel/xe_exercise_blt.c b/tests/intel/xe_exercise_blt.c
index 2f349b16d..df774130f 100644
--- a/tests/intel/xe_exercise_blt.c
+++ b/tests/intel/xe_exercise_blt.c
@@ -358,8 +358,8 @@ igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL)
xe_device_get(xe);
set = xe_get_memory_region_set(xe,
- XE_MEM_REGION_CLASS_SYSMEM,
- XE_MEM_REGION_CLASS_VRAM);
+ DRM_XE_MEM_REGION_CLASS_SYSMEM,
+ DRM_XE_MEM_REGION_CLASS_VRAM);
}
igt_describe("Check fast-copy blit");
diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c
index b2976ec84..d07ed4535 100644
--- a/tests/intel/xe_pm.c
+++ b/tests/intel/xe_pm.c
@@ -400,7 +400,7 @@ static void test_vram_d3cold_threshold(device_t device, int sysfs_fd)
igt_assert_eq(igt_ioctl(device.fd_xe, DRM_IOCTL_XE_DEVICE_QUERY, &query), 0);
for (i = 0; i < mem_usage->num_regions; i++) {
- if (mem_usage->regions[i].mem_class == XE_MEM_REGION_CLASS_VRAM) {
+ if (mem_usage->regions[i].mem_class == DRM_XE_MEM_REGION_CLASS_VRAM) {
vram_used_mb += (mem_usage->regions[i].used / (1024 * 1024));
vram_total_mb += (mem_usage->regions[i].total_size / (1024 * 1024));
}
diff --git a/tests/intel/xe_query.c b/tests/intel/xe_query.c
index dc19a9d32..c8d886bfe 100644
--- a/tests/intel/xe_query.c
+++ b/tests/intel/xe_query.c
@@ -163,9 +163,9 @@ void process_hwconfig(void *data, uint32_t len)
const char *get_topo_name(int value)
{
switch(value) {
- case XE_TOPO_DSS_GEOMETRY: return "DSS_GEOMETRY";
- case XE_TOPO_DSS_COMPUTE: return "DSS_COMPUTE";
- case XE_TOPO_EU_PER_DSS: return "EU_PER_DSS";
+ case DRM_XE_TOPO_DSS_GEOMETRY: return "DSS_GEOMETRY";
+ case DRM_XE_TOPO_DSS_COMPUTE: return "DSS_COMPUTE";
+ case DRM_XE_TOPO_EU_PER_DSS: return "EU_PER_DSS";
}
return "??";
}
@@ -221,9 +221,9 @@ test_query_mem_usage(int fd)
for (i = 0; i < mem_usage->num_regions; i++) {
igt_info("mem region %d: %s\t%#llx / %#llx\n", i,
mem_usage->regions[i].mem_class ==
- XE_MEM_REGION_CLASS_SYSMEM ? "SYSMEM"
+ DRM_XE_MEM_REGION_CLASS_SYSMEM ? "SYSMEM"
:mem_usage->regions[i].mem_class ==
- XE_MEM_REGION_CLASS_VRAM ? "VRAM" : "?",
+ DRM_XE_MEM_REGION_CLASS_VRAM ? "VRAM" : "?",
mem_usage->regions[i].used,
mem_usage->regions[i].total_size
);
@@ -359,27 +359,27 @@ test_query_config(int fd)
query.data = to_user_pointer(config);
igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query), 0);
- igt_info("XE_QUERY_CONFIG_REV_AND_DEVICE_ID\t%#llx\n",
- config->info[XE_QUERY_CONFIG_REV_AND_DEVICE_ID]);
+ igt_info("DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID\t%#llx\n",
+ config->info[DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID]);
igt_info(" REV_ID\t\t\t\t%#llx\n",
- config->info[XE_QUERY_CONFIG_REV_AND_DEVICE_ID] >> 16);
+ config->info[DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID] >> 16);
igt_info(" DEVICE_ID\t\t\t\t%#llx\n",
- config->info[XE_QUERY_CONFIG_REV_AND_DEVICE_ID] & 0xffff);
- igt_info("XE_QUERY_CONFIG_FLAGS\t\t\t%#llx\n",
- config->info[XE_QUERY_CONFIG_FLAGS]);
- igt_info(" XE_QUERY_CONFIG_FLAGS_HAS_VRAM\t%s\n",
- config->info[XE_QUERY_CONFIG_FLAGS] &
- XE_QUERY_CONFIG_FLAGS_HAS_VRAM ? "ON":"OFF");
- igt_info("XE_QUERY_CONFIG_MIN_ALIGNMENT\t\t%#llx\n",
- config->info[XE_QUERY_CONFIG_MIN_ALIGNMENT]);
- igt_info("XE_QUERY_CONFIG_VA_BITS\t\t\t%llu\n",
- config->info[XE_QUERY_CONFIG_VA_BITS]);
- igt_info("XE_QUERY_CONFIG_GT_COUNT\t\t%llu\n",
- config->info[XE_QUERY_CONFIG_GT_COUNT]);
- igt_info("XE_QUERY_CONFIG_MEM_REGION_COUNT\t%llu\n",
- config->info[XE_QUERY_CONFIG_MEM_REGION_COUNT]);
- igt_info("XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY\t%llu\n",
- config->info[XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY]);
+ config->info[DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID] & 0xffff);
+ igt_info("DRM_XE_QUERY_CONFIG_FLAGS\t\t\t%#llx\n",
+ config->info[DRM_XE_QUERY_CONFIG_FLAGS]);
+ igt_info(" DRM_XE_QUERY_CONFIG_FLAGS_HAS_VRAM\t%s\n",
+ config->info[DRM_XE_QUERY_CONFIG_FLAGS] &
+ DRM_XE_QUERY_CONFIG_FLAGS_HAS_VRAM ? "ON":"OFF");
+ igt_info("DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT\t\t%#llx\n",
+ config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT]);
+ igt_info("DRM_XE_QUERY_CONFIG_VA_BITS\t\t\t%llu\n",
+ config->info[DRM_XE_QUERY_CONFIG_VA_BITS]);
+ igt_info("DRM_XE_QUERY_CONFIG_GT_COUNT\t\t%llu\n",
+ config->info[DRM_XE_QUERY_CONFIG_GT_COUNT]);
+ igt_info("DRM_XE_QUERY_CONFIG_MEM_REGION_COUNT\t%llu\n",
+ config->info[DRM_XE_QUERY_CONFIG_MEM_REGION_COUNT]);
+ igt_info("DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY\t%llu\n",
+ config->info[DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY]);
dump_hex_debug(config, query.size);
free(config);
diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
index dd3302337..73dc23771 100644
--- a/tests/intel/xe_vm.c
+++ b/tests/intel/xe_vm.c
@@ -316,7 +316,7 @@ static void userptr_invalid(int fd)
vm = xe_vm_create(fd, 0, 0);
munmap(data, size);
ret = __xe_vm_bind(fd, vm, 0, 0, to_user_pointer(data), 0x40000,
- size, XE_VM_BIND_OP_MAP_USERPTR, 0, NULL, 0, 0, 0);
+ size, DRM_XE_VM_BIND_OP_MAP_USERPTR, 0, NULL, 0, 0, 0);
igt_assert(ret == -EFAULT);
xe_vm_destroy(fd, vm);
@@ -752,8 +752,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
bind_ops[i].range = bo_size;
bind_ops[i].addr = addr;
bind_ops[i].tile_mask = 0x1 << eci->gt_id;
- bind_ops[i].op = XE_VM_BIND_OP_MAP;
- bind_ops[i].flags = XE_VM_BIND_FLAG_ASYNC;
+ bind_ops[i].op = DRM_XE_VM_BIND_OP_MAP;
+ bind_ops[i].flags = DRM_XE_VM_BIND_FLAG_ASYNC;
bind_ops[i].region = 0;
bind_ops[i].reserved[0] = 0;
bind_ops[i].reserved[1] = 0;
@@ -797,8 +797,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
for (i = 0; i < n_execs; ++i) {
bind_ops[i].obj = 0;
- bind_ops[i].op = XE_VM_BIND_OP_UNMAP;
- bind_ops[i].flags = XE_VM_BIND_FLAG_ASYNC;
+ bind_ops[i].op = DRM_XE_VM_BIND_OP_UNMAP;
+ bind_ops[i].flags = DRM_XE_VM_BIND_FLAG_ASYNC;
}
syncobj_reset(fd, &sync[0].handle, 1);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 08/20] drm-uapi/xe: Add _FLAG to uAPI constants usable for flags
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (6 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 07/20] drm-uapi/xe: Add missing DRM_ prefix in uAPI constants Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 09/20] drm-uapi/xe: Make constant comments visible in kernel doc Francois Dugast
` (12 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
Align with commit ("Add _FLAG to uAPI constants usable for flags")
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
include/drm-uapi/xe_drm.h | 30 +++----
lib/igt_fb.c | 2 +-
lib/intel_batchbuffer.c | 12 +--
lib/intel_compute.c | 6 +-
lib/intel_ctx.c | 4 +-
lib/xe/xe_ioctl.c | 6 +-
lib/xe/xe_query.c | 4 +-
lib/xe/xe_spin.c | 4 +-
lib/xe/xe_util.c | 4 +-
tests/intel/xe_ccs.c | 4 +-
tests/intel/xe_create.c | 6 +-
tests/intel/xe_dma_buf_sync.c | 4 +-
tests/intel/xe_drm_fdinfo.c | 18 ++---
tests/intel/xe_evict.c | 24 +++---
tests/intel/xe_exec_balancer.c | 34 ++++----
tests/intel/xe_exec_basic.c | 16 ++--
tests/intel/xe_exec_compute_mode.c | 6 +-
tests/intel/xe_exec_fault_mode.c | 14 ++--
tests/intel/xe_exec_reset.c | 42 +++++-----
tests/intel/xe_exec_store.c | 16 ++--
tests/intel/xe_exec_threads.c | 44 +++++------
tests/intel/xe_exercise_blt.c | 2 +-
tests/intel/xe_guc_pc.c | 12 +--
tests/intel/xe_huc_copy.c | 4 +-
tests/intel/xe_intel_bb.c | 2 +-
tests/intel/xe_noexec_ping_pong.c | 2 +-
tests/intel/xe_pm.c | 12 +--
tests/intel/xe_pm_residency.c | 2 +-
tests/intel/xe_spin_batch.c | 2 +-
tests/intel/xe_vm.c | 122 ++++++++++++++---------------
tests/intel/xe_waitfence.c | 4 +-
31 files changed, 232 insertions(+), 232 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 05e644fb3..7d0a5adc5 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -660,10 +660,10 @@ struct drm_xe_vm_create {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
-#define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0)
-#define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1)
-#define DRM_XE_VM_CREATE_ASYNC_DEFAULT (0x1 << 2)
-#define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3)
+#define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (0x1 << 0)
+#define DRM_XE_VM_CREATE_FLAG_COMPUTE_MODE (0x1 << 1)
+#define DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT (0x1 << 2)
+#define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (0x1 << 3)
/** @flags: Flags */
__u32 flags;
@@ -895,11 +895,11 @@ struct drm_xe_sync {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
-#define DRM_XE_SYNC_SYNCOBJ 0x0
-#define DRM_XE_SYNC_TIMELINE_SYNCOBJ 0x1
-#define DRM_XE_SYNC_DMA_BUF 0x2
-#define DRM_XE_SYNC_USER_FENCE 0x3
-#define DRM_XE_SYNC_SIGNAL 0x10
+#define DRM_XE_SYNC_FLAG_SYNCOBJ 0x0
+#define DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ 0x1
+#define DRM_XE_SYNC_FLAG_DMA_BUF 0x2
+#define DRM_XE_SYNC_FLAG_USER_FENCE 0x3
+#define DRM_XE_SYNC_FLAG_SIGNAL 0x10
__u32 flags;
/** @pad: MBZ */
@@ -985,8 +985,8 @@ struct drm_xe_wait_user_fence {
/** @op: wait operation (type of comparison) */
__u16 op;
-#define DRM_XE_UFENCE_WAIT_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */
-#define DRM_XE_UFENCE_WAIT_ABSTIME (1 << 1)
+#define DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */
+#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 1)
/** @flags: wait flags */
__u16 flags;
@@ -1004,10 +1004,10 @@ struct drm_xe_wait_user_fence {
__u64 mask;
/**
* @timeout: how long to wait before bailing, value in nanoseconds.
- * Without DRM_XE_UFENCE_WAIT_ABSTIME flag set (relative timeout)
+ * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout)
* it contains timeout expressed in nanoseconds to wait (fence will
* expire at now() + timeout).
- * When DRM_XE_UFENCE_WAIT_ABSTIME flat is set (absolute timeout) wait
+ * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait
* will end at timeout (uses system MONOTONIC_CLOCK).
* Passing negative timeout leads to neverending wait.
*
@@ -1020,13 +1020,13 @@ struct drm_xe_wait_user_fence {
/**
* @num_engines: number of engine instances to wait on, must be zero
- * when DRM_XE_UFENCE_WAIT_SOFT_OP set
+ * when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set
*/
__u64 num_engines;
/**
* @instances: user pointer to array of drm_xe_engine_class_instance to
- * wait on, must be NULL when DRM_XE_UFENCE_WAIT_SOFT_OP set
+ * wait on, must be NULL when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set
*/
__u64 instances;
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 34934855a..d02dd7a0d 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -2892,7 +2892,7 @@ static void blitcopy(const struct igt_fb *dst_fb,
&bb_size,
mem_region) == 0);
} else if (is_xe) {
- vm = xe_vm_create(dst_fb->fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(dst_fb->fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
exec_queue = xe_exec_queue_create(dst_fb->fd, vm, &inst, 0);
xe_ctx = intel_ctx_xe(dst_fb->fd, vm, exec_queue, 0, 0, 0);
mem_region = vram_if_possible(dst_fb->fd, 0);
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index bea03ff39..0b8aca2ca 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -953,7 +953,7 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
if (!vm) {
igt_assert_f(!ctx, "No vm provided for engine");
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
}
ibb->uses_full_ppgtt = true;
@@ -1315,8 +1315,8 @@ static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(struct intel_bb *ibb,
static void __unbind_xe_objects(struct intel_bb *ibb)
{
struct drm_xe_sync syncs[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
int ret;
@@ -2302,8 +2302,8 @@ __xe_bb_exec(struct intel_bb *ibb, uint64_t flags, bool sync)
uint32_t engine = flags & (I915_EXEC_BSD_MASK | I915_EXEC_RING_MASK);
uint32_t engine_id;
struct drm_xe_sync syncs[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_vm_bind_op *bind_ops;
void *map;
@@ -2371,7 +2371,7 @@ __xe_bb_exec(struct intel_bb *ibb, uint64_t flags, bool sync)
}
ibb->xe_bound = true;
- syncs[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ syncs[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
ibb->engine_syncobj = syncobj_create(ibb->fd, 0);
syncs[1].handle = ibb->engine_syncobj;
diff --git a/lib/intel_compute.c b/lib/intel_compute.c
index 1ae33cdfc..e27043545 100644
--- a/lib/intel_compute.c
+++ b/lib/intel_compute.c
@@ -79,7 +79,7 @@ static void bo_execenv_create(int fd, struct bo_execenv *execenv)
else
engine_class = DRM_XE_ENGINE_CLASS_COMPUTE;
- execenv->vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ execenv->vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
execenv->exec_queue = xe_exec_queue_create_class(fd, execenv->vm,
engine_class);
}
@@ -105,7 +105,7 @@ static void bo_execenv_bind(struct bo_execenv *execenv,
uint64_t alignment = xe_get_default_alignment(fd);
struct drm_xe_sync sync = { 0 };
- sync.flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL;
+ sync.flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL;
sync.handle = syncobj_create(fd, 0);
for (int i = 0; i < entries; i++) {
@@ -161,7 +161,7 @@ static void bo_execenv_unbind(struct bo_execenv *execenv,
uint32_t vm = execenv->vm;
struct drm_xe_sync sync = { 0 };
- sync.flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL;
+ sync.flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL;
sync.handle = syncobj_create(fd, 0);
for (int i = 0; i < entries; i++) {
diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c
index f927b7df8..f82564572 100644
--- a/lib/intel_ctx.c
+++ b/lib/intel_ctx.c
@@ -423,8 +423,8 @@ intel_ctx_t *intel_ctx_xe(int fd, uint32_t vm, uint32_t exec_queue,
int __intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset)
{
struct drm_xe_sync syncs[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.exec_queue_id = ctx->exec_queue,
diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 21a85225f..06c3cb782 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -399,7 +399,7 @@ void xe_exec_sync(int fd, uint32_t exec_queue, uint64_t addr,
void xe_exec_wait(int fd, uint32_t exec_queue, uint64_t addr)
{
struct drm_xe_sync sync = {
- .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+ .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL,
.handle = syncobj_create(fd, 0),
};
@@ -416,7 +416,7 @@ int64_t xe_wait_ufence(int fd, uint64_t *addr, uint64_t value,
struct drm_xe_wait_user_fence wait = {
.addr = to_user_pointer(addr),
.op = DRM_XE_UFENCE_WAIT_EQ,
- .flags = !eci ? DRM_XE_UFENCE_WAIT_SOFT_OP : 0,
+ .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP : 0,
.value = value,
.mask = DRM_XE_UFENCE_WAIT_U64,
.timeout = timeout,
@@ -448,7 +448,7 @@ int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value,
struct drm_xe_wait_user_fence wait = {
.addr = to_user_pointer(addr),
.op = DRM_XE_UFENCE_WAIT_EQ,
- .flags = !eci ? DRM_XE_UFENCE_WAIT_SOFT_OP | DRM_XE_UFENCE_WAIT_ABSTIME : 0,
+ .flags = !eci ? DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP | DRM_XE_UFENCE_WAIT_FLAG_ABSTIME : 0,
.value = value,
.mask = DRM_XE_UFENCE_WAIT_U64,
.timeout = timeout,
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index bb54f0fd6..76e245f9c 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -314,8 +314,8 @@ bool xe_supports_faults(int fd)
bool supports_faults;
struct drm_xe_vm_create create = {
- .flags = DRM_XE_VM_CREATE_ASYNC_DEFAULT |
- DRM_XE_VM_CREATE_FAULT_MODE,
+ .flags = DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT |
+ DRM_XE_VM_CREATE_FLAG_FAULT_MODE,
};
supports_faults = !igt_ioctl(fd, DRM_IOCTL_XE_VM_CREATE, &create);
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index b05b38829..cfc663acc 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -191,7 +191,7 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt)
struct igt_spin *spin;
struct xe_spin *xe_spin;
struct drm_xe_sync sync = {
- .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+ .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL,
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -288,7 +288,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
uint32_t vm, bo, exec_queue, syncobj;
struct xe_spin *spin;
struct drm_xe_sync sync = {
- .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+ .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL,
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c
index 780125f92..2635edf72 100644
--- a/lib/xe/xe_util.c
+++ b/lib/xe/xe_util.c
@@ -179,8 +179,8 @@ void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine,
{
struct drm_xe_vm_bind_op *bind_ops;
struct drm_xe_sync tabsyncs[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ, .handle = sync_in },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, .handle = sync_out },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ, .handle = sync_in },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, .handle = sync_out },
};
struct drm_xe_sync *syncs;
uint32_t num_binds = 0;
diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c
index fa53c0279..1d5b286f3 100644
--- a/tests/intel/xe_ccs.c
+++ b/tests/intel/xe_ccs.c
@@ -343,7 +343,7 @@ static void block_copy(int xe,
uint32_t vm, exec_queue;
if (config->new_ctx) {
- vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
exec_queue = xe_exec_queue_create(xe, vm, &inst, 0);
surf_ctx = intel_ctx_xe(xe, vm, exec_queue, 0, 0, 0);
surf_ahnd = intel_allocator_open(xe, surf_ctx->vm,
@@ -550,7 +550,7 @@ static void block_copy_test(int xe,
copyfns[copy_function].suffix) {
uint32_t sync_bind, sync_out;
- vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
exec_queue = xe_exec_queue_create(xe, vm, &inst, 0);
sync_bind = syncobj_create(xe, 0);
sync_out = syncobj_create(xe, 0);
diff --git a/tests/intel/xe_create.c b/tests/intel/xe_create.c
index d99bd51cf..4242e1a67 100644
--- a/tests/intel/xe_create.c
+++ b/tests/intel/xe_create.c
@@ -54,7 +54,7 @@ static void create_invalid_size(int fd)
uint32_t handle;
int ret;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
xe_for_each_mem_region(fd, memreg, region) {
memregion = xe_mem_region(fd, region);
@@ -140,7 +140,7 @@ static void create_execqueues(int fd, enum exec_queue_destroy ed)
fd = drm_reopen_driver(fd);
num_engines = xe_number_hw_engines(fd);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
exec_queues_per_process = max_t(uint32_t, 1, MAXEXECQUEUES / nproc);
igt_debug("nproc: %u, exec_queues per process: %u\n", nproc, exec_queues_per_process);
@@ -199,7 +199,7 @@ static void create_massive_size(int fd)
uint32_t handle;
int ret;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
xe_for_each_mem_region(fd, memreg, region) {
ret = __create_bo(fd, vm, -1ULL << 32, region, &handle);
diff --git a/tests/intel/xe_dma_buf_sync.c b/tests/intel/xe_dma_buf_sync.c
index 5c401b6dd..0d835dddb 100644
--- a/tests/intel/xe_dma_buf_sync.c
+++ b/tests/intel/xe_dma_buf_sync.c
@@ -144,8 +144,8 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
uint64_t sdi_addr = addr + sdi_offset;
uint64_t spin_offset = (char *)&data[i]->spin - (char *)data[i];
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 64168ed19..4ef30cf49 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -48,8 +48,8 @@ static void test_active(int fd, struct drm_xe_engine_class_instance *eci)
uint32_t vm;
uint64_t addr = 0x1a0000;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -71,7 +71,7 @@ static void test_active(int fd, struct drm_xe_engine_class_instance *eci)
struct xe_spin_opts spin_opts = { .preempt = true };
int i, b, ret;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * N_EXEC_QUEUES;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -110,20 +110,20 @@ static void test_active(int fd, struct drm_xe_engine_class_instance *eci)
xe_spin_init(&data[i].spin, &spin_opts);
exec.exec_queue_id = exec_queues[e];
exec.address = spin_opts.addr;
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
xe_exec(fd, &exec);
xe_spin_wait_started(&data[i].spin);
addr += bo_size;
- sync[1].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
xe_vm_bind_async(fd, vm, bind_exec_queues[e], bo, 0, addr,
bo_size, sync + 1, 1);
addr += bo_size;
} else {
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_bind_async(fd, vm, bind_exec_queues[e], bo, 0, addr,
bo_size, sync, 1);
}
@@ -149,7 +149,7 @@ static void test_active(int fd, struct drm_xe_engine_class_instance *eci)
syncobj_destroy(fd, sync[0].handle);
sync[0].handle = syncobj_create(fd, 0);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_all_async(fd, vm, 0, bo, sync, 1);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
@@ -221,7 +221,7 @@ static void test_total_resident(int xe)
uint64_t addr = 0x1a0000;
int ret;
- vm = xe_vm_create(xe, DRM_XE_VM_CREATE_SCRATCH_PAGE, 0);
+ vm = xe_vm_create(xe, DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE, 0);
xe_for_each_mem_region(xe, memreg, region) {
uint64_t pre_size;
diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c
index eec001218..53aa402a3 100644
--- a/tests/intel/xe_evict.c
+++ b/tests/intel/xe_evict.c
@@ -38,8 +38,8 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
uint32_t bind_exec_queues[3] = { 0, 0, 0 };
uint64_t addr = 0x100000000, base_addr = 0x100000000;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -63,12 +63,12 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
fd = drm_open_driver(DRIVER_XE);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
if (flags & BIND_EXEC_QUEUE)
bind_exec_queues[0] = xe_bind_exec_queue_create(fd, vm, 0, true);
if (flags & MULTI_VM) {
- vm2 = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
- vm3 = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm2 = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
+ vm3 = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
if (flags & BIND_EXEC_QUEUE) {
bind_exec_queues[1] = xe_bind_exec_queue_create(fd, vm2,
0, true);
@@ -121,7 +121,7 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
ALIGN(sizeof(*data) * n_execs, 0x1000));
if (i < n_execs / 2) {
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[0].handle = syncobj_create(fd, 0);
if (flags & MULTI_VM) {
xe_vm_bind_async(fd, vm3, bind_exec_queues[2], __bo,
@@ -149,7 +149,7 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
data[i].batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
if (i >= n_exec_queues)
syncobj_reset(fd, &syncobjs[e], 1);
sync[1].handle = syncobjs[e];
@@ -216,7 +216,7 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
uint64_t addr = 0x100000000, base_addr = 0x100000000;
#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
struct drm_xe_sync sync[1] = {
- { .flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
+ { .flags = DRM_XE_SYNC_FLAG_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL,
.timeline_value = USER_FENCE_VALUE },
};
struct drm_xe_exec exec = {
@@ -242,13 +242,13 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
fd = drm_open_driver(DRIVER_XE);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
- DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT |
+ DRM_XE_VM_CREATE_FLAG_COMPUTE_MODE, 0);
if (flags & BIND_EXEC_QUEUE)
bind_exec_queues[0] = xe_bind_exec_queue_create(fd, vm, 0, true);
if (flags & MULTI_VM) {
- vm2 = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
- DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
+ vm2 = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT |
+ DRM_XE_VM_CREATE_FLAG_COMPUTE_MODE, 0);
if (flags & BIND_EXEC_QUEUE)
bind_exec_queues[1] = xe_bind_exec_queue_create(fd, vm2,
0, true);
diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c
index 3ca3de881..8a0165b8c 100644
--- a/tests/intel/xe_exec_balancer.c
+++ b/tests/intel/xe_exec_balancer.c
@@ -37,8 +37,8 @@ static void test_all_active(int fd, int gt, int class)
uint32_t vm;
uint64_t addr = 0x1a0000;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -66,7 +66,7 @@ static void test_all_active(int fd, int gt, int class)
if (num_placements < 2)
return;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * num_placements;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
@@ -93,8 +93,8 @@ static void test_all_active(int fd, int gt, int class)
for (i = 0; i < num_placements; i++) {
spin_opts.addr = addr + (char *)&data[i].spin - (char *)data;
xe_spin_init(&data[i].spin, &spin_opts);
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[i];
exec.exec_queue_id = exec_queues[i];
@@ -110,7 +110,7 @@ static void test_all_active(int fd, int gt, int class)
}
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
@@ -176,8 +176,8 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs,
uint32_t vm;
uint64_t addr = 0x1a0000;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_syncs = 2,
@@ -207,7 +207,7 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs,
if (num_placements < 2)
return;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
@@ -269,8 +269,8 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs,
data[i].batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
exec.exec_queue_id = exec_queues[e];
@@ -281,11 +281,11 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs,
xe_exec(fd, &exec);
if (flags & REBIND && i + 1 != n_execs) {
- sync[1].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size,
sync + 1, 1);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
addr += bo_size;
if (bo)
xe_vm_bind_async(fd, vm, 0, bo, 0, addr,
@@ -329,7 +329,7 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs,
NULL));
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
@@ -399,7 +399,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs,
uint64_t addr = 0x1a0000;
#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
struct drm_xe_sync sync[1] = {
- { .flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
+ { .flags = DRM_XE_SYNC_FLAG_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL,
.timeline_value = USER_FENCE_VALUE },
};
struct drm_xe_exec exec = {
@@ -433,8 +433,8 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs,
if (num_placements < 2)
return;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
- DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT |
+ DRM_XE_VM_CREATE_FLAG_COMPUTE_MODE, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c
index 232ddde8e..a401f0165 100644
--- a/tests/intel/xe_exec_basic.c
+++ b/tests/intel/xe_exec_basic.c
@@ -81,8 +81,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
int n_exec_queues, int n_execs, int n_vm, unsigned int flags)
{
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -109,7 +109,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(n_vm <= MAX_N_EXEC_QUEUES);
for (i = 0; i < n_vm; ++i)
- vm[i] = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm[i] = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -199,9 +199,9 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
data[i].batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
sync[0].handle = bind_syncobjs[cur_vm];
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
exec.exec_queue_id = exec_queues[e];
@@ -213,11 +213,11 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
if (flags & REBIND && i + 1 != n_execs) {
uint32_t __vm = vm[cur_vm];
- sync[1].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(fd, __vm, bind_exec_queues[e], 0,
__addr, bo_size, sync + 1, 1);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
addr[i % n_vm] += bo_size;
__addr = addr[i % n_vm];
if (bo)
@@ -266,7 +266,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(syncobj_wait(fd, &bind_syncobjs[i], 1, INT64_MAX, 0,
NULL));
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
for (i = 0; i < n_vm; ++i) {
syncobj_reset(fd, &sync[0].handle, 1);
xe_vm_unbind_async(fd, vm[i], bind_exec_queues[i], 0, addr[i],
diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c
index b0a677dca..20d3fc6e8 100644
--- a/tests/intel/xe_exec_compute_mode.c
+++ b/tests/intel/xe_exec_compute_mode.c
@@ -88,7 +88,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
uint64_t addr = 0x1a0000;
#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
struct drm_xe_sync sync[1] = {
- { .flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
+ { .flags = DRM_XE_SYNC_FLAG_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL,
.timeline_value = USER_FENCE_VALUE },
};
struct drm_xe_exec exec = {
@@ -113,8 +113,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(n_exec_queues <= MAX_N_EXECQUEUES);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
- DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT |
+ DRM_XE_VM_CREATE_FLAG_COMPUTE_MODE, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c
index 92359d1a7..b66f31419 100644
--- a/tests/intel/xe_exec_fault_mode.c
+++ b/tests/intel/xe_exec_fault_mode.c
@@ -8,7 +8,7 @@
* Category: Hardware building block
* Sub-category: execbuf
* Functionality: fault mode
- * GPU requirements: GPU needs support for DRM_XE_VM_CREATE_FAULT_MODE
+ * GPU requirements: GPU needs support for DRM_XE_VM_CREATE_FLAG_FAULT_MODE
*/
#include <fcntl.h>
@@ -107,7 +107,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
uint64_t addr = 0x1a0000;
#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
struct drm_xe_sync sync[1] = {
- { .flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
+ { .flags = DRM_XE_SYNC_FLAG_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL,
.timeline_value = USER_FENCE_VALUE },
};
struct drm_xe_exec exec = {
@@ -131,8 +131,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
- DRM_XE_VM_CREATE_FAULT_MODE, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT |
+ DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -347,7 +347,7 @@ test_atomic(int fd, struct drm_xe_engine_class_instance *eci,
uint64_t addr = 0x1a0000, addr_wait;
#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
struct drm_xe_sync sync[1] = {
- { .flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
+ { .flags = DRM_XE_SYNC_FLAG_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL,
.timeline_value = USER_FENCE_VALUE },
};
struct drm_xe_exec exec = {
@@ -375,8 +375,8 @@ test_atomic(int fd, struct drm_xe_engine_class_instance *eci,
uint32_t *ptr;
int i, b, wait_idx = 0;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
- DRM_XE_VM_CREATE_FAULT_MODE, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT |
+ DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0);
bo_size = sizeof(*data) * n_atomic;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
index 39647b736..195e62911 100644
--- a/tests/intel/xe_exec_reset.c
+++ b/tests/intel/xe_exec_reset.c
@@ -30,8 +30,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
uint32_t vm;
uint64_t addr = 0x1a0000;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -45,7 +45,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
struct xe_spin *spin;
struct xe_spin_opts spin_opts = { .addr = addr, .preempt = false };
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*spin);
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -62,8 +62,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
xe_spin_init(spin, &spin_opts);
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobj;
exec.exec_queue_id = exec_queue;
@@ -78,7 +78,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
igt_assert(syncobj_wait(fd, &syncobj, 1, INT64_MAX, 0, NULL));
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
@@ -140,8 +140,8 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs,
uint32_t vm;
uint64_t addr = 0x1a0000;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_syncs = 2,
@@ -176,7 +176,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs,
if (num_placements < 2)
return;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -257,8 +257,8 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs,
for (j = 0; j < num_placements && flags & PARALLEL; ++j)
batches[j] = exec_addr;
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
exec.exec_queue_id = exec_queues[e];
@@ -288,7 +288,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs,
NULL));
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
@@ -336,8 +336,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
uint32_t vm;
uint64_t addr = 0x1a0000;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -362,7 +362,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
if (flags & CLOSE_FD)
fd = drm_open_driver(DRIVER_XE);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -425,8 +425,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
exec_addr = batch_addr;
}
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
exec.exec_queue_id = exec_queues[e];
@@ -455,7 +455,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
NULL));
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
@@ -501,7 +501,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
uint64_t addr = 0x1a0000;
#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
struct drm_xe_sync sync[1] = {
- { .flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
+ { .flags = DRM_XE_SYNC_FLAG_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL,
.timeline_value = USER_FENCE_VALUE },
};
struct drm_xe_exec exec = {
@@ -528,8 +528,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
if (flags & CLOSE_FD)
fd = drm_open_driver(DRIVER_XE);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
- DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT |
+ DRM_XE_VM_CREATE_FLAG_COMPUTE_MODE, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
index 90684b8cb..46caa2e0c 100644
--- a/tests/intel/xe_exec_store.c
+++ b/tests/intel/xe_exec_store.c
@@ -55,7 +55,7 @@ static void store_dword_batch(struct data *data, uint64_t addr, int value)
static void store(int fd)
{
struct drm_xe_sync sync = {
- .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+ .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL,
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -75,7 +75,7 @@ static void store(int fd)
syncobj = syncobj_create(fd, 0);
sync.handle = syncobj;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data);
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -91,7 +91,7 @@ static void store(int fd)
exec_queue = xe_exec_queue_create(fd, vm, hw_engine, 0);
exec.exec_queue_id = exec_queue;
exec.address = data->addr;
- sync.flags &= DRM_XE_SYNC_SIGNAL;
+ sync.flags &= DRM_XE_SYNC_FLAG_SIGNAL;
xe_exec(fd, &exec);
igt_assert(syncobj_wait(fd, &syncobj, 1, INT64_MAX, 0, NULL));
@@ -112,8 +112,8 @@ static void store(int fd)
static void store_all(int fd, int gt, int class)
{
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, }
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -132,7 +132,7 @@ static void store_all(int fd, int gt, int class)
struct drm_xe_engine_class_instance *hwe;
int i, num_placements = 0;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data);
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -169,8 +169,8 @@ static void store_all(int fd, int gt, int class)
for (i = 0; i < num_placements; i++) {
store_dword_batch(data, addr, i);
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[i];
exec.exec_queue_id = exec_queues[i];
diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c
index ccbfc4723..1c2b66f55 100644
--- a/tests/intel/xe_exec_threads.c
+++ b/tests/intel/xe_exec_threads.c
@@ -47,8 +47,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
int class, int n_exec_queues, int n_execs, unsigned int flags)
{
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_sync sync_all[MAX_N_EXEC_QUEUES];
struct drm_xe_exec exec = {
@@ -77,7 +77,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
}
if (!vm) {
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
owns_vm = true;
}
@@ -125,7 +125,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
&create), 0);
exec_queues[i] = create.exec_queue_id;
syncobjs[i] = syncobj_create(fd, 0);
- sync_all[i].flags = DRM_XE_SYNC_SYNCOBJ;
+ sync_all[i].flags = DRM_XE_SYNC_FLAG_SYNCOBJ;
sync_all[i].handle = syncobjs[i];
};
exec.num_batch_buffer = flags & PARALLEL ? num_placements : 1;
@@ -158,8 +158,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
data[i].batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
exec.exec_queue_id = exec_queues[e];
@@ -173,7 +173,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size,
sync_all, n_exec_queues);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
addr += bo_size;
if (bo)
xe_vm_bind_async(fd, vm, 0, bo, 0, addr,
@@ -221,7 +221,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
NULL));
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
@@ -254,7 +254,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
{
#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
struct drm_xe_sync sync[1] = {
- { .flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL,
+ { .flags = DRM_XE_SYNC_FLAG_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL,
.timeline_value = USER_FENCE_VALUE },
};
struct drm_xe_exec exec = {
@@ -285,8 +285,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
}
if (!vm) {
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT |
- DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT |
+ DRM_XE_VM_CREATE_FLAG_COMPUTE_MODE, 0);
owns_vm = true;
}
@@ -457,8 +457,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
int n_execs, unsigned int flags)
{
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_sync sync_all[MAX_N_EXEC_QUEUES];
struct drm_xe_exec exec = {
@@ -489,7 +489,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
}
if (!vm) {
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
owns_vm = true;
}
@@ -536,7 +536,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
else
bind_exec_queues[i] = 0;
syncobjs[i] = syncobj_create(fd, 0);
- sync_all[i].flags = DRM_XE_SYNC_SYNCOBJ;
+ sync_all[i].flags = DRM_XE_SYNC_FLAG_SYNCOBJ;
sync_all[i].handle = syncobjs[i];
};
@@ -576,8 +576,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
exec_addr = batch_addr;
}
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
exec.exec_queue_id = exec_queues[e];
@@ -599,7 +599,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
0, addr, bo_size,
sync_all, n_exec_queues);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
addr += bo_size;
if (bo)
xe_vm_bind_async(fd, vm, bind_exec_queues[e],
@@ -649,7 +649,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
NULL));
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr,
bo_size, sync, 1);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
@@ -1009,11 +1009,11 @@ static void threads(int fd, int flags)
if (flags & SHARED_VM) {
vm_legacy_mode = xe_vm_create(fd,
- DRM_XE_VM_CREATE_ASYNC_DEFAULT,
+ DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT,
0);
vm_compute_mode = xe_vm_create(fd,
- DRM_XE_VM_CREATE_ASYNC_DEFAULT |
- DRM_XE_VM_CREATE_COMPUTE_MODE,
+ DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT |
+ DRM_XE_VM_CREATE_FLAG_COMPUTE_MODE,
0);
}
diff --git a/tests/intel/xe_exercise_blt.c b/tests/intel/xe_exercise_blt.c
index df774130f..fd310138d 100644
--- a/tests/intel/xe_exercise_blt.c
+++ b/tests/intel/xe_exercise_blt.c
@@ -280,7 +280,7 @@ static void fast_copy_test(int xe,
region1 = igt_collection_get_value(regions, 0);
region2 = igt_collection_get_value(regions, 1);
- vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
exec_queue = xe_exec_queue_create(xe, vm, &inst, 0);
ctx = intel_ctx_xe(xe, vm, exec_queue, 0, 0, 0);
diff --git a/tests/intel/xe_guc_pc.c b/tests/intel/xe_guc_pc.c
index 3f2c4ae23..fa2f20cca 100644
--- a/tests/intel/xe_guc_pc.c
+++ b/tests/intel/xe_guc_pc.c
@@ -37,8 +37,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
uint32_t vm;
uint64_t addr = 0x1a0000;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -60,7 +60,7 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
igt_assert(n_execs > 0);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -95,8 +95,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
data[i].batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
exec.exec_queue_id = exec_queues[e];
@@ -114,7 +114,7 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr,
bo_size, sync, 1);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
diff --git a/tests/intel/xe_huc_copy.c b/tests/intel/xe_huc_copy.c
index c71ff74a1..2693a392c 100644
--- a/tests/intel/xe_huc_copy.c
+++ b/tests/intel/xe_huc_copy.c
@@ -117,9 +117,9 @@ test_huc_copy(int fd)
{ .addr = ADDR_BATCH, .size = SIZE_BATCH }, // batch
};
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_VIDEO_DECODE);
- sync.flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL;
+ sync.flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL;
sync.handle = syncobj_create(fd, 0);
for(int i = 0; i < BO_DICT_ENTRIES; i++) {
diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c
index 26e4dcc85..d66996cd5 100644
--- a/tests/intel/xe_intel_bb.c
+++ b/tests/intel/xe_intel_bb.c
@@ -191,7 +191,7 @@ static void simple_bb(struct buf_ops *bops, bool new_context)
intel_bb_reset(ibb, true);
if (new_context) {
- vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
ctx = xe_exec_queue_create(xe, vm, xe_hw_engine(xe, 0), 0);
intel_bb_destroy(ibb);
ibb = intel_bb_create_with_context(xe, ctx, vm, NULL, PAGE_SIZE);
diff --git a/tests/intel/xe_noexec_ping_pong.c b/tests/intel/xe_noexec_ping_pong.c
index 88b22ed11..9c2a70ff3 100644
--- a/tests/intel/xe_noexec_ping_pong.c
+++ b/tests/intel/xe_noexec_ping_pong.c
@@ -64,7 +64,7 @@ static void test_ping_pong(int fd, struct drm_xe_engine_class_instance *eci)
* stats.
*/
for (i = 0; i < NUM_VMS; ++i) {
- vm[i] = xe_vm_create(fd, DRM_XE_VM_CREATE_COMPUTE_MODE, 0);
+ vm[i] = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_COMPUTE_MODE, 0);
for (j = 0; j < NUM_BOS; ++j) {
igt_debug("Creating bo size %lu for vm %u\n",
(unsigned long) bo_size,
diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c
index d07ed4535..18afb68b0 100644
--- a/tests/intel/xe_pm.c
+++ b/tests/intel/xe_pm.c
@@ -231,8 +231,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
uint32_t vm;
uint64_t addr = 0x1a0000;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -259,7 +259,7 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
if (check_rpm)
igt_assert(in_d3(device, d_state));
- vm = xe_vm_create(device.fd_xe, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(device.fd_xe, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
if (check_rpm)
igt_assert(out_of_d3(device, d_state));
@@ -304,8 +304,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
data[i].batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
exec.exec_queue_id = exec_queues[e];
@@ -331,7 +331,7 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
if (check_rpm && runtime_usage_available(device.pci_xe))
rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(device.fd_xe, vm, bind_exec_queues[0], 0, addr,
bo_size, sync, 1);
igt_assert(syncobj_wait(device.fd_xe, &sync[0].handle, 1, INT64_MAX, 0,
diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c
index 8e9197fae..c87eeef3c 100644
--- a/tests/intel/xe_pm_residency.c
+++ b/tests/intel/xe_pm_residency.c
@@ -87,7 +87,7 @@ static void exec_load(int fd, struct drm_xe_engine_class_instance *hwe, unsigned
} *data;
struct drm_xe_sync sync = {
- .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+ .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL,
};
struct drm_xe_exec exec = {
diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index eb5d6aba8..6ab604d9b 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -145,7 +145,7 @@ static void xe_spin_fixed_duration(int fd)
{
struct drm_xe_sync sync = {
.handle = syncobj_create(fd, 0),
- .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+ .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL,
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
index 73dc23771..7164f8c12 100644
--- a/tests/intel/xe_vm.c
+++ b/tests/intel/xe_vm.c
@@ -89,7 +89,7 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
static void
test_scratch(int fd)
{
- uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_SCRATCH_PAGE, 0);
+ uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE, 0);
uint64_t addrs[] = {
0x000000000000ull,
0x7ffdb86402d8ull,
@@ -124,7 +124,7 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
uint64_t bind_addr = addrs[i] & ~(uint64_t)(bo_size - 1);
if (!vm)
- vms[i] = xe_vm_create(fd, DRM_XE_VM_CREATE_SCRATCH_PAGE,
+ vms[i] = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE,
0);
igt_debug("Binding addr %"PRIx64"\n", addrs[i]);
xe_vm_bind_sync(fd, vm ? vm : vms[i], bo, 0,
@@ -214,7 +214,7 @@ test_bind_once(int fd)
uint64_t addr = 0x7ffdb86402d8ull;
__test_bind_one_bo(fd,
- xe_vm_create(fd, DRM_XE_VM_CREATE_SCRATCH_PAGE, 0),
+ xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE, 0),
1, &addr);
}
@@ -234,7 +234,7 @@ test_bind_one_bo_many_times(int fd)
ARRAY_SIZE(addrs_48b);
__test_bind_one_bo(fd,
- xe_vm_create(fd, DRM_XE_VM_CREATE_SCRATCH_PAGE, 0),
+ xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE, 0),
addrs_size, addrs);
}
@@ -272,10 +272,10 @@ static void unbind_all(int fd, int n_vmas)
uint32_t vm;
int i;
struct drm_xe_sync sync[1] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo = xe_bo_create(fd, 0, vm, bo_size);
for (i = 0; i < n_vmas; ++i)
@@ -347,8 +347,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
uint32_t vm;
uint64_t addr = 0x1000 * 512;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_sync sync_all[MAX_N_EXEC_QUEUES + 1];
struct drm_xe_exec exec = {
@@ -372,7 +372,7 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
data = malloc(sizeof(*data) * n_bo);
igt_assert(data);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(struct shared_pte_page_data);
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -387,7 +387,7 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
for (i = 0; i < n_exec_queues; i++) {
exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0);
syncobjs[i] = syncobj_create(fd, 0);
- sync_all[i].flags = DRM_XE_SYNC_SYNCOBJ;
+ sync_all[i].flags = DRM_XE_SYNC_FLAG_SYNCOBJ;
sync_all[i].handle = syncobjs[i];
};
@@ -412,8 +412,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
data[i]->batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i]->batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
exec.exec_queue_id = exec_queues[e];
@@ -425,7 +425,7 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
if (i % 2)
continue;
- sync_all[n_execs].flags = DRM_XE_SYNC_SIGNAL;
+ sync_all[n_execs].flags = DRM_XE_SYNC_FLAG_SIGNAL;
sync_all[n_execs].handle = sync[0].handle;
xe_vm_unbind_async(fd, vm, 0, 0, addr + i * addr_stride,
bo_size, sync_all, n_execs + 1);
@@ -461,8 +461,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
data[i]->batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i]->batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
exec.exec_queue_id = exec_queues[e];
@@ -475,7 +475,7 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
if (!(i % 2))
continue;
- sync_all[n_execs].flags = DRM_XE_SYNC_SIGNAL;
+ sync_all[n_execs].flags = DRM_XE_SYNC_FLAG_SIGNAL;
sync_all[n_execs].handle = sync[0].handle;
xe_vm_unbind_async(fd, vm, 0, 0, addr + i * addr_stride,
bo_size, sync_all, n_execs + 1);
@@ -530,8 +530,8 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec
uint32_t vm;
uint64_t addr = 0x1a0000;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -553,7 +553,7 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec
struct xe_spin_opts spin_opts = { .preempt = true };
int i, b;
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * N_EXEC_QUEUES;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -587,22 +587,22 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec
xe_spin_init(&data[i].spin, &spin_opts);
exec.exec_queue_id = exec_queues[e];
exec.address = spin_opts.addr;
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
xe_exec(fd, &exec);
xe_spin_wait_started(&data[i].spin);
/* Do bind to 1st exec_queue blocked on cork */
addr += (flags & CONFLICT) ? (0x1 << 21) : bo_size;
- sync[1].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
xe_vm_bind_async(fd, vm, bind_exec_queues[e], bo, 0, addr,
bo_size, sync + 1, 1);
addr += bo_size;
} else {
/* Do bind to 2nd exec_queue which blocks write below */
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_bind_async(fd, vm, bind_exec_queues[e], bo, 0, addr,
bo_size, sync, 1);
}
@@ -620,8 +620,8 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec
data[i].batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[!i ? N_EXEC_QUEUES : e];
exec.num_syncs = 2;
@@ -665,7 +665,7 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec
syncobj_destroy(fd, sync[0].handle);
sync[0].handle = syncobj_create(fd, 0);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_all_async(fd, vm, 0, bo, sync, 1);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
@@ -712,8 +712,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
uint32_t vm;
uint64_t addr = 0x1a0000, base_addr = 0x1a0000;
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -733,7 +733,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
igt_assert(n_execs <= BIND_ARRAY_MAX_N_EXEC);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = sizeof(*data) * n_execs;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
@@ -779,8 +779,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
data[i].batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
if (i == n_execs - 1) {
sync[1].handle = syncobj_create(fd, 0);
exec.num_syncs = 2;
@@ -802,8 +802,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
}
syncobj_reset(fd, &sync[0].handle, 1);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
- sync[1].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_bind_array(fd, vm, bind_exec_queue, bind_ops, n_execs, sync, 2);
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
@@ -900,8 +900,8 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
unsigned int flags)
{
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -927,7 +927,7 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
}
igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
if (flags & LARGE_BIND_FLAG_USERPTR) {
map = aligned_alloc(xe_get_default_alignment(fd), bo_size);
@@ -984,8 +984,8 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
data[i].batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
sync[1].handle = syncobjs[e];
if (i != e)
@@ -1007,7 +1007,7 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0, NULL));
syncobj_reset(fd, &sync[0].handle, 1);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
if (flags & LARGE_BIND_FLAG_SPLIT) {
xe_vm_unbind_async(fd, vm, 0, 0, base_addr,
bo_size / 2, NULL, 0);
@@ -1060,7 +1060,7 @@ static void *hammer_thread(void *tdata)
{
struct thread_data *t = tdata;
struct drm_xe_sync sync[1] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -1184,8 +1184,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
unsigned int flags)
{
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -1219,7 +1219,7 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
unbind_n_page_offset *= n_page_per_2mb;
}
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = page_size * bo_n_pages;
if (flags & MAP_FLAG_USERPTR) {
@@ -1287,10 +1287,10 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
data->batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
if (i)
syncobj_reset(fd, &sync[1].handle, 1);
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
exec.exec_queue_id = exec_queue;
exec.address = batch_addr;
@@ -1302,8 +1302,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
/* Unbind some of the pages */
syncobj_reset(fd, &sync[0].handle, 1);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
- sync[1].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
xe_vm_unbind_async(fd, vm, 0, 0,
addr + unbind_n_page_offset * page_size,
unbind_n_pages * page_size, sync, 2);
@@ -1344,9 +1344,9 @@ try_again_after_invalidate:
data->batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
syncobj_reset(fd, &sync[1].handle, 1);
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
exec.exec_queue_id = exec_queue;
exec.address = batch_addr;
@@ -1387,7 +1387,7 @@ try_again_after_invalidate:
/* Confirm unbound region can be rebound */
syncobj_reset(fd, &sync[0].handle, 1);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
if (flags & MAP_FLAG_USERPTR)
xe_vm_bind_userptr_async(fd, vm, 0,
addr + unbind_n_page_offset * page_size,
@@ -1415,9 +1415,9 @@ try_again_after_invalidate:
data->batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
syncobj_reset(fd, &sync[1].handle, 1);
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
exec.exec_queue_id = exec_queue;
exec.address = batch_addr;
@@ -1485,8 +1485,8 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
int unbind_n_pages, unsigned int flags)
{
struct drm_xe_sync sync[2] = {
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
- { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+ { .flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
};
struct drm_xe_exec exec = {
.num_batch_buffer = 1,
@@ -1519,7 +1519,7 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
unbind_n_page_offset *= n_page_per_2mb;
}
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_size = page_size * bo_n_pages;
if (flags & MAP_FLAG_USERPTR) {
@@ -1593,10 +1593,10 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
data->batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
if (i)
syncobj_reset(fd, &sync[1].handle, 1);
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
exec.exec_queue_id = exec_queue;
exec.address = batch_addr;
@@ -1608,8 +1608,8 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
/* Bind some of the pages to different BO / userptr */
syncobj_reset(fd, &sync[0].handle, 1);
- sync[0].flags |= DRM_XE_SYNC_SIGNAL;
- sync[1].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+ sync[1].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
if (flags & MAP_FLAG_USERPTR)
xe_vm_bind_userptr_async(fd, vm, 0, addr + bo_size +
unbind_n_page_offset * page_size,
@@ -1661,10 +1661,10 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
data->batch[b++] = MI_BATCH_BUFFER_END;
igt_assert(b <= ARRAY_SIZE(data[i].batch));
- sync[0].flags &= ~DRM_XE_SYNC_SIGNAL;
+ sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
if (i)
syncobj_reset(fd, &sync[1].handle, 1);
- sync[1].flags |= DRM_XE_SYNC_SIGNAL;
+ sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
exec.exec_queue_id = exec_queue;
exec.address = batch_addr;
diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c
index e0116f181..05060f329 100644
--- a/tests/intel/xe_waitfence.c
+++ b/tests/intel/xe_waitfence.c
@@ -30,7 +30,7 @@ static void do_bind(int fd, uint32_t vm, uint32_t bo, uint64_t offset,
uint64_t addr, uint64_t size, uint64_t val)
{
struct drm_xe_sync sync[1] = {};
- sync[0].flags = DRM_XE_SYNC_USER_FENCE | DRM_XE_SYNC_SIGNAL;
+ sync[0].flags = DRM_XE_SYNC_FLAG_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL;
sync[0].addr = to_user_pointer(&wait_fence);
sync[0].timeline_value = val;
@@ -63,7 +63,7 @@ waitfence(int fd, enum waittype wt)
uint32_t bo_7;
int64_t timeout;
- uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_ASYNC_DEFAULT, 0);
+ uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
bo_1 = xe_bo_create_flags(fd, vm, 0x40000, MY_FLAG);
do_bind(fd, vm, bo_1, 0, 0x200000, 0x40000, 1);
bo_2 = xe_bo_create_flags(fd, vm, 0x40000, MY_FLAG);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 09/20] drm-uapi/xe: Make constant comments visible in kernel doc
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (7 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 08/20] drm-uapi/xe: Add _FLAG to uAPI constants usable for flags Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 10/20] fixup! tests/intel/xe_query: Add a test for querying engine cycles Francois Dugast
` (11 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
Align with commit ("Make constant comments visible in kernel doc")
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
include/drm-uapi/xe_drm.h | 274 +++++++++++++++++++++-----------------
1 file changed, 155 insertions(+), 119 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 7d0a5adc5..250f955cc 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -126,23 +126,40 @@ struct xe_user_extension {
#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
#define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
-/** struct drm_xe_engine_class_instance - instance of an engine class */
+/**
+ * struct drm_xe_engine_class_instance - instance of an engine class
+ *
+ * The @engine_class can be:
+ * - %DRM_XE_ENGINE_CLASS_RENDER
+ * - %DRM_XE_ENGINE_CLASS_COPY
+ * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE
+ * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE
+ * - %DRM_XE_ENGINE_CLASS_COMPUTE
+ * - %DRM_XE_ENGINE_CLASS_VM_BIND_ASYNC - Kernel only class (not actual
+ * hardware engine class) used for creating ordered queues of
+ * asynchronous VM bind operations.
+ * - %DRM_XE_ENGINE_CLASS_VM_BIND_SYNC - Kernel only class (not actual
+ * synchronous VM bind operations.
+ *
+ */
struct drm_xe_engine_class_instance {
#define DRM_XE_ENGINE_CLASS_RENDER 0
#define DRM_XE_ENGINE_CLASS_COPY 1
#define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
#define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
#define DRM_XE_ENGINE_CLASS_COMPUTE 4
- /*
- * Kernel only classes (not actual hardware engine class). Used for
- * creating ordered queues of VM bind operations.
- */
#define DRM_XE_ENGINE_CLASS_VM_BIND_ASYNC 5
#define DRM_XE_ENGINE_CLASS_VM_BIND_SYNC 6
+ /**
+ * @engine_class: Class of this instance among possible
+ * DRM_XE_ENGINE_CLASS_*
+ */
__u16 engine_class;
-
+ /** @engine_instance: Engine instance */
__u16 engine_instance;
+ /** @gt_id: GT ID the instance is associated with */
__u16 gt_id;
+ /** @rsvd: Reserved */
__u16 rsvd;
};
@@ -313,44 +330,36 @@ struct drm_xe_query_mem_usage {
* If a query is made with a struct drm_xe_device_query where .query
* is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses
* struct drm_xe_query_config in .data.
+ *
+ * The index in @info can be:
+ * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits)
+ * and the device revision (next 8 bits)
+ * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device
+ * configuration, see list below
+ *
+ * - %DRM_XE_QUERY_CONFIG_FLAGS_HAS_VRAM - Flag is set if the device
+ * has usable VRAM
+ * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
+ * required by this device, typically SZ_4K or SZ_64K
+ * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
+ * - %DRM_XE_QUERY_CONFIG_GT_COUNT - Total number of GTs for the entire
+ * device
+ * - %DRM_XE_QUERY_CONFIG_MEM_REGION_COUNT - Total number of accessible
+ * memory regions
+ * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest
+ * available exec queue priority
*/
struct drm_xe_query_config {
/** @pad: MBZ */
__u32 pad;
- /*
- * Device ID (lower 16 bits) and the device revision (next
- * 8 bits)
- */
#define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
- /*
- * Flags describing the device configuration, see list below
- */
#define DRM_XE_QUERY_CONFIG_FLAGS 1
- /*
- * Flag is set if the device has usable VRAM
- */
#define DRM_XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0)
- /*
- * Minimal memory alignment required by this device,
- * typically SZ_4K or SZ_64K
- */
#define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
- /*
- * Maximum bits of a virtual address
- */
#define DRM_XE_QUERY_CONFIG_VA_BITS 3
- /*
- * Total number of GTs for the entire device
- */
#define DRM_XE_QUERY_CONFIG_GT_COUNT 4
- /*
- * Total number of accessible memory regions
- */
#define DRM_XE_QUERY_CONFIG_MEM_REGION_COUNT 5
- /*
- * Value of the highest available exec queue priority
- */
#define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 6
/** @info: array of elements containing the config info */
__u64 info[];
@@ -363,6 +372,7 @@ struct drm_xe_query_config {
* existing GT individual descriptions.
* Graphics Technology (GT) is a subset of a GPU/tile that is responsible for
* implementing graphics and/or media operations.
+ *
*/
struct drm_xe_query_gt {
#define DRM_XE_QUERY_GT_TYPE_MAIN 0
@@ -420,34 +430,31 @@ struct drm_xe_query_gt_list {
* If a query is made with a struct drm_xe_device_query where .query
* is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses
* struct drm_xe_query_topology_mask in .data.
+ *
+ * The @type can be:
+ * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices
+ * (DSS) available for geometry operations. For example a query response
+ * containing the following in mask:
+ * ``DSS_GEOMETRY ff ff ff ff 00 00 00 00``
+ * means 32 DSS are available for geometry.
+ * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices
+ * (DSS) available for compute operations. For example a query response
+ * containing the following in mask:
+ * ``DSS_COMPUTE ff ff ff ff 00 00 00 00``
+ * means 32 DSS are available for compute.
+ * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU)
+ * available per Dual Sub Slices (DSS). For example a query response
+ * containing the following in mask:
+ * ``EU_PER_DSS ff ff 00 00 00 00 00 00``
+ * means each DSS has 16 EU.
+ *
*/
struct drm_xe_query_topology_mask {
/** @gt_id: GT ID the mask is associated with */
__u16 gt_id;
- /*
- * To query the mask of Dual Sub Slices (DSS) available for geometry
- * operations. For example a query response containing the following
- * in mask:
- * DSS_GEOMETRY ff ff ff ff 00 00 00 00
- * means 32 DSS are available for geometry.
- */
#define DRM_XE_TOPO_DSS_GEOMETRY (1 << 0)
- /*
- * To query the mask of Dual Sub Slices (DSS) available for compute
- * operations. For example a query response containing the following
- * in mask:
- * DSS_COMPUTE ff ff ff ff 00 00 00 00
- * means 32 DSS are available for compute.
- */
#define DRM_XE_TOPO_DSS_COMPUTE (1 << 1)
- /*
- * To query the mask of Execution Units (EU) available per Dual Sub
- * Slices (DSS). For example a query response containing the following
- * in mask:
- * EU_PER_DSS ff ff 00 00 00 00 00 00
- * means each DSS has 16 EU.
- */
#define DRM_XE_TOPO_EU_PER_DSS (1 << 2)
/** @type: type of mask */
__u16 type;
@@ -466,7 +473,7 @@ struct drm_xe_query_topology_mask {
* of the micro-controller firmware.
*/
struct drm_xe_query_uc_fw_version {
- /** @uc: The micro-controller type to query firmware version */
+ /** @uc_type: The micro-controller type to query firmware version */
#define DRM_XE_QUERY_UC_TYPE_GUC 0
#define DRM_XE_QUERY_UC_TYPE_HUC 1
__u16 uc_type;
@@ -474,13 +481,13 @@ struct drm_xe_query_uc_fw_version {
/** @pad: MBZ */
__u16 pad;
- /* @major_ver: major uc fw version */
+ /** @major_ver: major uc fw version */
__u32 major_ver;
- /* @minor_ver: minor uc fw version */
+ /** @minor_ver: minor uc fw version */
__u32 minor_ver;
- /* @patch_ver: patch uc fw version */
+ /** @patch_ver: patch uc fw version */
__u32 patch_ver;
- /* @branch_ver: branch uc fw version */
+ /** @branch_ver: branch uc fw version */
__u32 branch_ver;
/** @pad2: MBZ */
@@ -497,6 +504,19 @@ struct drm_xe_query_uc_fw_version {
* and sets the value in the query member. This determines the type of
* the structure provided by the driver in data, among struct drm_xe_query_*.
*
+ * The @query can be:
+ * - %DRM_XE_DEVICE_QUERY_ENGINES
+ * - %DRM_XE_DEVICE_QUERY_MEM_USAGE
+ * - %DRM_XE_DEVICE_QUERY_CONFIG
+ * - %DRM_XE_DEVICE_QUERY_GT_LIST - Query type to retrieve the hardware
+ * configuration of the device such as information on slices, memory,
+ * caches, and so on. It is provided as a table of key / value
+ * attributes.
+ * - %DRM_XE_DEVICE_QUERY_HWCONFIG
+ * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY
+ * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES
+ * - %DRM_XE_DEVICE_QUERY_UC_FW_VERSION
+ *
* If size is set to 0, the driver fills it with the required size for
* the requested type of data to query. If size is equal to the required
* size, the queried information is copied into data. If size is set to
@@ -539,11 +559,6 @@ struct drm_xe_device_query {
#define DRM_XE_DEVICE_QUERY_MEM_USAGE 1
#define DRM_XE_DEVICE_QUERY_CONFIG 2
#define DRM_XE_DEVICE_QUERY_GT_LIST 3
- /*
- * Query type to retrieve the hardware configuration of the device
- * such as information on slices, memory, caches, and so on. It is
- * provided as a table of attributes (key / value).
- */
#define DRM_XE_DEVICE_QUERY_HWCONFIG 4
#define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
#define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6
@@ -561,6 +576,29 @@ struct drm_xe_device_query {
__u64 reserved[2];
};
+/**
+ * struct drm_xe_gem_create - structure for gem creation
+ *
+ * The @flags can be:
+ * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING
+ * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
+ * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
+ * possible placement, ensure that the corresponding VRAM allocation
+ * will always use the CPU accessible part of VRAM. This is important
+ * for small-bar systems (on full-bar systems this gets turned into a
+ * noop).
+ * Note1: System memory can be used as an extra placement if the kernel
+ * should spill the allocation to system memory, if space can't be made
+ * available in the CPU accessible part of VRAM (giving the same
+ * behaviour as the i915 interface, see
+ * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS).
+ * Note2: For clear-color CCS surfaces the kernel needs to read the
+ * clear-color value stored in the buffer, and on discrete platforms we
+ * need to use VRAM for display surfaces, therefore the kernel requires
+ * setting this flag for such objects, otherwise an error is thrown on
+ * small-bar systems.
+ *
+ */
struct drm_xe_gem_create {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
@@ -574,21 +612,6 @@ struct drm_xe_gem_create {
#define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
#define DRM_XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
-/*
- * When using VRAM as a possible placement, ensure that the corresponding VRAM
- * allocation will always use the CPU accessible part of VRAM. This is important
- * for small-bar systems (on full-bar systems this gets turned into a noop).
- *
- * Note: System memory can be used as an extra placement if the kernel should
- * spill the allocation to system memory, if space can't be made available in
- * the CPU accessible part of VRAM (giving the same behaviour as the i915
- * interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS).
- *
- * Note: For clear-color CCS surfaces the kernel needs to read the clear-color
- * value stored in the buffer, and on discrete platforms we need to use VRAM for
- * display surfaces, therefore the kernel requires setting this flag for such
- * objects, otherwise an error is thrown on small-bar systems.
- */
#define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26)
/**
* @flags: Flags, currently a mask of memory instances of where BO can
@@ -685,6 +708,30 @@ struct drm_xe_vm_destroy {
__u64 reserved[2];
};
+/**
+ * struct drm_xe_vm_bind_op - run bind operations
+ *
+ * The @op can be:
+ * - %DRM_XE_VM_BIND_OP_MAP
+ * - %DRM_XE_VM_BIND_OP_UNMAP
+ * - %DRM_XE_VM_BIND_OP_MAP_USERPTR
+ * - %DRM_XE_VM_BIND_OP_UNMAP_ALL
+ * - %DRM_XE_VM_BIND_OP_PREFETCH
+ *
+ * and the @flags can be:
+ * - %DRM_XE_VM_BIND_FLAG_READONLY
+ * - %DRM_XE_VM_BIND_FLAG_ASYNC
+ * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - Valid on a faulting VM only, do the
+ * MAP operation immediately rather than deferring the MAP to the page
+ * fault handler.
+ * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page
+ * tables are setup with a special bit which indicates writes are
+ * dropped and all reads return zero. In the future, the NULL flags
+ * will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
+ * handle MBZ, and the BO offset MBZ. This flag is intended to
+ * implement VK sparse bindings.
+ *
+ */
struct drm_xe_vm_bind_op {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
@@ -732,23 +779,12 @@ struct drm_xe_vm_bind_op {
#define DRM_XE_VM_BIND_FLAG_READONLY (0x1 << 0)
#define DRM_XE_VM_BIND_FLAG_ASYNC (0x1 << 1)
- /*
- * Valid on a faulting VM only, do the MAP operation immediately rather
- * than deferring the MAP to the page fault handler.
- */
#define DRM_XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 2)
- /*
- * When the NULL flag is set, the page tables are setup with a special
- * bit which indicates writes are dropped and all reads return zero. In
- * the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP
- * operations, the BO handle MBZ, and the BO offset MBZ. This flag is
- * intended to implement VK sparse bindings.
- */
#define DRM_XE_VM_BIND_FLAG_NULL (0x1 << 3)
/** @flags: Bind flags */
__u32 flags;
- /** @mem_region: Memory region to prefetch VMA to, instance not a mask */
+ /** @region: Memory region to prefetch VMA to, instance not a mask */
__u32 region;
/** @reserved: Reserved */
@@ -1034,6 +1070,35 @@ struct drm_xe_wait_user_fence {
__u64 reserved[2];
};
+/**
+ * struct drm_xe_vm_madvise - give advice about use of memory
+ *
+ * The @property can be:
+ * - %DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS - Setting the preferred
+ * location will trigger a migrate of the VMA backing store to new
+ * location if the backing store is already allocated.
+ * For DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS usage, see enum
+ * drm_xe_memory_class.
+ * - %DRM_XE_VM_MADVISE_PREFERRED_GT
+ * - %DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS_GT - In this case lower 32 bits
+ * are mem class, upper 32 are GT. Combination provides a single IOCTL
+ * plus migrate VMA to preferred location.
+ * - %DRM_XE_VM_MADVISE_CPU_ATOMIC - The CPU will do atomic memory
+ * operations to this VMA. Must be set on some devices for atomics to
+ * behave correctly.
+ * - %DRM_XE_VM_MADVISE_DEVICE_ATOMIC - The device will do atomic memory
+ * operations to this VMA. Must be set on some devices for atomics to
+ * behave correctly.
+ * - %DRM_XE_VM_MADVISE_PRIORITY - Priority WRT to eviction (moving from
+ * preferred memory location due to memory pressure). The lower the
+ * priority, the more likely to be evicted.
+ *
+ * - %DRM_XE_VMA_PRIORITY_LOW
+ * - %DRM_XE_VMA_PRIORITY_NORMAL - Default
+ * - %DRM_XE_VMA_PRIORITY_HIGH - Must be user with elevated privileges
+ * - %DRM_XE_VM_MADVISE_PIN - Pin the VMA in memory, must be user with
+ * elevated privileges
+ */
struct drm_xe_vm_madvise {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
@@ -1050,44 +1115,15 @@ struct drm_xe_vm_madvise {
/** @addr: Address of the VMA to operation on */
__u64 addr;
- /*
- * Setting the preferred location will trigger a migrate of the VMA
- * backing store to new location if the backing store is already
- * allocated.
- *
- * For DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS usage, see enum
- * drm_xe_memory_class.
- */
#define DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS 0
#define DRM_XE_VM_MADVISE_PREFERRED_GT 1
- /*
- * In this case lower 32 bits are mem class, upper 32 are GT.
- * Combination provides a single IOCTL plus migrate VMA to preferred
- * location.
- */
#define DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS_GT 2
- /*
- * The CPU will do atomic memory operations to this VMA. Must be set on
- * some devices for atomics to behave correctly.
- */
#define DRM_XE_VM_MADVISE_CPU_ATOMIC 3
- /*
- * The device will do atomic memory operations to this VMA. Must be set
- * on some devices for atomics to behave correctly.
- */
#define DRM_XE_VM_MADVISE_DEVICE_ATOMIC 4
- /*
- * Priority WRT to eviction (moving from preferred memory location due
- * to memory pressure). The lower the priority, the more likely to be
- * evicted.
- */
#define DRM_XE_VM_MADVISE_PRIORITY 5
#define DRM_XE_VMA_PRIORITY_LOW 0
- /* Default */
#define DRM_XE_VMA_PRIORITY_NORMAL 1
- /* Must be user with elevated privileges */
#define DRM_XE_VMA_PRIORITY_HIGH 2
- /* Pin the VMA in memory, must be user with elevated privileges */
#define DRM_XE_VM_MADVISE_PIN 6
/** @property: property to set */
__u32 property;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 10/20] fixup! tests/intel/xe_query: Add a test for querying engine cycles
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (8 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 09/20] drm-uapi/xe: Make constant comments visible in kernel doc Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 11/20] drm-uapi/xe: Remove GT_TYPE_REMOTE Francois Dugast
` (10 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
---
include/drm-uapi/xe_drm.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 250f955cc..2fc4278ae 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -159,8 +159,8 @@ struct drm_xe_engine_class_instance {
__u16 engine_instance;
/** @gt_id: GT ID the instance is associated with */
__u16 gt_id;
- /** @rsvd: Reserved */
- __u16 rsvd;
+ /** @pad: MBZ */
+ __u16 pad;
};
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 11/20] drm-uapi/xe: Remove GT_TYPE_REMOTE.
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (9 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 10/20] fixup! tests/intel/xe_query: Add a test for querying engine cycles Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-12 18:36 ` Kamil Konieczny
2023-10-11 14:18 ` [igt-dev] [RFC v1 12/20] drm-uapi/xe: Kill VM_MADVISE IOCTL and the atomic tests Francois Dugast
` (9 subsequent siblings)
20 siblings, 1 reply; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Align with commit ("drm/xe/uapi: Remove GT_TYPE_REMOTE")
Cc: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
include/drm-uapi/xe_drm.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 2fc4278ae..09e6bef79 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -376,9 +376,8 @@ struct drm_xe_query_config {
*/
struct drm_xe_query_gt {
#define DRM_XE_QUERY_GT_TYPE_MAIN 0
-#define DRM_XE_QUERY_GT_TYPE_REMOTE 1
-#define DRM_XE_QUERY_GT_TYPE_MEDIA 2
- /** @type: GT type: Main, Remote, or Media */
+#define DRM_XE_QUERY_GT_TYPE_MEDIA 1
+ /** @type: GT type: Main or Media */
__u16 type;
/** @gt_id: Unique ID of this GT within the PCI Device */
__u16 gt_id;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 12/20] drm-uapi/xe: Kill VM_MADVISE IOCTL and the atomic tests
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (10 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 11/20] drm-uapi/xe: Remove GT_TYPE_REMOTE Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 13/20] drm/xe_query: Remove backward compatibility of vram_visible_size Francois Dugast
` (8 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Align with commit ("drm/xe/uapi: Kill VM_MADVISE IOCTL").
Cc: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
include/drm-uapi/xe_drm.h | 92 ++--------------
lib/xe/xe_ioctl.c | 14 ---
lib/xe/xe_ioctl.h | 2 -
tests/intel/xe_exec_fault_mode.c | 174 ++-----------------------------
4 files changed, 20 insertions(+), 262 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 09e6bef79..85f419d16 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -103,28 +103,26 @@ struct xe_user_extension {
#define DRM_XE_VM_CREATE 0x03
#define DRM_XE_VM_DESTROY 0x04
#define DRM_XE_VM_BIND 0x05
-#define DRM_XE_EXEC_QUEUE_CREATE 0x06
-#define DRM_XE_EXEC_QUEUE_DESTROY 0x07
-#define DRM_XE_EXEC 0x08
+#define DRM_XE_EXEC 0x06
+#define DRM_XE_EXEC_QUEUE_CREATE 0x07
+#define DRM_XE_EXEC_QUEUE_DESTROY 0x08
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x09
-#define DRM_XE_WAIT_USER_FENCE 0x0a
-#define DRM_XE_VM_MADVISE 0x0b
-#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x0c
-
+#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x0a
+#define DRM_XE_WAIT_USER_FENCE 0x0b
/* Must be kept compact -- no holes */
+
#define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)
#define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create)
#define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset)
#define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)
-#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
-#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
+#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
+#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
+#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create)
+#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy)
+#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property)
-#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy)
-#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
-#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
-#define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
/**
* struct drm_xe_engine_class_instance - instance of an engine class
@@ -1069,74 +1067,6 @@ struct drm_xe_wait_user_fence {
__u64 reserved[2];
};
-/**
- * struct drm_xe_vm_madvise - give advice about use of memory
- *
- * The @property can be:
- * - %DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS - Setting the preferred
- * location will trigger a migrate of the VMA backing store to new
- * location if the backing store is already allocated.
- * For DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS usage, see enum
- * drm_xe_memory_class.
- * - %DRM_XE_VM_MADVISE_PREFERRED_GT
- * - %DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS_GT - In this case lower 32 bits
- * are mem class, upper 32 are GT. Combination provides a single IOCTL
- * plus migrate VMA to preferred location.
- * - %DRM_XE_VM_MADVISE_CPU_ATOMIC - The CPU will do atomic memory
- * operations to this VMA. Must be set on some devices for atomics to
- * behave correctly.
- * - %DRM_XE_VM_MADVISE_DEVICE_ATOMIC - The device will do atomic memory
- * operations to this VMA. Must be set on some devices for atomics to
- * behave correctly.
- * - %DRM_XE_VM_MADVISE_PRIORITY - Priority WRT to eviction (moving from
- * preferred memory location due to memory pressure). The lower the
- * priority, the more likely to be evicted.
- *
- * - %DRM_XE_VMA_PRIORITY_LOW
- * - %DRM_XE_VMA_PRIORITY_NORMAL - Default
- * - %DRM_XE_VMA_PRIORITY_HIGH - Must be user with elevated privileges
- * - %DRM_XE_VM_MADVISE_PIN - Pin the VMA in memory, must be user with
- * elevated privileges
- */
-struct drm_xe_vm_madvise {
- /** @extensions: Pointer to the first extension struct, if any */
- __u64 extensions;
-
- /** @vm_id: The ID VM in which the VMA exists */
- __u32 vm_id;
-
- /** @pad: MBZ */
- __u32 pad;
-
- /** @range: Number of bytes in the VMA */
- __u64 range;
-
- /** @addr: Address of the VMA to operation on */
- __u64 addr;
-
-#define DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS 0
-#define DRM_XE_VM_MADVISE_PREFERRED_GT 1
-#define DRM_XE_VM_MADVISE_PREFERRED_MEM_CLASS_GT 2
-#define DRM_XE_VM_MADVISE_CPU_ATOMIC 3
-#define DRM_XE_VM_MADVISE_DEVICE_ATOMIC 4
-#define DRM_XE_VM_MADVISE_PRIORITY 5
-#define DRM_XE_VMA_PRIORITY_LOW 0
-#define DRM_XE_VMA_PRIORITY_NORMAL 1
-#define DRM_XE_VMA_PRIORITY_HIGH 2
-#define DRM_XE_VM_MADVISE_PIN 6
- /** @property: property to set */
- __u32 property;
-
- /** @pad2: MBZ */
- __u32 pad2;
-
- /** @value: property value */
- __u64 value;
-
- /** @reserved: Reserved */
- __u64 reserved[2];
-};
-
/**
* DOC: XE PMU event config IDs
*
diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 06c3cb782..db41d5ba5 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -475,17 +475,3 @@ void xe_force_gt_reset(int fd, int gt)
minor(st.st_rdev), gt);
system(reset_string);
}
-
-void xe_vm_madvise(int fd, uint32_t vm, uint64_t addr, uint64_t size,
- uint32_t property, uint32_t value)
-{
- struct drm_xe_vm_madvise madvise = {
- .vm_id = vm,
- .range = size,
- .addr = addr,
- .property = property,
- .value = value,
- };
-
- igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_MADVISE, &madvise), 0);
-}
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index a8dbcf376..d9c97bf22 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -90,7 +90,5 @@ int64_t xe_wait_ufence_abstime(int fd, uint64_t *addr, uint64_t value,
struct drm_xe_engine_class_instance *eci,
int64_t timeout);
void xe_force_gt_reset(int fd, int gt);
-void xe_vm_madvise(int fd, uint32_t vm, uint64_t addr, uint64_t size,
- uint32_t property, uint32_t value);
#endif /* XE_IOCTL_H */
diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c
index b66f31419..92d552f97 100644
--- a/tests/intel/xe_exec_fault_mode.c
+++ b/tests/intel/xe_exec_fault_mode.c
@@ -23,15 +23,15 @@
#include <string.h>
#define MAX_N_EXEC_QUEUES 16
-#define USERPTR (0x1 << 0)
-#define REBIND (0x1 << 1)
-#define INVALIDATE (0x1 << 2)
-#define RACE (0x1 << 3)
-#define BIND_EXEC_QUEUE (0x1 << 4)
-#define WAIT_ATOMIC (0x1 << 5)
-#define IMMEDIATE (0x1 << 6)
-#define PREFETCH (0x1 << 7)
-#define INVALID_FAULT (0x1 << 8)
+
+#define USERPTR (0x1 << 0)
+#define REBIND (0x1 << 1)
+#define INVALIDATE (0x1 << 2)
+#define RACE (0x1 << 3)
+#define BIND_EXEC_QUEUE (0x1 << 4)
+#define IMMEDIATE (0x1 << 5)
+#define PREFETCH (0x1 << 6)
+#define INVALID_FAULT (0x1 << 7)
/**
* SUBTEST: once-%s
@@ -317,146 +317,6 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
close(map_fd);
}
-#define MI_ATOMIC_INLINE_DATA (1 << 18)
-#define MI_ATOMIC_ADD (0x7 << 8)
-
-/**
- * SUBTEST: atomic-once
- * Description: Run atomic fault mode test only once
- * Test category: functionality test
- *
- * SUBTEST: atomic-once-wait
- * Description: Run atomic wait fault mode test once
- * Test category: functionality test
- *
- * SUBTEST: atomic-many
- * Description: Run atomic fault mode test many times
- * Description: atomic many
- * Test category: functionality test
- *
- * SUBTEST: atomic-many-wait
- * Description: Run atomic wait fault mode test many times
- * Test category: functionality test
- *
- */
-static void
-test_atomic(int fd, struct drm_xe_engine_class_instance *eci,
- int n_atomic, unsigned int flags)
-{
- uint32_t vm;
- uint64_t addr = 0x1a0000, addr_wait;
-#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull
- struct drm_xe_sync sync[1] = {
- { .flags = DRM_XE_SYNC_FLAG_USER_FENCE | DRM_XE_SYNC_FLAG_SIGNAL,
- .timeline_value = USER_FENCE_VALUE },
- };
- struct drm_xe_exec exec = {
- .num_batch_buffer = 1,
- .num_syncs = 1,
- .syncs = to_user_pointer(sync),
- };
- uint32_t exec_queue;
- size_t bo_size;
- uint32_t bo, bo_wait;
- struct {
- uint32_t batch[16];
- uint64_t pad;
- uint64_t vm_sync;
- uint64_t exec_sync;
- uint32_t data;
- } *data;
- struct {
- uint32_t batch[16];
- uint64_t pad;
- uint64_t vm_sync;
- uint64_t exec_sync;
- uint32_t data;
- } *wait;
- uint32_t *ptr;
- int i, b, wait_idx = 0;
-
- vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT |
- DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0);
- bo_size = sizeof(*data) * n_atomic;
- bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
- xe_get_default_alignment(fd));
- addr_wait = addr + bo_size;
-
- bo = xe_bo_create_flags(fd, vm, bo_size,
- all_memory_regions(fd) |
- visible_vram_if_possible(fd, 0));
- bo_wait = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
- data = xe_bo_map(fd, bo, bo_size);
- wait = xe_bo_map(fd, bo_wait, bo_size);
- ptr = &data[0].data;
- memset(data, 0, bo_size);
- memset(wait, 0, bo_size);
-
- exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
-
- sync[0].addr = to_user_pointer(&wait[wait_idx].vm_sync);
- xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1);
- xe_wait_ufence(fd, &wait[wait_idx++].vm_sync, USER_FENCE_VALUE, NULL,
- ONE_SEC);
-
- sync[0].addr = to_user_pointer(&wait[wait_idx].vm_sync);
- xe_vm_bind_async(fd, vm, 0, bo_wait, 0, addr_wait, bo_size, sync, 1);
- xe_wait_ufence(fd, &wait[wait_idx++].vm_sync, USER_FENCE_VALUE, NULL,
- ONE_SEC);
-
- xe_vm_madvise(fd, vm, addr, bo_size, DRM_XE_VM_MADVISE_CPU_ATOMIC, 1);
- xe_vm_madvise(fd, vm, addr, bo_size, DRM_XE_VM_MADVISE_DEVICE_ATOMIC, 1);
-
- for (i = 0; i < n_atomic; i++) {
- uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
- uint64_t batch_addr = addr + batch_offset;
- uint64_t sdi_offset = (char *)&data[0].data - (char *)data;
- uint64_t sdi_addr = addr + sdi_offset;
-
- b = 0;
- data[i].batch[b++] = MI_ATOMIC | MI_ATOMIC_INLINE_DATA |
- MI_ATOMIC_ADD;
- data[i].batch[b++] = sdi_addr;
- data[i].batch[b++] = sdi_addr >> 32;
- data[i].batch[b++] = 1;
- data[i].batch[b++] = MI_BATCH_BUFFER_END;
-
- sync[0].addr = addr_wait +
- (char *)&wait[i].exec_sync - (char *)wait;
-
- exec.exec_queue_id = exec_queue;
- exec.address = batch_addr;
- xe_exec(fd, &exec);
-
- if (flags & WAIT_ATOMIC)
- xe_wait_ufence(fd, &wait[i].exec_sync, USER_FENCE_VALUE,
- NULL, ONE_SEC);
- __atomic_add_fetch(ptr, 1, __ATOMIC_SEQ_CST);
- }
-
- xe_wait_ufence(fd, &wait[n_atomic - 1].exec_sync, USER_FENCE_VALUE,
- NULL, ONE_SEC);
- igt_assert(*ptr == n_atomic * 2);
-
- sync[0].addr = to_user_pointer(&wait[wait_idx].vm_sync);
- xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
- xe_wait_ufence(fd, &wait[wait_idx++].vm_sync, USER_FENCE_VALUE, NULL,
- ONE_SEC);
-
- sync[0].addr = to_user_pointer(&wait[wait_idx].vm_sync);
- xe_vm_unbind_async(fd, vm, 0, 0, addr_wait, bo_size, sync, 1);
- xe_wait_ufence(fd, &wait[wait_idx++].vm_sync, USER_FENCE_VALUE, NULL,
- ONE_SEC);
-
- xe_exec_queue_destroy(fd, exec_queue);
- munmap(data, bo_size);
- munmap(wait, bo_size);
- gem_close(fd, bo);
- gem_close(fd, bo_wait);
- xe_vm_destroy(fd, vm);
-}
-
igt_main
{
struct drm_xe_engine_class_instance *hwe;
@@ -546,22 +406,6 @@ igt_main
s->flags);
}
- igt_subtest("atomic-once")
- xe_for_each_hw_engine(fd, hwe)
- test_atomic(fd, hwe, 1, 0);
-
- igt_subtest("atomic-once-wait")
- xe_for_each_hw_engine(fd, hwe)
- test_atomic(fd, hwe, 1, WAIT_ATOMIC);
-
- igt_subtest("atomic-many")
- xe_for_each_hw_engine(fd, hwe)
- test_atomic(fd, hwe, 8, 0);
-
- igt_subtest("atomic-many-wait")
- xe_for_each_hw_engine(fd, hwe)
- test_atomic(fd, hwe, 8, WAIT_ATOMIC);
-
igt_fixture
drm_close_driver(fd);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 13/20] drm/xe_query: Remove backward compatibility of vram_visible_size.
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (11 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 12/20] drm-uapi/xe: Kill VM_MADVISE IOCTL and the atomic tests Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-12 18:39 ` Kamil Konieczny
2023-10-11 14:18 ` [igt-dev] [RFC v1 14/20] xe_ioctl: Converge bo_create to the most used version Francois Dugast
` (7 subsequent siblings)
20 siblings, 1 reply; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
We are breaking the uapi compatibility at this time, so this
is useless anyway.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
lib/xe/xe_query.c | 42 +++++++-----------------------------------
1 file changed, 7 insertions(+), 35 deletions(-)
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 76e245f9c..87841e8a3 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -397,16 +397,6 @@ uint64_t vram_memory(int fd, int gt)
return xe_has_vram(fd) ? native_region_for_gt(xe_dev->gt_list, gt) : 0;
}
-static uint64_t __xe_visible_vram_size(int fd, int gt)
-{
- struct xe_device *xe_dev;
-
- xe_dev = find_in_cache(fd);
- igt_assert(xe_dev);
-
- return xe_dev->visible_vram_size[gt];
-}
-
/**
* visible_vram_memory:
* @fd: xe device fd
@@ -418,14 +408,7 @@ static uint64_t __xe_visible_vram_size(int fd, int gt)
*/
uint64_t visible_vram_memory(int fd, int gt)
{
- /*
- * TODO: Keep it backwards compat for now. Fixup once the kernel side
- * has landed.
- */
- if (__xe_visible_vram_size(fd, gt))
- return vram_memory(fd, gt) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
- else
- return vram_memory(fd, gt); /* older kernel */
+ return vram_memory(fd, gt) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
}
/**
@@ -457,14 +440,7 @@ uint64_t visible_vram_if_possible(int fd, int gt)
uint64_t system_memory = regions & 0x1;
uint64_t vram = regions & (0x2 << gt);
- /*
- * TODO: Keep it backwards compat for now. Fixup once the kernel side
- * has landed.
- */
- if (__xe_visible_vram_size(fd, gt))
- return vram ? vram | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
- else
- return vram ? vram : system_memory; /* older kernel */
+ return vram ? vram | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
}
/**
@@ -616,18 +592,14 @@ uint64_t xe_vram_size(int fd, int gt)
*/
uint64_t xe_visible_vram_size(int fd, int gt)
{
- uint64_t visible_size;
+ struct xe_device *xe_dev;
- /*
- * TODO: Keep it backwards compat for now. Fixup once the kernel side
- * has landed.
- */
- visible_size = __xe_visible_vram_size(fd, gt);
- if (!visible_size) /* older kernel */
- visible_size = xe_vram_size(fd, gt);
+ xe_dev = find_in_cache(fd);
+ igt_assert(xe_dev);
- return visible_size;
+ return xe_dev->visible_vram_size[gt];
}
+
/**
* xe_vram_available:
* @fd: xe device fd
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 14/20] xe_ioctl: Converge bo_create to the most used version
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (12 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 13/20] drm/xe_query: Remove backward compatibility of vram_visible_size Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 15/20] xe_ioctl: Rename *xe_bo_create_flags to simply xe_bo_create Francois Dugast
` (6 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Let's unify the call instead of having 2 separated
options for the same goal.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
lib/xe/xe_ioctl.c | 15 ---------------
lib/xe/xe_ioctl.h | 1 -
tests/intel/xe_spin_batch.c | 2 +-
tests/intel/xe_vm.c | 7 ++++---
4 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index db41d5ba5..2edf8a7cf 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -253,21 +253,6 @@ uint32_t xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags)
return handle;
}
-uint32_t xe_bo_create(int fd, int gt, uint32_t vm, uint64_t size)
-{
- struct drm_xe_gem_create create = {
- .vm_id = vm,
- .size = size,
- .flags = vram_if_possible(fd, gt),
- };
- int err;
-
- err = igt_ioctl(fd, DRM_IOCTL_XE_GEM_CREATE, &create);
- igt_assert_eq(err, 0);
-
- return create.handle;
-}
-
uint32_t xe_bind_exec_queue_create(int fd, uint32_t vm, uint64_t ext, bool async)
{
struct drm_xe_engine_class_instance instance = {
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index d9c97bf22..993ba8158 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -67,7 +67,6 @@ void xe_vm_destroy(int fd, uint32_t vm);
uint32_t __xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags,
uint32_t *handle);
uint32_t xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags);
-uint32_t xe_bo_create(int fd, int gt, uint32_t vm, uint64_t size);
uint32_t xe_exec_queue_create(int fd, uint32_t vm,
struct drm_xe_engine_class_instance *instance,
uint64_t ext);
diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index 6ab604d9b..261fde9af 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -169,7 +169,7 @@ static void xe_spin_fixed_duration(int fd)
exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY);
ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
bo_size = ALIGN(sizeof(*spin) + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, 0, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size, vram_if_possible(fd, 0));
spin = xe_bo_map(fd, bo, bo_size);
spin_addr = intel_allocator_alloc_with_strategy(ahnd, bo, bo_size, 0,
ALLOC_STRATEGY_LOW_TO_HIGH);
diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
index 7164f8c12..27d44af7f 100644
--- a/tests/intel/xe_vm.c
+++ b/tests/intel/xe_vm.c
@@ -276,7 +276,7 @@ static void unbind_all(int fd, int n_vmas)
};
vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
- bo = xe_bo_create(fd, 0, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size, vram_if_possible(fd, 0));
for (i = 0; i < n_vmas; ++i)
xe_vm_bind_async(fd, vm, 0, bo, 0, addr + i * bo_size,
@@ -322,6 +322,7 @@ static void userptr_invalid(int fd)
xe_vm_destroy(fd, vm);
}
+
/**
* SUBTEST: shared-%s-page
* Description: Test shared arg[1] page
@@ -1532,9 +1533,9 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(map0 != MAP_FAILED);
igt_assert(map1 != MAP_FAILED);
} else {
- bo0 = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+ bo0 = xe_bo_create_flags(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id));
map0 = xe_bo_map(fd, bo0, bo_size);
- bo1 = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+ bo1 = xe_bo_create_flags(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id));
map1 = xe_bo_map(fd, bo1, bo_size);
}
memset(map0, 0, bo_size);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 15/20] xe_ioctl: Rename *xe_bo_create_flags to simply xe_bo_create
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (13 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 14/20] xe_ioctl: Converge bo_create to the most used version Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 16/20] xe_query: Add missing include Francois Dugast
` (5 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Now that we have only one variant we can unify to the
simplest version.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
lib/igt_draw.c | 6 ++---
lib/igt_fb.c | 6 ++---
lib/intel_batchbuffer.c | 6 ++---
lib/intel_blt.c | 2 +-
lib/intel_bufops.c | 2 +-
lib/xe/xe_ioctl.c | 8 +++---
lib/xe/xe_ioctl.h | 6 ++---
lib/xe/xe_spin.c | 8 +++---
tests/intel/api_intel_allocator.c | 4 +--
tests/intel/kms_big_fb.c | 22 ++++++++--------
tests/intel/xe_ccs.c | 12 ++++-----
tests/intel/xe_dma_buf_sync.c | 4 +--
tests/intel/xe_drm_fdinfo.c | 6 ++---
tests/intel/xe_evict.c | 40 +++++++++++++++---------------
tests/intel/xe_exec_balancer.c | 6 ++---
tests/intel/xe_exec_basic.c | 3 +--
tests/intel/xe_exec_compute_mode.c | 4 +--
tests/intel/xe_exec_fault_mode.c | 10 ++++----
tests/intel/xe_exec_reset.c | 16 ++++++------
tests/intel/xe_exec_store.c | 8 +++---
tests/intel/xe_exec_threads.c | 12 ++++-----
tests/intel/xe_exercise_blt.c | 4 +--
tests/intel/xe_guc_pc.c | 4 +--
tests/intel/xe_intel_bb.c | 2 +-
tests/intel/xe_mmap.c | 32 ++++++++++++------------
tests/intel/xe_noexec_ping_pong.c | 4 +--
tests/intel/xe_pm.c | 6 ++---
tests/intel/xe_pm_residency.c | 4 +--
tests/intel/xe_prime_self_import.c | 28 ++++++++++-----------
tests/intel/xe_spin_batch.c | 2 +-
tests/intel/xe_vm.c | 33 ++++++++++++------------
tests/intel/xe_waitfence.c | 14 +++++------
tests/kms_addfb_basic.c | 2 +-
tests/kms_getfb.c | 2 +-
34 files changed, 163 insertions(+), 165 deletions(-)
diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 476778a13..e37c64fd5 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -789,9 +789,9 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,
if (is_i915_device(fd))
tmp.handle = gem_create(fd, tmp.size);
else
- tmp.handle = xe_bo_create_flags(fd, 0,
- ALIGN(tmp.size, xe_get_default_alignment(fd)),
- visible_vram_if_possible(fd, 0));
+ tmp.handle = xe_bo_create(fd, 0,
+ ALIGN(tmp.size, xe_get_default_alignment(fd)),
+ visible_vram_if_possible(fd, 0));
tmp.stride = rect->w * pixel_size;
tmp.bpp = buf->bpp;
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index d02dd7a0d..39f623585 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -1205,8 +1205,8 @@ static int create_bo_for_fb(struct igt_fb *fb, bool prefer_sysmem)
/* If we can't use fences, we won't use ggtt detiling later. */
igt_assert(err == 0 || err == -EOPNOTSUPP);
} else if (is_xe_device(fd)) {
- fb->gem_handle = xe_bo_create_flags(fd, 0, fb->size,
- visible_vram_if_possible(fd, 0));
+ fb->gem_handle = xe_bo_create(fd, 0, fb->size,
+ visible_vram_if_possible(fd, 0));
} else if (is_vc4_device(fd)) {
fb->gem_handle = igt_vc4_create_bo(fd, fb->size);
@@ -2903,7 +2903,7 @@ static void blitcopy(const struct igt_fb *dst_fb,
bb_size = ALIGN(bb_size + xe_cs_prefetch_size(dst_fb->fd),
xe_get_default_alignment(dst_fb->fd));
- xe_bb = xe_bo_create_flags(dst_fb->fd, 0, bb_size, mem_region);
+ xe_bb = xe_bo_create(dst_fb->fd, 0, bb_size, mem_region);
}
for (int i = 0; i < dst_fb->num_planes - dst_cc; i++) {
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 0b8aca2ca..4ca371956 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -945,7 +945,7 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
ibb->alignment = xe_get_default_alignment(fd);
size = ALIGN(size, ibb->alignment);
- ibb->handle = xe_bo_create_flags(fd, 0, size, visible_vram_if_possible(fd, 0));
+ ibb->handle = xe_bo_create(fd, 0, size, visible_vram_if_possible(fd, 0));
/* Limit to 48-bit due to MI_* address limitation */
ibb->gtt_size = 1ull << min_t(uint32_t, xe_va_bits(fd), 48);
@@ -1403,8 +1403,8 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
if (ibb->driver == INTEL_DRIVER_I915)
ibb->handle = gem_create(ibb->fd, ibb->size);
else
- ibb->handle = xe_bo_create_flags(ibb->fd, 0, ibb->size,
- visible_vram_if_possible(ibb->fd, 0));
+ ibb->handle = xe_bo_create(ibb->fd, 0, ibb->size,
+ visible_vram_if_possible(ibb->fd, 0));
/* Reacquire offset for RELOC and SIMPLE */
if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE ||
diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 429511920..9e4d8c535 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1422,7 +1422,7 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region,
if (blt->driver == INTEL_DRIVER_XE) {
size = ALIGN(size, xe_get_default_alignment(blt->fd));
- handle = xe_bo_create_flags(blt->fd, 0, size, region);
+ handle = xe_bo_create(blt->fd, 0, size, region);
} else {
igt_assert(__gem_create_in_memory_regions(blt->fd, &handle,
&size, region) == 0);
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 2c91adb88..6f3a77f47 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -920,7 +920,7 @@ static void __intel_buf_init(struct buf_ops *bops,
igt_assert_eq(__gem_create(bops->fd, &size, &buf->handle), 0);
} else {
size = ALIGN(size, xe_get_default_alignment(bops->fd));
- buf->handle = xe_bo_create_flags(bops->fd, 0, size, region);
+ buf->handle = xe_bo_create(bops->fd, 0, size, region);
}
}
diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 2edf8a7cf..aafd77966 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -226,8 +226,8 @@ void xe_vm_destroy(int fd, uint32_t vm)
igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_DESTROY, &destroy), 0);
}
-uint32_t __xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags,
- uint32_t *handle)
+uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags,
+ uint32_t *handle)
{
struct drm_xe_gem_create create = {
.vm_id = vm,
@@ -244,11 +244,11 @@ uint32_t __xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags
return 0;
}
-uint32_t xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags)
+uint32_t xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags)
{
uint32_t handle;
- igt_assert_eq(__xe_bo_create_flags(fd, vm, size, flags, &handle), 0);
+ igt_assert_eq(__xe_bo_create(fd, vm, size, flags, &handle), 0);
return handle;
}
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index 993ba8158..294e9bc13 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -64,9 +64,9 @@ void xe_vm_unbind_all_async(int fd, uint32_t vm, uint32_t exec_queue,
uint32_t bo, struct drm_xe_sync *sync,
uint32_t num_syncs);
void xe_vm_destroy(int fd, uint32_t vm);
-uint32_t __xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags,
- uint32_t *handle);
-uint32_t xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags);
+uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags,
+ uint32_t *handle);
+uint32_t xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags);
uint32_t xe_exec_queue_create(int fd, uint32_t vm,
struct drm_xe_engine_class_instance *instance,
uint64_t ext);
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index cfc663acc..828938434 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -219,8 +219,8 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt)
spin->engine = xe_exec_queue_create_class(fd, spin->vm, DRM_XE_ENGINE_CLASS_COPY);
}
- spin->handle = xe_bo_create_flags(fd, spin->vm, bo_size,
- visible_vram_if_possible(fd, 0));
+ spin->handle = xe_bo_create(fd, spin->vm, bo_size,
+ visible_vram_if_possible(fd, 0));
xe_spin = xe_bo_map(fd, spin->handle, bo_size);
addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
@@ -298,8 +298,8 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
vm = xe_vm_create(fd, 0, 0);
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, hwe->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, hwe->gt_id));
spin = xe_bo_map(fd, bo, 0x1000);
xe_vm_bind_sync(fd, vm, bo, 0, addr, bo_size);
diff --git a/tests/intel/api_intel_allocator.c b/tests/intel/api_intel_allocator.c
index f3fcf8a34..158fd86a1 100644
--- a/tests/intel/api_intel_allocator.c
+++ b/tests/intel/api_intel_allocator.c
@@ -468,8 +468,8 @@ static void __simple_allocs(int fd)
size = (rand() % 4 + 1) * 0x1000;
if (is_xe)
- handles[i] = xe_bo_create_flags(fd, 0, size,
- system_memory(fd));
+ handles[i] = xe_bo_create(fd, 0, size,
+ system_memory(fd));
else
handles[i] = gem_create(fd, size);
diff --git a/tests/intel/kms_big_fb.c b/tests/intel/kms_big_fb.c
index 611e60896..91848d69e 100644
--- a/tests/intel/kms_big_fb.c
+++ b/tests/intel/kms_big_fb.c
@@ -785,10 +785,10 @@ test_size_overflow(data_t *data)
if (is_i915_device(data->drm_fd))
bo = gem_buffer_create_fb_obj(data->drm_fd, (1ULL << 32) - 4096);
else
- bo = xe_bo_create_flags(data->drm_fd, 0,
- ALIGN(((1ULL << 32) - 4096),
- xe_get_default_alignment(data->drm_fd)),
- vram_if_possible(data->drm_fd, 0));
+ bo = xe_bo_create(data->drm_fd, 0,
+ ALIGN(((1ULL << 32) - 4096),
+ xe_get_default_alignment(data->drm_fd)),
+ vram_if_possible(data->drm_fd, 0));
igt_require(bo);
ret = __kms_addfb(data->drm_fd, bo,
@@ -853,10 +853,10 @@ test_size_offset_overflow(data_t *data)
if (is_i915_device(data->drm_fd))
bo = gem_buffer_create_fb_obj(data->drm_fd, (1ULL << 32) - 4096);
else
- bo = xe_bo_create_flags(data->drm_fd, 0,
- ALIGN(((1ULL << 32) - 4096),
- xe_get_default_alignment(data->drm_fd)),
- vram_if_possible(data->drm_fd, 0));
+ bo = xe_bo_create(data->drm_fd, 0,
+ ALIGN(((1ULL << 32) - 4096),
+ xe_get_default_alignment(data->drm_fd)),
+ vram_if_possible(data->drm_fd, 0));
igt_require(bo);
offsets[0] = 0;
@@ -942,9 +942,9 @@ test_addfb(data_t *data)
if (is_i915_device(data->drm_fd))
bo = gem_buffer_create_fb_obj(data->drm_fd, size);
else
- bo = xe_bo_create_flags(data->drm_fd, 0,
- ALIGN(size, xe_get_default_alignment(data->drm_fd)),
- vram_if_possible(data->drm_fd, 0));
+ bo = xe_bo_create(data->drm_fd, 0,
+ ALIGN(size, xe_get_default_alignment(data->drm_fd)),
+ vram_if_possible(data->drm_fd, 0));
igt_require(bo);
if (is_i915_device(data->drm_fd) && intel_display_ver(data->devid) < 4)
diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c
index 1d5b286f3..1b36ceb1e 100644
--- a/tests/intel/xe_ccs.c
+++ b/tests/intel/xe_ccs.c
@@ -102,8 +102,8 @@ static void surf_copy(int xe,
igt_assert(mid->compression);
ccscopy = (uint32_t *) malloc(ccssize);
- ccs = xe_bo_create_flags(xe, 0, ccssize, sysmem);
- ccs2 = xe_bo_create_flags(xe, 0, ccssize, sysmem);
+ ccs = xe_bo_create(xe, 0, ccssize, sysmem);
+ ccs2 = xe_bo_create(xe, 0, ccssize, sysmem);
blt_ctrl_surf_copy_init(xe, &surf);
surf.print_bb = param.print_bb;
@@ -111,7 +111,7 @@ static void surf_copy(int xe,
uc_mocs, BLT_INDIRECT_ACCESS);
blt_set_ctrl_surf_object(&surf.dst, ccs, sysmem, ccssize, uc_mocs, DIRECT_ACCESS);
bb_size = xe_get_default_alignment(xe);
- bb1 = xe_bo_create_flags(xe, 0, bb_size, sysmem);
+ bb1 = xe_bo_create(xe, 0, bb_size, sysmem);
blt_set_batch(&surf.bb, bb1, bb_size, sysmem);
blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
intel_ctx_xe_sync(ctx, true);
@@ -166,7 +166,7 @@ static void surf_copy(int xe,
blt_set_copy_object(&blt.dst, dst);
blt_set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D);
blt_set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D);
- bb2 = xe_bo_create_flags(xe, 0, bb_size, sysmem);
+ bb2 = xe_bo_create(xe, 0, bb_size, sysmem);
blt_set_batch(&blt.bb, bb2, bb_size, sysmem);
blt_block_copy(xe, ctx, NULL, ahnd, &blt, &ext);
intel_ctx_xe_sync(ctx, true);
@@ -297,7 +297,7 @@ static void block_copy(int xe,
uint8_t uc_mocs = intel_get_uc_mocs(xe);
int result;
- bb = xe_bo_create_flags(xe, 0, bb_size, region1);
+ bb = xe_bo_create(xe, 0, bb_size, region1);
if (!blt_uses_extended_block_copy(xe))
pext = NULL;
@@ -418,7 +418,7 @@ static void block_multicopy(int xe,
uint8_t uc_mocs = intel_get_uc_mocs(xe);
int result;
- bb = xe_bo_create_flags(xe, 0, bb_size, region1);
+ bb = xe_bo_create(xe, 0, bb_size, region1);
if (!blt_uses_extended_block_copy(xe))
pext3 = NULL;
diff --git a/tests/intel/xe_dma_buf_sync.c b/tests/intel/xe_dma_buf_sync.c
index 0d835dddb..ac9d9d767 100644
--- a/tests/intel/xe_dma_buf_sync.c
+++ b/tests/intel/xe_dma_buf_sync.c
@@ -119,8 +119,8 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd[0]),
xe_get_default_alignment(fd[0]));
for (i = 0; i < n_bo; ++i) {
- bo[i] = xe_bo_create_flags(fd[0], 0, bo_size,
- visible_vram_if_possible(fd[0], hwe0->gt_id));
+ bo[i] = xe_bo_create(fd[0], 0, bo_size,
+ visible_vram_if_possible(fd[0], hwe0->gt_id));
dma_buf_fd[i] = prime_handle_to_fd(fd[0], bo[i]);
import_bo[i] = prime_fd_to_handle(fd[1], dma_buf_fd[i]);
diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 4ef30cf49..8f737a533 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -85,7 +85,7 @@ static void test_active(int fd, struct drm_xe_engine_class_instance *eci)
igt_assert_f(ret != 0, "failed with err:%d\n", errno);
pre_size = info.region_mem[memregion->instance + 1].active;
- bo = xe_bo_create_flags(fd, vm, bo_size, region);
+ bo = xe_bo_create(fd, vm, bo_size, region);
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < N_EXEC_QUEUES; i++) {
@@ -185,7 +185,7 @@ static void test_shared(int xe)
igt_assert_f(ret != 0, "failed with err:%d\n", errno);
pre_size = info.region_mem[memregion->instance + 1].shared;
- bo = xe_bo_create_flags(xe, 0, BO_SIZE, region);
+ bo = xe_bo_create(xe, 0, BO_SIZE, region);
flink.handle = bo;
ret = igt_ioctl(xe, DRM_IOCTL_GEM_FLINK, &flink);
@@ -232,7 +232,7 @@ static void test_total_resident(int xe)
igt_assert_f(ret != 0, "failed with err:%d\n", errno);
pre_size = info.region_mem[memregion->instance + 1].shared;
- handle = xe_bo_create_flags(xe, vm, BO_SIZE, region);
+ handle = xe_bo_create(xe, vm, BO_SIZE, region);
xe_vm_bind_sync(xe, vm, handle, 0, addr, BO_SIZE);
ret = igt_parse_drm_fdinfo(xe, &info, NULL, 0, NULL, 0);
diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c
index 53aa402a3..ec25f9eff 100644
--- a/tests/intel/xe_evict.c
+++ b/tests/intel/xe_evict.c
@@ -99,18 +99,18 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
i < n_execs / 8 ? 0 : vm;
if (flags & MULTI_VM) {
- __bo = bo[i] = xe_bo_create_flags(fd, 0,
- bo_size,
- visible_vram_memory(fd, eci->gt_id));
+ __bo = bo[i] = xe_bo_create(fd, 0,
+ bo_size,
+ visible_vram_memory(fd, eci->gt_id));
} else if (flags & THREADED) {
- __bo = bo[i] = xe_bo_create_flags(fd, vm,
- bo_size,
- visible_vram_memory(fd, eci->gt_id));
+ __bo = bo[i] = xe_bo_create(fd, vm,
+ bo_size,
+ visible_vram_memory(fd, eci->gt_id));
} else {
- __bo = bo[i] = xe_bo_create_flags(fd, _vm,
- bo_size,
- visible_vram_memory(fd, eci->gt_id) |
- system_memory(fd));
+ __bo = bo[i] = xe_bo_create(fd, _vm,
+ bo_size,
+ visible_vram_memory(fd, eci->gt_id) |
+ system_memory(fd));
}
} else {
__bo = bo[i % (n_execs / 2)];
@@ -275,18 +275,18 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
i < n_execs / 8 ? 0 : vm;
if (flags & MULTI_VM) {
- __bo = bo[i] = xe_bo_create_flags(fd, 0,
- bo_size,
- visible_vram_memory(fd, eci->gt_id));
+ __bo = bo[i] = xe_bo_create(fd, 0,
+ bo_size,
+ visible_vram_memory(fd, eci->gt_id));
} else if (flags & THREADED) {
- __bo = bo[i] = xe_bo_create_flags(fd, vm,
- bo_size,
- visible_vram_memory(fd, eci->gt_id));
+ __bo = bo[i] = xe_bo_create(fd, vm,
+ bo_size,
+ visible_vram_memory(fd, eci->gt_id));
} else {
- __bo = bo[i] = xe_bo_create_flags(fd, _vm,
- bo_size,
- visible_vram_memory(fd, eci->gt_id) |
- system_memory(fd));
+ __bo = bo[i] = xe_bo_create(fd, _vm,
+ bo_size,
+ visible_vram_memory(fd, eci->gt_id) |
+ system_memory(fd));
}
} else {
__bo = bo[i % (n_execs / 2)];
diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c
index 8a0165b8c..da34e117d 100644
--- a/tests/intel/xe_exec_balancer.c
+++ b/tests/intel/xe_exec_balancer.c
@@ -70,7 +70,7 @@ static void test_all_active(int fd, int gt, int class)
bo_size = sizeof(*data) * num_placements;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
- bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
+ bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < num_placements; i++) {
@@ -224,7 +224,7 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs,
}
memset(data, 0, bo_size);
} else {
- bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
+ bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
data = xe_bo_map(fd, bo, bo_size);
}
@@ -452,7 +452,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs,
igt_assert(data);
}
} else {
- bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
+ bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c
index a401f0165..841696b68 100644
--- a/tests/intel/xe_exec_basic.c
+++ b/tests/intel/xe_exec_basic.c
@@ -140,8 +140,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
if (flags & DEFER_ALLOC)
bo_flags |= DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING;
- bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
- bo_size, bo_flags);
+ bo = xe_bo_create(fd, n_vm == 1 ? vm[0] : 0, bo_size, bo_flags);
if (!(flags & DEFER_BIND))
data = xe_bo_map(fd, bo, bo_size);
}
diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c
index 20d3fc6e8..beb962f79 100644
--- a/tests/intel/xe_exec_compute_mode.c
+++ b/tests/intel/xe_exec_compute_mode.c
@@ -141,8 +141,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(data);
}
} else {
- bo = xe_bo_create_flags(fd, flags & VM_FOR_BO ? vm : 0,
- bo_size, visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, flags & VM_FOR_BO ? vm : 0,
+ bo_size, visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c
index 92d552f97..903ad430d 100644
--- a/tests/intel/xe_exec_fault_mode.c
+++ b/tests/intel/xe_exec_fault_mode.c
@@ -151,12 +151,12 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
}
} else {
if (flags & PREFETCH)
- bo = xe_bo_create_flags(fd, 0, bo_size,
- all_memory_regions(fd) |
- visible_vram_if_possible(fd, 0));
+ bo = xe_bo_create(fd, 0, bo_size,
+ all_memory_regions(fd) |
+ visible_vram_if_possible(fd, 0));
else
- bo = xe_bo_create_flags(fd, 0, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, 0, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
index 195e62911..704690e83 100644
--- a/tests/intel/xe_exec_reset.c
+++ b/tests/intel/xe_exec_reset.c
@@ -50,8 +50,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
spin = xe_bo_map(fd, bo, bo_size);
exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
@@ -181,7 +181,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
+ bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < n_exec_queues; i++) {
@@ -367,8 +367,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < n_exec_queues; i++) {
@@ -534,8 +534,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
memset(data, 0, bo_size);
@@ -661,7 +661,7 @@ static void submit_jobs(struct gt_thread_data *t)
uint32_t bo;
uint32_t *data;
- bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
+ bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
data = xe_bo_map(fd, bo, bo_size);
data[0] = MI_BATCH_BUFFER_END;
diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
index 46caa2e0c..db685178f 100644
--- a/tests/intel/xe_exec_store.c
+++ b/tests/intel/xe_exec_store.c
@@ -81,8 +81,8 @@ static void store(int fd)
xe_get_default_alignment(fd));
hw_engine = xe_hw_engine(fd, 1);
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, hw_engine->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, hw_engine->gt_id));
xe_vm_bind_async(fd, vm, hw_engine->gt_id, bo, 0, addr, bo_size, &sync, 1);
data = xe_bo_map(fd, bo, bo_size);
@@ -137,8 +137,8 @@ static void store_all(int fd, int gt, int class)
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, 0));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, 0));
data = xe_bo_map(fd, bo, bo_size);
xe_for_each_hw_engine(fd, hwe) {
diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c
index 1c2b66f55..6ee580c18 100644
--- a/tests/intel/xe_exec_threads.c
+++ b/tests/intel/xe_exec_threads.c
@@ -106,8 +106,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
igt_assert(data);
}
} else {
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, gt));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, gt));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
@@ -307,8 +307,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
igt_assert(data);
}
} else {
- bo = xe_bo_create_flags(fd, 0, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, 0, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
@@ -510,8 +510,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
igt_assert(data);
}
} else {
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
diff --git a/tests/intel/xe_exercise_blt.c b/tests/intel/xe_exercise_blt.c
index fd310138d..9c69be3ef 100644
--- a/tests/intel/xe_exercise_blt.c
+++ b/tests/intel/xe_exercise_blt.c
@@ -125,7 +125,7 @@ static void fast_copy_emit(int xe, const intel_ctx_t *ctx,
uint32_t bb, width = param.width, height = param.height;
int result;
- bb = xe_bo_create_flags(xe, 0, bb_size, region1);
+ bb = xe_bo_create(xe, 0, bb_size, region1);
blt_copy_init(xe, &bltinit);
src = blt_create_object(&bltinit, region1, width, height, bpp, 0,
@@ -184,7 +184,7 @@ static void fast_copy(int xe, const intel_ctx_t *ctx,
uint32_t width = param.width, height = param.height;
int result;
- bb = xe_bo_create_flags(xe, 0, bb_size, region1);
+ bb = xe_bo_create(xe, 0, bb_size, region1);
blt_copy_init(xe, &blt);
src = blt_create_object(&blt, region1, width, height, bpp, 0,
diff --git a/tests/intel/xe_guc_pc.c b/tests/intel/xe_guc_pc.c
index fa2f20cca..1e29d8905 100644
--- a/tests/intel/xe_guc_pc.c
+++ b/tests/intel/xe_guc_pc.c
@@ -65,8 +65,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < n_exec_queues; i++) {
diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c
index d66996cd5..a3a315297 100644
--- a/tests/intel/xe_intel_bb.c
+++ b/tests/intel/xe_intel_bb.c
@@ -396,7 +396,7 @@ static void create_in_region(struct buf_ops *bops, uint64_t region)
intel_bb_set_debug(ibb, true);
size = xe_min_page_size(xe, system_memory(xe));
- handle = xe_bo_create_flags(xe, 0, size, system_memory(xe));
+ handle = xe_bo_create(xe, 0, size, system_memory(xe));
intel_buf_init_full(bops, handle, &buf,
width/4, height, 32, 0,
I915_TILING_NONE, 0,
diff --git a/tests/intel/xe_mmap.c b/tests/intel/xe_mmap.c
index 7e7e43c00..a805eabda 100644
--- a/tests/intel/xe_mmap.c
+++ b/tests/intel/xe_mmap.c
@@ -52,7 +52,7 @@ test_mmap(int fd, uint32_t flags)
igt_require_f(flags, "Device doesn't support such memory region\n");
- bo = xe_bo_create_flags(fd, 0, 4096, flags);
+ bo = xe_bo_create(fd, 0, 4096, flags);
map = xe_bo_map(fd, bo, 4096);
strcpy(map, "Write some data to the BO!");
@@ -72,8 +72,8 @@ static void test_bad_flags(int fd)
{
uint64_t size = xe_get_default_alignment(fd);
struct drm_xe_gem_mmap_offset mmo = {
- .handle = xe_bo_create_flags(fd, 0, size,
- visible_vram_if_possible(fd, 0)),
+ .handle = xe_bo_create(fd, 0, size,
+ visible_vram_if_possible(fd, 0)),
.flags = -1u,
};
@@ -92,8 +92,8 @@ static void test_bad_extensions(int fd)
uint64_t size = xe_get_default_alignment(fd);
struct xe_user_extension ext;
struct drm_xe_gem_mmap_offset mmo = {
- .handle = xe_bo_create_flags(fd, 0, size,
- visible_vram_if_possible(fd, 0)),
+ .handle = xe_bo_create(fd, 0, size,
+ visible_vram_if_possible(fd, 0)),
};
mmo.extensions = to_user_pointer(&ext);
@@ -113,8 +113,8 @@ static void test_bad_object(int fd)
{
uint64_t size = xe_get_default_alignment(fd);
struct drm_xe_gem_mmap_offset mmo = {
- .handle = xe_bo_create_flags(fd, 0, size,
- visible_vram_if_possible(fd, 0)),
+ .handle = xe_bo_create(fd, 0, size,
+ visible_vram_if_possible(fd, 0)),
};
mmo.handle = 0xdeadbeef;
@@ -159,13 +159,13 @@ static void test_small_bar(int fd)
uint32_t *map;
/* 2BIG invalid case */
- igt_assert_neq(__xe_bo_create_flags(fd, 0, visible_size + 4096,
- visible_vram_memory(fd, 0), &bo),
+ igt_assert_neq(__xe_bo_create(fd, 0, visible_size + 4096,
+ visible_vram_memory(fd, 0), &bo),
0);
/* Normal operation */
- bo = xe_bo_create_flags(fd, 0, visible_size / 4,
- visible_vram_memory(fd, 0));
+ bo = xe_bo_create(fd, 0, visible_size / 4,
+ visible_vram_memory(fd, 0));
mmo = xe_bo_mmap_offset(fd, bo);
map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
igt_assert(map != MAP_FAILED);
@@ -176,9 +176,9 @@ static void test_small_bar(int fd)
gem_close(fd, bo);
/* Normal operation with system memory spilling */
- bo = xe_bo_create_flags(fd, 0, visible_size,
- visible_vram_memory(fd, 0) |
- system_memory(fd));
+ bo = xe_bo_create(fd, 0, visible_size,
+ visible_vram_memory(fd, 0) |
+ system_memory(fd));
mmo = xe_bo_mmap_offset(fd, bo);
map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
igt_assert(map != MAP_FAILED);
@@ -189,8 +189,8 @@ static void test_small_bar(int fd)
gem_close(fd, bo);
/* Bogus operation with SIGBUS */
- bo = xe_bo_create_flags(fd, 0, visible_size + 4096,
- vram_memory(fd, 0));
+ bo = xe_bo_create(fd, 0, visible_size + 4096,
+ vram_memory(fd, 0));
mmo = xe_bo_mmap_offset(fd, bo);
map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
igt_assert(map != MAP_FAILED);
diff --git a/tests/intel/xe_noexec_ping_pong.c b/tests/intel/xe_noexec_ping_pong.c
index 9c2a70ff3..88ef39783 100644
--- a/tests/intel/xe_noexec_ping_pong.c
+++ b/tests/intel/xe_noexec_ping_pong.c
@@ -70,8 +70,8 @@ static void test_ping_pong(int fd, struct drm_xe_engine_class_instance *eci)
(unsigned long) bo_size,
(unsigned int) vm[i]);
- bo[i][j] = xe_bo_create_flags(fd, vm[i], bo_size,
- vram_memory(fd, 0));
+ bo[i][j] = xe_bo_create(fd, vm[i], bo_size,
+ vram_memory(fd, 0));
xe_vm_bind(fd, vm[i], bo[i][j], 0, 0x40000 + j*bo_size,
bo_size, NULL, 0);
}
diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c
index 18afb68b0..d72e921cf 100644
--- a/tests/intel/xe_pm.c
+++ b/tests/intel/xe_pm.c
@@ -271,8 +271,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
if (check_rpm && runtime_usage_available(device.pci_xe))
rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
- bo = xe_bo_create_flags(device.fd_xe, vm, bo_size,
- visible_vram_if_possible(device.fd_xe, eci->gt_id));
+ bo = xe_bo_create(device.fd_xe, vm, bo_size,
+ visible_vram_if_possible(device.fd_xe, eci->gt_id));
data = xe_bo_map(device.fd_xe, bo, bo_size);
for (i = 0; i < n_exec_queues; i++) {
@@ -409,7 +409,7 @@ static void test_vram_d3cold_threshold(device_t device, int sysfs_fd)
threshold = vram_used_mb + (SIZE / 1024 /1024);
igt_require(threshold < vram_total_mb);
- bo = xe_bo_create_flags(device.fd_xe, 0, SIZE, flags);
+ bo = xe_bo_create(device.fd_xe, 0, SIZE, flags);
map = xe_bo_map(device.fd_xe, bo, SIZE);
memset(map, 0, SIZE);
munmap(map, SIZE);
diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c
index c87eeef3c..cc133f5fb 100644
--- a/tests/intel/xe_pm_residency.c
+++ b/tests/intel/xe_pm_residency.c
@@ -100,8 +100,8 @@ static void exec_load(int fd, struct drm_xe_engine_class_instance *hwe, unsigned
exec_queue = xe_exec_queue_create(fd, vm, hwe, 0);
bo_size = xe_get_default_alignment(fd);
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, hwe->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, hwe->gt_id));
data = xe_bo_map(fd, bo, bo_size);
syncobj = syncobj_create(fd, 0);
diff --git a/tests/intel/xe_prime_self_import.c b/tests/intel/xe_prime_self_import.c
index 994fd99f5..bcecd2fcd 100644
--- a/tests/intel/xe_prime_self_import.c
+++ b/tests/intel/xe_prime_self_import.c
@@ -106,7 +106,7 @@ static void test_with_fd_dup(void)
fd1 = drm_open_driver(DRIVER_XE);
fd2 = drm_open_driver(DRIVER_XE);
- handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
+ handle = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
gem_close(fd1, handle);
@@ -139,8 +139,8 @@ static void test_with_two_bos(void)
fd1 = drm_open_driver(DRIVER_XE);
fd2 = drm_open_driver(DRIVER_XE);
- handle1 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
- handle2 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
+ handle1 = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
+ handle2 = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
dma_buf_fd = prime_handle_to_fd(fd1, handle1);
handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
@@ -175,8 +175,8 @@ static void test_with_one_bo_two_files(void)
fd1 = drm_open_driver(DRIVER_XE);
fd2 = drm_open_driver(DRIVER_XE);
- handle_orig = xe_bo_create_flags(fd1, 0, BO_SIZE,
- visible_vram_if_possible(fd1, 0));
+ handle_orig = xe_bo_create(fd1, 0, BO_SIZE,
+ visible_vram_if_possible(fd1, 0));
dma_buf_fd1 = prime_handle_to_fd(fd1, handle_orig);
flink_name = gem_flink(fd1, handle_orig);
@@ -208,7 +208,7 @@ static void test_with_one_bo(void)
fd1 = drm_open_driver(DRIVER_XE);
fd2 = drm_open_driver(DRIVER_XE);
- handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
+ handle = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
dma_buf_fd = prime_handle_to_fd(fd1, handle);
handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
@@ -294,8 +294,8 @@ static void *thread_fn_reimport_vs_close(void *p)
fds[0] = drm_open_driver(DRIVER_XE);
- handle = xe_bo_create_flags(fds[0], 0, BO_SIZE,
- visible_vram_if_possible(fds[0], 0));
+ handle = xe_bo_create(fds[0], 0, BO_SIZE,
+ visible_vram_if_possible(fds[0], 0));
fds[1] = prime_handle_to_fd(fds[0], handle);
pthread_barrier_init(&g_barrier, NULL, num_threads);
@@ -337,8 +337,8 @@ static void *thread_fn_export_vs_close(void *p)
igt_until_timeout(g_time_out) {
/* We want to race gem close against prime export on handle one.*/
- handle = xe_bo_create_flags(fd, 0, 4096,
- visible_vram_if_possible(fd, 0));
+ handle = xe_bo_create(fd, 0, 4096,
+ visible_vram_if_possible(fd, 0));
if (handle != 1)
gem_close(fd, handle);
@@ -434,8 +434,8 @@ static void test_llseek_size(void)
for (i = 0; i < 10; i++) {
int bufsz = xe_get_default_alignment(fd) << i;
- handle = xe_bo_create_flags(fd, 0, bufsz,
- visible_vram_if_possible(fd, 0));
+ handle = xe_bo_create(fd, 0, bufsz,
+ visible_vram_if_possible(fd, 0));
dma_buf_fd = prime_handle_to_fd(fd, handle);
gem_close(fd, handle);
@@ -463,8 +463,8 @@ static void test_llseek_bad(void)
fd = drm_open_driver(DRIVER_XE);
- handle = xe_bo_create_flags(fd, 0, BO_SIZE,
- visible_vram_if_possible(fd, 0));
+ handle = xe_bo_create(fd, 0, BO_SIZE,
+ visible_vram_if_possible(fd, 0));
dma_buf_fd = prime_handle_to_fd(fd, handle);
gem_close(fd, handle);
diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index 261fde9af..c1b161f9c 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -169,7 +169,7 @@ static void xe_spin_fixed_duration(int fd)
exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY);
ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
bo_size = ALIGN(sizeof(*spin) + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
- bo = xe_bo_create_flags(fd, vm, bo_size, vram_if_possible(fd, 0));
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0));
spin = xe_bo_map(fd, bo, bo_size);
spin_addr = intel_allocator_alloc_with_strategy(ahnd, bo, bo_size, 0,
ALLOC_STRATEGY_LOW_TO_HIGH);
diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
index 27d44af7f..1f71182fe 100644
--- a/tests/intel/xe_vm.c
+++ b/tests/intel/xe_vm.c
@@ -51,8 +51,8 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
batch_size = (n_dwords * 4 + 1) * sizeof(uint32_t);
batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- batch_bo = xe_bo_create_flags(fd, vm, batch_size,
- visible_vram_if_possible(fd, 0));
+ batch_bo = xe_bo_create(fd, vm, batch_size,
+ visible_vram_if_possible(fd, 0));
batch_map = xe_bo_map(fd, batch_bo, batch_size);
for (i = 0; i < n_dwords; i++) {
@@ -116,7 +116,7 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
vms = malloc(sizeof(*vms) * n_addrs);
igt_assert(vms);
}
- bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
+ bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
map = xe_bo_map(fd, bo, bo_size);
memset(map, 0, bo_size);
@@ -276,7 +276,7 @@ static void unbind_all(int fd, int n_vmas)
};
vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
- bo = xe_bo_create_flags(fd, vm, bo_size, vram_if_possible(fd, 0));
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0));
for (i = 0; i < n_vmas; ++i)
xe_vm_bind_async(fd, vm, 0, bo, 0, addr + i * bo_size,
@@ -322,7 +322,6 @@ static void userptr_invalid(int fd)
xe_vm_destroy(fd, vm);
}
-
/**
* SUBTEST: shared-%s-page
* Description: Test shared arg[1] page
@@ -379,8 +378,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
xe_get_default_alignment(fd));
for (i = 0; i < n_bo; ++i) {
- bo[i] = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo[i] = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data[i] = xe_bo_map(fd, bo[i], bo_size);
}
@@ -558,8 +557,8 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec
bo_size = sizeof(*data) * N_EXEC_QUEUES;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < N_EXEC_QUEUES; i++) {
@@ -739,8 +738,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
if (flags & BIND_ARRAY_BIND_EXEC_QUEUE_FLAG)
@@ -937,8 +936,8 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
igt_skip_on(xe_visible_vram_size(fd, 0) && bo_size >
xe_visible_vram_size(fd, 0));
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
map = xe_bo_map(fd, bo, bo_size);
}
@@ -1229,8 +1228,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
MAP_ANONYMOUS, -1, 0);
igt_assert(map != MAP_FAILED);
} else {
- bo = xe_bo_create_flags(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
map = xe_bo_map(fd, bo, bo_size);
}
memset(map, 0, bo_size);
@@ -1533,9 +1532,9 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(map0 != MAP_FAILED);
igt_assert(map1 != MAP_FAILED);
} else {
- bo0 = xe_bo_create_flags(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id));
+ bo0 = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id));
map0 = xe_bo_map(fd, bo0, bo_size);
- bo1 = xe_bo_create_flags(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id));
+ bo1 = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id));
map1 = xe_bo_map(fd, bo1, bo_size);
}
memset(map0, 0, bo_size);
diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c
index 05060f329..913afcdb5 100644
--- a/tests/intel/xe_waitfence.c
+++ b/tests/intel/xe_waitfence.c
@@ -64,19 +64,19 @@ waitfence(int fd, enum waittype wt)
int64_t timeout;
uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
- bo_1 = xe_bo_create_flags(fd, vm, 0x40000, MY_FLAG);
+ bo_1 = xe_bo_create(fd, vm, 0x40000, MY_FLAG);
do_bind(fd, vm, bo_1, 0, 0x200000, 0x40000, 1);
- bo_2 = xe_bo_create_flags(fd, vm, 0x40000, MY_FLAG);
+ bo_2 = xe_bo_create(fd, vm, 0x40000, MY_FLAG);
do_bind(fd, vm, bo_2, 0, 0xc0000000, 0x40000, 2);
- bo_3 = xe_bo_create_flags(fd, vm, 0x40000, MY_FLAG);
+ bo_3 = xe_bo_create(fd, vm, 0x40000, MY_FLAG);
do_bind(fd, vm, bo_3, 0, 0x180000000, 0x40000, 3);
- bo_4 = xe_bo_create_flags(fd, vm, 0x10000, MY_FLAG);
+ bo_4 = xe_bo_create(fd, vm, 0x10000, MY_FLAG);
do_bind(fd, vm, bo_4, 0, 0x140000000, 0x10000, 4);
- bo_5 = xe_bo_create_flags(fd, vm, 0x100000, MY_FLAG);
+ bo_5 = xe_bo_create(fd, vm, 0x100000, MY_FLAG);
do_bind(fd, vm, bo_5, 0, 0x100000000, 0x100000, 5);
- bo_6 = xe_bo_create_flags(fd, vm, 0x1c0000, MY_FLAG);
+ bo_6 = xe_bo_create(fd, vm, 0x1c0000, MY_FLAG);
do_bind(fd, vm, bo_6, 0, 0xc0040000, 0x1c0000, 6);
- bo_7 = xe_bo_create_flags(fd, vm, 0x10000, MY_FLAG);
+ bo_7 = xe_bo_create(fd, vm, 0x10000, MY_FLAG);
do_bind(fd, vm, bo_7, 0, 0xeffff0000, 0x10000, 7);
if (wt == RELTIME) {
diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index fc16b8814..4f293c2ee 100644
--- a/tests/kms_addfb_basic.c
+++ b/tests/kms_addfb_basic.c
@@ -199,7 +199,7 @@ static void invalid_tests(int fd)
handle = gem_create_in_memory_regions(fd, size, REGION_SMEM);
} else {
igt_require(xe_has_vram(fd));
- handle = xe_bo_create_flags(fd, 0, size, system_memory(fd));
+ handle = xe_bo_create(fd, 0, size, system_memory(fd));
}
f.handles[0] = handle;
diff --git a/tests/kms_getfb.c b/tests/kms_getfb.c
index 059f66d99..1f9e813d8 100644
--- a/tests/kms_getfb.c
+++ b/tests/kms_getfb.c
@@ -149,7 +149,7 @@ static void get_ccs_fb(int fd, struct drm_mode_fb_cmd2 *ret)
if (is_i915_device(fd))
add.handles[0] = gem_buffer_create_fb_obj(fd, size);
else
- add.handles[0] = xe_bo_create_flags(fd, 0, size, vram_if_possible(fd, 0));
+ add.handles[0] = xe_bo_create(fd, 0, size, vram_if_possible(fd, 0));
igt_require(add.handles[0] != 0);
if (!HAS_FLATCCS(devid))
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 16/20] xe_query: Add missing include.
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (14 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 15/20] xe_ioctl: Rename *xe_bo_create_flags to simply xe_bo_create Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-12 18:44 ` Kamil Konieczny
2023-10-11 14:18 ` [igt-dev] [RFC v1 17/20] xe_query: Kill visible_vram_if_possible Francois Dugast
` (4 subsequent siblings)
20 siblings, 1 reply; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
When trying to use xe_for_each_mem_region from a caller
that is not importing the igt_aux.h, the following build issue
will occur:
../lib/xe/xe_query.h:76:38: error: implicit declaration of function ‘igt_fls’ [-Werror=implicit-function-declaration]
76 | for (uint64_t __i = 0; __i < igt_fls(__memreg); __i++) \
So, to avoid a dependency chain, let's include from the file
that is using the helper.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
lib/xe/xe_query.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index 8557bb4c5..dcdfa52c2 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -11,6 +11,8 @@
#include <stdint.h>
#include <xe_drm.h>
+
+#include "igt_aux.h"
#include "igt_list.h"
#define SZ_4K 0x1000
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 17/20] xe_query: Kill visible_vram_if_possible
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (15 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 16/20] xe_query: Add missing include Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-12 18:46 ` Kamil Konieczny
2023-10-11 14:18 ` [igt-dev] [RFC v1 18/20] drm-uapi/xe: Separate bo_create placement from flags Francois Dugast
` (3 subsequent siblings)
20 siblings, 1 reply; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Let the caller set the flag and the xe_bo_query clear if
not needed.
Although the current helper makes the code cleaner, the
goal is to split the flags into placement and flags as two
different arguments on xe_bo_create. So, the flag decision
cannot be hidden under the helper.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
lib/igt_draw.c | 3 ++-
lib/igt_fb.c | 3 ++-
lib/intel_batchbuffer.c | 6 ++++--
lib/xe/xe_ioctl.c | 19 +++++++++++++++++++
lib/xe/xe_query.c | 19 -------------------
lib/xe/xe_query.h | 1 -
lib/xe/xe_spin.c | 7 ++++---
tests/intel/xe_dma_buf_sync.c | 3 ++-
tests/intel/xe_exec_balancer.c | 9 ++++++---
tests/intel/xe_exec_basic.c | 2 +-
tests/intel/xe_exec_compute_mode.c | 3 ++-
tests/intel/xe_exec_fault_mode.c | 6 ++++--
tests/intel/xe_exec_reset.c | 14 +++++++++-----
tests/intel/xe_exec_store.c | 6 ++++--
tests/intel/xe_exec_threads.c | 9 ++++++---
tests/intel/xe_guc_pc.c | 3 ++-
tests/intel/xe_mmap.c | 9 ++++++---
tests/intel/xe_pm.c | 3 ++-
tests/intel/xe_pm_residency.c | 3 ++-
tests/intel/xe_prime_self_import.c | 27 ++++++++++++++++++---------
tests/intel/xe_vm.c | 21 ++++++++++++++-------
21 files changed, 109 insertions(+), 67 deletions(-)
diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index e37c64fd5..d02125c47 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -791,7 +791,8 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,
else
tmp.handle = xe_bo_create(fd, 0,
ALIGN(tmp.size, xe_get_default_alignment(fd)),
- visible_vram_if_possible(fd, 0));
+ vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
tmp.stride = rect->w * pixel_size;
tmp.bpp = buf->bpp;
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 39f623585..66f4ccdc4 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -1206,7 +1206,8 @@ static int create_bo_for_fb(struct igt_fb *fb, bool prefer_sysmem)
igt_assert(err == 0 || err == -EOPNOTSUPP);
} else if (is_xe_device(fd)) {
fb->gem_handle = xe_bo_create(fd, 0, fb->size,
- visible_vram_if_possible(fd, 0));
+ vram_if_possible(fd, 0)
+ | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
} else if (is_vc4_device(fd)) {
fb->gem_handle = igt_vc4_create_bo(fd, fb->size);
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 4ca371956..05dd6e35c 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -945,7 +945,8 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
ibb->alignment = xe_get_default_alignment(fd);
size = ALIGN(size, ibb->alignment);
- ibb->handle = xe_bo_create(fd, 0, size, visible_vram_if_possible(fd, 0));
+ ibb->handle = xe_bo_create(fd, 0, size, vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
/* Limit to 48-bit due to MI_* address limitation */
ibb->gtt_size = 1ull << min_t(uint32_t, xe_va_bits(fd), 48);
@@ -1404,7 +1405,8 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
ibb->handle = gem_create(ibb->fd, ibb->size);
else
ibb->handle = xe_bo_create(ibb->fd, 0, ibb->size,
- visible_vram_if_possible(ibb->fd, 0));
+ vram_if_possible(ibb->fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
/* Reacquire offset for RELOC and SIMPLE */
if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE ||
diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index aafd77966..4e21e4c84 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -226,6 +226,18 @@ void xe_vm_destroy(int fd, uint32_t vm)
igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_DESTROY, &destroy), 0);
}
+static bool vram_selected(int fd, uint32_t selected_regions)
+{
+ uint64_t regions = all_memory_regions(fd) & selected_regions;
+ uint64_t region;
+
+ xe_for_each_mem_region(fd, regions, region)
+ if (xe_mem_region(fd, region)->mem_class == DRM_XE_MEM_REGION_CLASS_VRAM)
+ return true;
+
+ return false;
+}
+
uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags,
uint32_t *handle)
{
@@ -236,6 +248,13 @@ uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags,
};
int err;
+ /*
+ * In case vram_if_possible returned system_memory,
+ * visible VRAM cannot be requested through flags
+ */
+ if (!vram_selected(fd, flags))
+ create.flags &= ~DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
+
err = igt_ioctl(fd, DRM_IOCTL_XE_GEM_CREATE, &create);
if (err)
return err;
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 87841e8a3..4329a7e80 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -424,25 +424,6 @@ uint64_t vram_if_possible(int fd, int gt)
return vram_memory(fd, gt) ?: system_memory(fd);
}
-/**
- * visible_vram_if_possible:
- * @fd: xe device fd
- * @gt: gt id
- *
- * Returns vram memory bitmask for xe device @fd and @gt id or system memory if
- * there's no vram memory available for @gt. Also attaches the
- * DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
- * when using vram.
- */
-uint64_t visible_vram_if_possible(int fd, int gt)
-{
- uint64_t regions = all_memory_regions(fd);
- uint64_t system_memory = regions & 0x1;
- uint64_t vram = regions & (0x2 << gt);
-
- return vram ? vram | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
-}
-
/**
* xe_hw_engines:
* @fd: xe device fd
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index dcdfa52c2..60eddb126 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -87,7 +87,6 @@ uint64_t system_memory(int fd);
uint64_t vram_memory(int fd, int gt);
uint64_t visible_vram_memory(int fd, int gt);
uint64_t vram_if_possible(int fd, int gt);
-uint64_t visible_vram_if_possible(int fd, int gt);
struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region);
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 828938434..270b58bf5 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -220,7 +220,8 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt)
}
spin->handle = xe_bo_create(fd, spin->vm, bo_size,
- visible_vram_if_possible(fd, 0));
+ vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
xe_spin = xe_bo_map(fd, spin->handle, bo_size);
addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
@@ -298,8 +299,8 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
vm = xe_vm_create(fd, 0, 0);
- bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, hwe->gt_id));
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, hwe->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
spin = xe_bo_map(fd, bo, 0x1000);
xe_vm_bind_sync(fd, vm, bo, 0, addr, bo_size);
diff --git a/tests/intel/xe_dma_buf_sync.c b/tests/intel/xe_dma_buf_sync.c
index ac9d9d767..9318647af 100644
--- a/tests/intel/xe_dma_buf_sync.c
+++ b/tests/intel/xe_dma_buf_sync.c
@@ -120,7 +120,8 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
xe_get_default_alignment(fd[0]));
for (i = 0; i < n_bo; ++i) {
bo[i] = xe_bo_create(fd[0], 0, bo_size,
- visible_vram_if_possible(fd[0], hwe0->gt_id));
+ vram_if_possible(fd[0], hwe0->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd[i] = prime_handle_to_fd(fd[0], bo[i]);
import_bo[i] = prime_fd_to_handle(fd[1], dma_buf_fd[i]);
diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c
index da34e117d..388bb6185 100644
--- a/tests/intel/xe_exec_balancer.c
+++ b/tests/intel/xe_exec_balancer.c
@@ -70,7 +70,8 @@ static void test_all_active(int fd, int gt, int class)
bo_size = sizeof(*data) * num_placements;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < num_placements; i++) {
@@ -224,7 +225,8 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs,
}
memset(data, 0, bo_size);
} else {
- bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
@@ -452,7 +454,8 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs,
igt_assert(data);
}
} else {
- bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c
index 841696b68..ca287b2e5 100644
--- a/tests/intel/xe_exec_basic.c
+++ b/tests/intel/xe_exec_basic.c
@@ -136,7 +136,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
} else {
uint32_t bo_flags;
- bo_flags = visible_vram_if_possible(fd, eci->gt_id);
+ bo_flags = vram_if_possible(fd, eci->gt_id) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
if (flags & DEFER_ALLOC)
bo_flags |= DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING;
diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c
index beb962f79..07a27fd29 100644
--- a/tests/intel/xe_exec_compute_mode.c
+++ b/tests/intel/xe_exec_compute_mode.c
@@ -142,7 +142,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
}
} else {
bo = xe_bo_create(fd, flags & VM_FOR_BO ? vm : 0,
- bo_size, visible_vram_if_possible(fd, eci->gt_id));
+ bo_size, vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c
index 903ad430d..bfd61c4ea 100644
--- a/tests/intel/xe_exec_fault_mode.c
+++ b/tests/intel/xe_exec_fault_mode.c
@@ -153,10 +153,12 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
if (flags & PREFETCH)
bo = xe_bo_create(fd, 0, bo_size,
all_memory_regions(fd) |
- visible_vram_if_possible(fd, 0));
+ vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
else
bo = xe_bo_create(fd, 0, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
index 704690e83..3affb19ae 100644
--- a/tests/intel/xe_exec_reset.c
+++ b/tests/intel/xe_exec_reset.c
@@ -51,7 +51,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
spin = xe_bo_map(fd, bo, bo_size);
exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
@@ -181,7 +182,8 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < n_exec_queues; i++) {
@@ -368,7 +370,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < n_exec_queues; i++) {
@@ -535,7 +537,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
memset(data, 0, bo_size);
@@ -661,7 +664,8 @@ static void submit_jobs(struct gt_thread_data *t)
uint32_t bo;
uint32_t *data;
- bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
data[0] = MI_BATCH_BUFFER_END;
diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
index db685178f..f999a2bb4 100644
--- a/tests/intel/xe_exec_store.c
+++ b/tests/intel/xe_exec_store.c
@@ -82,7 +82,8 @@ static void store(int fd)
hw_engine = xe_hw_engine(fd, 1);
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, hw_engine->gt_id));
+ vram_if_possible(fd, hw_engine->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
xe_vm_bind_async(fd, vm, hw_engine->gt_id, bo, 0, addr, bo_size, &sync, 1);
data = xe_bo_map(fd, bo, bo_size);
@@ -138,7 +139,8 @@ static void store_all(int fd, int gt, int class)
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, 0));
+ vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
xe_for_each_hw_engine(fd, hwe) {
diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c
index 6ee580c18..d6505f522 100644
--- a/tests/intel/xe_exec_threads.c
+++ b/tests/intel/xe_exec_threads.c
@@ -107,7 +107,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
}
} else {
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, gt));
+ vram_if_possible(fd, gt) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
@@ -308,7 +309,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
}
} else {
bo = xe_bo_create(fd, 0, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
@@ -511,7 +513,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
}
} else {
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
diff --git a/tests/intel/xe_guc_pc.c b/tests/intel/xe_guc_pc.c
index 1e29d8905..4234475e0 100644
--- a/tests/intel/xe_guc_pc.c
+++ b/tests/intel/xe_guc_pc.c
@@ -66,7 +66,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < n_exec_queues; i++) {
diff --git a/tests/intel/xe_mmap.c b/tests/intel/xe_mmap.c
index a805eabda..a4b53ad48 100644
--- a/tests/intel/xe_mmap.c
+++ b/tests/intel/xe_mmap.c
@@ -73,7 +73,8 @@ static void test_bad_flags(int fd)
uint64_t size = xe_get_default_alignment(fd);
struct drm_xe_gem_mmap_offset mmo = {
.handle = xe_bo_create(fd, 0, size,
- visible_vram_if_possible(fd, 0)),
+ vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM),
.flags = -1u,
};
@@ -93,7 +94,8 @@ static void test_bad_extensions(int fd)
struct xe_user_extension ext;
struct drm_xe_gem_mmap_offset mmo = {
.handle = xe_bo_create(fd, 0, size,
- visible_vram_if_possible(fd, 0)),
+ vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM),
};
mmo.extensions = to_user_pointer(&ext);
@@ -114,7 +116,8 @@ static void test_bad_object(int fd)
uint64_t size = xe_get_default_alignment(fd);
struct drm_xe_gem_mmap_offset mmo = {
.handle = xe_bo_create(fd, 0, size,
- visible_vram_if_possible(fd, 0)),
+ vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM),
};
mmo.handle = 0xdeadbeef;
diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c
index d72e921cf..df85f2c05 100644
--- a/tests/intel/xe_pm.c
+++ b/tests/intel/xe_pm.c
@@ -272,7 +272,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
bo = xe_bo_create(device.fd_xe, vm, bo_size,
- visible_vram_if_possible(device.fd_xe, eci->gt_id));
+ vram_if_possible(device.fd_xe, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(device.fd_xe, bo, bo_size);
for (i = 0; i < n_exec_queues; i++) {
diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c
index cc133f5fb..40a1693b8 100644
--- a/tests/intel/xe_pm_residency.c
+++ b/tests/intel/xe_pm_residency.c
@@ -101,7 +101,8 @@ static void exec_load(int fd, struct drm_xe_engine_class_instance *hwe, unsigned
bo_size = xe_get_default_alignment(fd);
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, hwe->gt_id));
+ vram_if_possible(fd, hwe->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
syncobj = syncobj_create(fd, 0);
diff --git a/tests/intel/xe_prime_self_import.c b/tests/intel/xe_prime_self_import.c
index bcecd2fcd..df2d8635b 100644
--- a/tests/intel/xe_prime_self_import.c
+++ b/tests/intel/xe_prime_self_import.c
@@ -106,7 +106,8 @@ static void test_with_fd_dup(void)
fd1 = drm_open_driver(DRIVER_XE);
fd2 = drm_open_driver(DRIVER_XE);
- handle = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
+ handle = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
gem_close(fd1, handle);
@@ -139,8 +140,10 @@ static void test_with_two_bos(void)
fd1 = drm_open_driver(DRIVER_XE);
fd2 = drm_open_driver(DRIVER_XE);
- handle1 = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
- handle2 = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
+ handle1 = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+ handle2 = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd = prime_handle_to_fd(fd1, handle1);
handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
@@ -176,7 +179,8 @@ static void test_with_one_bo_two_files(void)
fd2 = drm_open_driver(DRIVER_XE);
handle_orig = xe_bo_create(fd1, 0, BO_SIZE,
- visible_vram_if_possible(fd1, 0));
+ vram_if_possible(fd1, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd1 = prime_handle_to_fd(fd1, handle_orig);
flink_name = gem_flink(fd1, handle_orig);
@@ -208,7 +212,8 @@ static void test_with_one_bo(void)
fd1 = drm_open_driver(DRIVER_XE);
fd2 = drm_open_driver(DRIVER_XE);
- handle = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
+ handle = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd = prime_handle_to_fd(fd1, handle);
handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
@@ -295,7 +300,8 @@ static void *thread_fn_reimport_vs_close(void *p)
fds[0] = drm_open_driver(DRIVER_XE);
handle = xe_bo_create(fds[0], 0, BO_SIZE,
- visible_vram_if_possible(fds[0], 0));
+ vram_if_possible(fds[0], 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
fds[1] = prime_handle_to_fd(fds[0], handle);
pthread_barrier_init(&g_barrier, NULL, num_threads);
@@ -338,7 +344,8 @@ static void *thread_fn_export_vs_close(void *p)
igt_until_timeout(g_time_out) {
/* We want to race gem close against prime export on handle one.*/
handle = xe_bo_create(fd, 0, 4096,
- visible_vram_if_possible(fd, 0));
+ vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
if (handle != 1)
gem_close(fd, handle);
@@ -435,7 +442,8 @@ static void test_llseek_size(void)
int bufsz = xe_get_default_alignment(fd) << i;
handle = xe_bo_create(fd, 0, bufsz,
- visible_vram_if_possible(fd, 0));
+ vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd = prime_handle_to_fd(fd, handle);
gem_close(fd, handle);
@@ -464,7 +472,8 @@ static void test_llseek_bad(void)
fd = drm_open_driver(DRIVER_XE);
handle = xe_bo_create(fd, 0, BO_SIZE,
- visible_vram_if_possible(fd, 0));
+ vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd = prime_handle_to_fd(fd, handle);
gem_close(fd, handle);
diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
index 1f71182fe..7e66786d4 100644
--- a/tests/intel/xe_vm.c
+++ b/tests/intel/xe_vm.c
@@ -52,7 +52,8 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
batch_bo = xe_bo_create(fd, vm, batch_size,
- visible_vram_if_possible(fd, 0));
+ vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
batch_map = xe_bo_map(fd, batch_bo, batch_size);
for (i = 0; i < n_dwords; i++) {
@@ -116,7 +117,8 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
vms = malloc(sizeof(*vms) * n_addrs);
igt_assert(vms);
}
- bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
map = xe_bo_map(fd, bo, bo_size);
memset(map, 0, bo_size);
@@ -379,7 +381,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
for (i = 0; i < n_bo; ++i) {
bo[i] = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data[i] = xe_bo_map(fd, bo[i], bo_size);
}
@@ -558,7 +561,8 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < N_EXEC_QUEUES; i++) {
@@ -739,7 +743,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
if (flags & BIND_ARRAY_BIND_EXEC_QUEUE_FLAG)
@@ -937,7 +942,8 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
xe_visible_vram_size(fd, 0));
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
map = xe_bo_map(fd, bo, bo_size);
}
@@ -1229,7 +1235,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(map != MAP_FAILED);
} else {
bo = xe_bo_create(fd, vm, bo_size,
- visible_vram_if_possible(fd, eci->gt_id));
+ vram_if_possible(fd, eci->gt_id) |
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
map = xe_bo_map(fd, bo, bo_size);
}
memset(map, 0, bo_size);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 18/20] drm-uapi/xe: Separate bo_create placement from flags
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (16 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 17/20] xe_query: Kill visible_vram_if_possible Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 19/20] drm-uapi/xe: Align with GuC version type update Francois Dugast
` (2 subsequent siblings)
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Align with kernel commit ("drm/xe/uapi: Separate bo_create placement from flags")
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
include/drm-uapi/xe_drm.h | 12 +++++-----
lib/igt_draw.c | 2 +-
lib/igt_fb.c | 6 ++---
lib/intel_batchbuffer.c | 4 ++--
lib/intel_blt.c | 2 +-
lib/intel_bufops.c | 2 +-
lib/xe/xe_ioctl.c | 12 +++++-----
lib/xe/xe_ioctl.h | 7 +++---
lib/xe/xe_query.c | 14 ------------
lib/xe/xe_query.h | 1 -
lib/xe/xe_spin.c | 4 ++--
tests/intel/api_intel_allocator.c | 2 +-
tests/intel/kms_big_fb.c | 6 ++---
tests/intel/xe_ccs.c | 12 +++++-----
tests/intel/xe_create.c | 4 ++--
tests/intel/xe_dma_buf_sync.c | 2 +-
tests/intel/xe_drm_fdinfo.c | 6 ++---
tests/intel/xe_evict.c | 22 +++++++++++-------
tests/intel/xe_exec_balancer.c | 6 ++---
tests/intel/xe_exec_basic.c | 5 +++--
tests/intel/xe_exec_compute_mode.c | 2 +-
tests/intel/xe_exec_fault_mode.c | 4 ++--
tests/intel/xe_exec_reset.c | 11 ++++-----
tests/intel/xe_exec_store.c | 4 ++--
tests/intel/xe_exec_threads.c | 6 ++---
tests/intel/xe_exercise_blt.c | 4 ++--
tests/intel/xe_guc_pc.c | 2 +-
tests/intel/xe_intel_bb.c | 2 +-
tests/intel/xe_mmap.c | 36 +++++++++++++++++-------------
tests/intel/xe_noexec_ping_pong.c | 2 +-
tests/intel/xe_pm.c | 10 ++++-----
tests/intel/xe_pm_residency.c | 2 +-
tests/intel/xe_prime_self_import.c | 18 +++++++--------
tests/intel/xe_spin_batch.c | 2 +-
tests/intel/xe_vm.c | 20 ++++++++---------
tests/intel/xe_waitfence.c | 16 ++++++-------
tests/kms_addfb_basic.c | 2 +-
tests/kms_getfb.c | 2 +-
38 files changed, 137 insertions(+), 139 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 85f419d16..6e29a6776 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -607,9 +607,12 @@ struct drm_xe_gem_create {
*/
__u64 size;
-#define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
-#define DRM_XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
-#define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26)
+ /** @placement: A mask of memory instances of where BO can be placed. */
+ __u32 placement;
+
+#define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0)
+#define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1)
+#define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2)
/**
* @flags: Flags, currently a mask of memory instances of where BO can
* be placed
@@ -633,9 +636,6 @@ struct drm_xe_gem_create {
*/
__u32 handle;
- /** @pad: MBZ */
- __u32 pad;
-
/** @reserved: Reserved */
__u64 reserved[2];
};
diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index d02125c47..d07552f02 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -791,7 +791,7 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,
else
tmp.handle = xe_bo_create(fd, 0,
ALIGN(tmp.size, xe_get_default_alignment(fd)),
- vram_if_possible(fd, 0) |
+ vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
tmp.stride = rect->w * pixel_size;
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 66f4ccdc4..c9aeb3ce2 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -1206,8 +1206,8 @@ static int create_bo_for_fb(struct igt_fb *fb, bool prefer_sysmem)
igt_assert(err == 0 || err == -EOPNOTSUPP);
} else if (is_xe_device(fd)) {
fb->gem_handle = xe_bo_create(fd, 0, fb->size,
- vram_if_possible(fd, 0)
- | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+ vram_if_possible(fd, 0),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
} else if (is_vc4_device(fd)) {
fb->gem_handle = igt_vc4_create_bo(fd, fb->size);
@@ -2904,7 +2904,7 @@ static void blitcopy(const struct igt_fb *dst_fb,
bb_size = ALIGN(bb_size + xe_cs_prefetch_size(dst_fb->fd),
xe_get_default_alignment(dst_fb->fd));
- xe_bb = xe_bo_create(dst_fb->fd, 0, bb_size, mem_region);
+ xe_bb = xe_bo_create(dst_fb->fd, 0, bb_size, mem_region, 0);
}
for (int i = 0; i < dst_fb->num_planes - dst_cc; i++) {
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 05dd6e35c..334814fb7 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -945,7 +945,7 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
ibb->alignment = xe_get_default_alignment(fd);
size = ALIGN(size, ibb->alignment);
- ibb->handle = xe_bo_create(fd, 0, size, vram_if_possible(fd, 0) |
+ ibb->handle = xe_bo_create(fd, 0, size, vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
/* Limit to 48-bit due to MI_* address limitation */
@@ -1405,7 +1405,7 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
ibb->handle = gem_create(ibb->fd, ibb->size);
else
ibb->handle = xe_bo_create(ibb->fd, 0, ibb->size,
- vram_if_possible(ibb->fd, 0) |
+ vram_if_possible(ibb->fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
/* Reacquire offset for RELOC and SIMPLE */
diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 9e4d8c535..3c7ee8320 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1422,7 +1422,7 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region,
if (blt->driver == INTEL_DRIVER_XE) {
size = ALIGN(size, xe_get_default_alignment(blt->fd));
- handle = xe_bo_create(blt->fd, 0, size, region);
+ handle = xe_bo_create(blt->fd, 0, size, region, 0);
} else {
igt_assert(__gem_create_in_memory_regions(blt->fd, &handle,
&size, region) == 0);
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 6f3a77f47..5582481f6 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -920,7 +920,7 @@ static void __intel_buf_init(struct buf_ops *bops,
igt_assert_eq(__gem_create(bops->fd, &size, &buf->handle), 0);
} else {
size = ALIGN(size, xe_get_default_alignment(bops->fd));
- buf->handle = xe_bo_create(bops->fd, 0, size, region);
+ buf->handle = xe_bo_create(bops->fd, 0, size, region, 0);
}
}
diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 4e21e4c84..30f35657d 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -238,12 +238,13 @@ static bool vram_selected(int fd, uint32_t selected_regions)
return false;
}
-uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags,
- uint32_t *handle)
+uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t placement,
+ uint32_t flags, uint32_t *handle)
{
struct drm_xe_gem_create create = {
.vm_id = vm,
.size = size,
+ .placement = placement,
.flags = flags,
};
int err;
@@ -252,7 +253,7 @@ uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags,
* In case vram_if_possible returned system_memory,
* visible VRAM cannot be requested through flags
*/
- if (!vram_selected(fd, flags))
+ if (!vram_selected(fd, placement))
create.flags &= ~DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
err = igt_ioctl(fd, DRM_IOCTL_XE_GEM_CREATE, &create);
@@ -263,11 +264,12 @@ uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags,
return 0;
}
-uint32_t xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags)
+uint32_t xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t placement,
+ uint32_t flags)
{
uint32_t handle;
- igt_assert_eq(__xe_bo_create(fd, vm, size, flags, &handle), 0);
+ igt_assert_eq(__xe_bo_create(fd, vm, size, placement, flags, &handle), 0);
return handle;
}
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index 294e9bc13..c19d0464b 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -64,9 +64,10 @@ void xe_vm_unbind_all_async(int fd, uint32_t vm, uint32_t exec_queue,
uint32_t bo, struct drm_xe_sync *sync,
uint32_t num_syncs);
void xe_vm_destroy(int fd, uint32_t vm);
-uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags,
- uint32_t *handle);
-uint32_t xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags);
+uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t placement,
+ uint32_t flags, uint32_t *handle);
+uint32_t xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t placement,
+ uint32_t flags);
uint32_t xe_exec_queue_create(int fd, uint32_t vm,
struct drm_xe_engine_class_instance *instance,
uint64_t ext);
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 4329a7e80..68f334e6a 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -397,20 +397,6 @@ uint64_t vram_memory(int fd, int gt)
return xe_has_vram(fd) ? native_region_for_gt(xe_dev->gt_list, gt) : 0;
}
-/**
- * visible_vram_memory:
- * @fd: xe device fd
- * @gt: gt id
- *
- * Returns vram memory bitmask for xe device @fd and @gt id, with
- * DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU access is
- * possible.
- */
-uint64_t visible_vram_memory(int fd, int gt)
-{
- return vram_memory(fd, gt) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
-}
-
/**
* vram_if_possible:
* @fd: xe device fd
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index 60eddb126..eb30312ae 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -85,7 +85,6 @@ unsigned int xe_number_gt(int fd);
uint64_t all_memory_regions(int fd);
uint64_t system_memory(int fd);
uint64_t vram_memory(int fd, int gt);
-uint64_t visible_vram_memory(int fd, int gt);
uint64_t vram_if_possible(int fd, int gt);
struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 270b58bf5..91bc6664d 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -220,7 +220,7 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt)
}
spin->handle = xe_bo_create(fd, spin->vm, bo_size,
- vram_if_possible(fd, 0) |
+ vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
xe_spin = xe_bo_map(fd, spin->handle, bo_size);
addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
@@ -299,7 +299,7 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
vm = xe_vm_create(fd, 0, 0);
- bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, hwe->gt_id) |
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, hwe->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
spin = xe_bo_map(fd, bo, 0x1000);
diff --git a/tests/intel/api_intel_allocator.c b/tests/intel/api_intel_allocator.c
index 158fd86a1..2d01da7d0 100644
--- a/tests/intel/api_intel_allocator.c
+++ b/tests/intel/api_intel_allocator.c
@@ -469,7 +469,7 @@ static void __simple_allocs(int fd)
size = (rand() % 4 + 1) * 0x1000;
if (is_xe)
handles[i] = xe_bo_create(fd, 0, size,
- system_memory(fd));
+ system_memory(fd), 0);
else
handles[i] = gem_create(fd, size);
diff --git a/tests/intel/kms_big_fb.c b/tests/intel/kms_big_fb.c
index 91848d69e..221ec8fc5 100644
--- a/tests/intel/kms_big_fb.c
+++ b/tests/intel/kms_big_fb.c
@@ -788,7 +788,7 @@ test_size_overflow(data_t *data)
bo = xe_bo_create(data->drm_fd, 0,
ALIGN(((1ULL << 32) - 4096),
xe_get_default_alignment(data->drm_fd)),
- vram_if_possible(data->drm_fd, 0));
+ vram_if_possible(data->drm_fd, 0), 0);
igt_require(bo);
ret = __kms_addfb(data->drm_fd, bo,
@@ -856,7 +856,7 @@ test_size_offset_overflow(data_t *data)
bo = xe_bo_create(data->drm_fd, 0,
ALIGN(((1ULL << 32) - 4096),
xe_get_default_alignment(data->drm_fd)),
- vram_if_possible(data->drm_fd, 0));
+ vram_if_possible(data->drm_fd, 0), 0);
igt_require(bo);
offsets[0] = 0;
@@ -944,7 +944,7 @@ test_addfb(data_t *data)
else
bo = xe_bo_create(data->drm_fd, 0,
ALIGN(size, xe_get_default_alignment(data->drm_fd)),
- vram_if_possible(data->drm_fd, 0));
+ vram_if_possible(data->drm_fd, 0), 0);
igt_require(bo);
if (is_i915_device(data->drm_fd) && intel_display_ver(data->devid) < 4)
diff --git a/tests/intel/xe_ccs.c b/tests/intel/xe_ccs.c
index 1b36ceb1e..9fcaf458c 100644
--- a/tests/intel/xe_ccs.c
+++ b/tests/intel/xe_ccs.c
@@ -102,8 +102,8 @@ static void surf_copy(int xe,
igt_assert(mid->compression);
ccscopy = (uint32_t *) malloc(ccssize);
- ccs = xe_bo_create(xe, 0, ccssize, sysmem);
- ccs2 = xe_bo_create(xe, 0, ccssize, sysmem);
+ ccs = xe_bo_create(xe, 0, ccssize, sysmem, 0);
+ ccs2 = xe_bo_create(xe, 0, ccssize, sysmem, 0);
blt_ctrl_surf_copy_init(xe, &surf);
surf.print_bb = param.print_bb;
@@ -111,7 +111,7 @@ static void surf_copy(int xe,
uc_mocs, BLT_INDIRECT_ACCESS);
blt_set_ctrl_surf_object(&surf.dst, ccs, sysmem, ccssize, uc_mocs, DIRECT_ACCESS);
bb_size = xe_get_default_alignment(xe);
- bb1 = xe_bo_create(xe, 0, bb_size, sysmem);
+ bb1 = xe_bo_create(xe, 0, bb_size, sysmem, 0);
blt_set_batch(&surf.bb, bb1, bb_size, sysmem);
blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf);
intel_ctx_xe_sync(ctx, true);
@@ -166,7 +166,7 @@ static void surf_copy(int xe,
blt_set_copy_object(&blt.dst, dst);
blt_set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D);
blt_set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D);
- bb2 = xe_bo_create(xe, 0, bb_size, sysmem);
+ bb2 = xe_bo_create(xe, 0, bb_size, sysmem, 0);
blt_set_batch(&blt.bb, bb2, bb_size, sysmem);
blt_block_copy(xe, ctx, NULL, ahnd, &blt, &ext);
intel_ctx_xe_sync(ctx, true);
@@ -297,7 +297,7 @@ static void block_copy(int xe,
uint8_t uc_mocs = intel_get_uc_mocs(xe);
int result;
- bb = xe_bo_create(xe, 0, bb_size, region1);
+ bb = xe_bo_create(xe, 0, bb_size, region1, 0);
if (!blt_uses_extended_block_copy(xe))
pext = NULL;
@@ -418,7 +418,7 @@ static void block_multicopy(int xe,
uint8_t uc_mocs = intel_get_uc_mocs(xe);
int result;
- bb = xe_bo_create(xe, 0, bb_size, region1);
+ bb = xe_bo_create(xe, 0, bb_size, region1, 0);
if (!blt_uses_extended_block_copy(xe))
pext3 = NULL;
diff --git a/tests/intel/xe_create.c b/tests/intel/xe_create.c
index 4242e1a67..4326b15e8 100644
--- a/tests/intel/xe_create.c
+++ b/tests/intel/xe_create.c
@@ -18,13 +18,13 @@
#define PAGE_SIZE 0x1000
-static int __create_bo(int fd, uint32_t vm, uint64_t size, uint32_t flags,
+static int __create_bo(int fd, uint32_t vm, uint64_t size, uint32_t placement,
uint32_t *handlep)
{
struct drm_xe_gem_create create = {
.vm_id = vm,
.size = size,
- .flags = flags,
+ .placement = placement,
};
int ret = 0;
diff --git a/tests/intel/xe_dma_buf_sync.c b/tests/intel/xe_dma_buf_sync.c
index 9318647af..aeb4c4995 100644
--- a/tests/intel/xe_dma_buf_sync.c
+++ b/tests/intel/xe_dma_buf_sync.c
@@ -120,7 +120,7 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
xe_get_default_alignment(fd[0]));
for (i = 0; i < n_bo; ++i) {
bo[i] = xe_bo_create(fd[0], 0, bo_size,
- vram_if_possible(fd[0], hwe0->gt_id) |
+ vram_if_possible(fd[0], hwe0->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd[i] = prime_handle_to_fd(fd[0], bo[i]);
import_bo[i] = prime_fd_to_handle(fd[1], dma_buf_fd[i]);
diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
index 8f737a533..6bca5a6f1 100644
--- a/tests/intel/xe_drm_fdinfo.c
+++ b/tests/intel/xe_drm_fdinfo.c
@@ -85,7 +85,7 @@ static void test_active(int fd, struct drm_xe_engine_class_instance *eci)
igt_assert_f(ret != 0, "failed with err:%d\n", errno);
pre_size = info.region_mem[memregion->instance + 1].active;
- bo = xe_bo_create(fd, vm, bo_size, region);
+ bo = xe_bo_create(fd, vm, bo_size, region, 0);
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < N_EXEC_QUEUES; i++) {
@@ -185,7 +185,7 @@ static void test_shared(int xe)
igt_assert_f(ret != 0, "failed with err:%d\n", errno);
pre_size = info.region_mem[memregion->instance + 1].shared;
- bo = xe_bo_create(xe, 0, BO_SIZE, region);
+ bo = xe_bo_create(xe, 0, BO_SIZE, region, 0);
flink.handle = bo;
ret = igt_ioctl(xe, DRM_IOCTL_GEM_FLINK, &flink);
@@ -232,7 +232,7 @@ static void test_total_resident(int xe)
igt_assert_f(ret != 0, "failed with err:%d\n", errno);
pre_size = info.region_mem[memregion->instance + 1].shared;
- handle = xe_bo_create(xe, vm, BO_SIZE, region);
+ handle = xe_bo_create(xe, vm, BO_SIZE, region, 0);
xe_vm_bind_sync(xe, vm, handle, 0, addr, BO_SIZE);
ret = igt_parse_drm_fdinfo(xe, &info, NULL, 0, NULL, 0);
diff --git a/tests/intel/xe_evict.c b/tests/intel/xe_evict.c
index ec25f9eff..83d0750b5 100644
--- a/tests/intel/xe_evict.c
+++ b/tests/intel/xe_evict.c
@@ -101,16 +101,19 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
if (flags & MULTI_VM) {
__bo = bo[i] = xe_bo_create(fd, 0,
bo_size,
- visible_vram_memory(fd, eci->gt_id));
+ vram_memory(fd, eci->gt_id),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
} else if (flags & THREADED) {
__bo = bo[i] = xe_bo_create(fd, vm,
bo_size,
- visible_vram_memory(fd, eci->gt_id));
+ vram_memory(fd, eci->gt_id),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
} else {
__bo = bo[i] = xe_bo_create(fd, _vm,
bo_size,
- visible_vram_memory(fd, eci->gt_id) |
- system_memory(fd));
+ vram_memory(fd, eci->gt_id) |
+ system_memory(fd),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
}
} else {
__bo = bo[i % (n_execs / 2)];
@@ -277,16 +280,19 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
if (flags & MULTI_VM) {
__bo = bo[i] = xe_bo_create(fd, 0,
bo_size,
- visible_vram_memory(fd, eci->gt_id));
+ vram_memory(fd, eci->gt_id),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
} else if (flags & THREADED) {
__bo = bo[i] = xe_bo_create(fd, vm,
bo_size,
- visible_vram_memory(fd, eci->gt_id));
+ vram_memory(fd, eci->gt_id),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
} else {
__bo = bo[i] = xe_bo_create(fd, _vm,
bo_size,
- visible_vram_memory(fd, eci->gt_id) |
- system_memory(fd));
+ vram_memory(fd, eci->gt_id) |
+ system_memory(fd),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
}
} else {
__bo = bo[i % (n_execs / 2)];
diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c
index 388bb6185..fa3d7a338 100644
--- a/tests/intel/xe_exec_balancer.c
+++ b/tests/intel/xe_exec_balancer.c
@@ -70,7 +70,7 @@ static void test_all_active(int fd, int gt, int class)
bo_size = sizeof(*data) * num_placements;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
@@ -225,7 +225,7 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs,
}
memset(data, 0, bo_size);
} else {
- bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
@@ -454,7 +454,7 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs,
igt_assert(data);
}
} else {
- bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c
index ca287b2e5..23acdd434 100644
--- a/tests/intel/xe_exec_basic.c
+++ b/tests/intel/xe_exec_basic.c
@@ -136,11 +136,12 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
} else {
uint32_t bo_flags;
- bo_flags = vram_if_possible(fd, eci->gt_id) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
+ bo_flags = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
if (flags & DEFER_ALLOC)
bo_flags |= DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING;
- bo = xe_bo_create(fd, n_vm == 1 ? vm[0] : 0, bo_size, bo_flags);
+ bo = xe_bo_create(fd, n_vm == 1 ? vm[0] : 0, bo_size,
+ vram_if_possible(fd, eci->gt_id), bo_flags);
if (!(flags & DEFER_BIND))
data = xe_bo_map(fd, bo, bo_size);
}
diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c
index 07a27fd29..98a98256e 100644
--- a/tests/intel/xe_exec_compute_mode.c
+++ b/tests/intel/xe_exec_compute_mode.c
@@ -142,7 +142,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
}
} else {
bo = xe_bo_create(fd, flags & VM_FOR_BO ? vm : 0,
- bo_size, vram_if_possible(fd, eci->gt_id) |
+ bo_size, vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c
index bfd61c4ea..3eb448ef4 100644
--- a/tests/intel/xe_exec_fault_mode.c
+++ b/tests/intel/xe_exec_fault_mode.c
@@ -153,11 +153,11 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
if (flags & PREFETCH)
bo = xe_bo_create(fd, 0, bo_size,
all_memory_regions(fd) |
- vram_if_possible(fd, 0) |
+ vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
else
bo = xe_bo_create(fd, 0, bo_size,
- vram_if_possible(fd, eci->gt_id) |
+ vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
index 3affb19ae..d8b8e0355 100644
--- a/tests/intel/xe_exec_reset.c
+++ b/tests/intel/xe_exec_reset.c
@@ -51,7 +51,7 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, eci->gt_id) |
+ vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
spin = xe_bo_map(fd, bo, bo_size);
@@ -182,7 +182,7 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
@@ -370,7 +370,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, eci->gt_id) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+ vram_if_possible(fd, eci->gt_id),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < n_exec_queues; i++) {
@@ -537,7 +538,7 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, eci->gt_id) |
+ vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
memset(data, 0, bo_size);
@@ -664,7 +665,7 @@ static void submit_jobs(struct gt_thread_data *t)
uint32_t bo;
uint32_t *data;
- bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0) |
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
data[0] = MI_BATCH_BUFFER_END;
diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
index f999a2bb4..c083ac65a 100644
--- a/tests/intel/xe_exec_store.c
+++ b/tests/intel/xe_exec_store.c
@@ -82,7 +82,7 @@ static void store(int fd)
hw_engine = xe_hw_engine(fd, 1);
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, hw_engine->gt_id) |
+ vram_if_possible(fd, hw_engine->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
xe_vm_bind_async(fd, vm, hw_engine->gt_id, bo, 0, addr, bo_size, &sync, 1);
@@ -139,7 +139,7 @@ static void store_all(int fd, int gt, int class)
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, 0) |
+ vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c
index d6505f522..cb8944a2d 100644
--- a/tests/intel/xe_exec_threads.c
+++ b/tests/intel/xe_exec_threads.c
@@ -107,7 +107,7 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
}
} else {
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, gt) |
+ vram_if_possible(fd, gt),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
@@ -309,7 +309,7 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
}
} else {
bo = xe_bo_create(fd, 0, bo_size,
- vram_if_possible(fd, eci->gt_id) |
+ vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
@@ -513,7 +513,7 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
}
} else {
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, eci->gt_id) |
+ vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
}
diff --git a/tests/intel/xe_exercise_blt.c b/tests/intel/xe_exercise_blt.c
index 9c69be3ef..655e9a3ea 100644
--- a/tests/intel/xe_exercise_blt.c
+++ b/tests/intel/xe_exercise_blt.c
@@ -125,7 +125,7 @@ static void fast_copy_emit(int xe, const intel_ctx_t *ctx,
uint32_t bb, width = param.width, height = param.height;
int result;
- bb = xe_bo_create(xe, 0, bb_size, region1);
+ bb = xe_bo_create(xe, 0, bb_size, region1, 0);
blt_copy_init(xe, &bltinit);
src = blt_create_object(&bltinit, region1, width, height, bpp, 0,
@@ -184,7 +184,7 @@ static void fast_copy(int xe, const intel_ctx_t *ctx,
uint32_t width = param.width, height = param.height;
int result;
- bb = xe_bo_create(xe, 0, bb_size, region1);
+ bb = xe_bo_create(xe, 0, bb_size, region1, 0);
blt_copy_init(xe, &blt);
src = blt_create_object(&blt, region1, width, height, bpp, 0,
diff --git a/tests/intel/xe_guc_pc.c b/tests/intel/xe_guc_pc.c
index 4234475e0..8d7b677b4 100644
--- a/tests/intel/xe_guc_pc.c
+++ b/tests/intel/xe_guc_pc.c
@@ -66,7 +66,7 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, eci->gt_id) |
+ vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
diff --git a/tests/intel/xe_intel_bb.c b/tests/intel/xe_intel_bb.c
index a3a315297..00bd17d4c 100644
--- a/tests/intel/xe_intel_bb.c
+++ b/tests/intel/xe_intel_bb.c
@@ -396,7 +396,7 @@ static void create_in_region(struct buf_ops *bops, uint64_t region)
intel_bb_set_debug(ibb, true);
size = xe_min_page_size(xe, system_memory(xe));
- handle = xe_bo_create(xe, 0, size, system_memory(xe));
+ handle = xe_bo_create(xe, 0, size, system_memory(xe), 0);
intel_buf_init_full(bops, handle, &buf,
width/4, height, 32, 0,
I915_TILING_NONE, 0,
diff --git a/tests/intel/xe_mmap.c b/tests/intel/xe_mmap.c
index a4b53ad48..965644e22 100644
--- a/tests/intel/xe_mmap.c
+++ b/tests/intel/xe_mmap.c
@@ -45,14 +45,14 @@
* @vram-system: system vram
*/
static void
-test_mmap(int fd, uint32_t flags)
+test_mmap(int fd, uint32_t placement, uint32_t flags)
{
uint32_t bo;
void *map;
- igt_require_f(flags, "Device doesn't support such memory region\n");
+ igt_require_f(placement, "Device doesn't support such memory region\n");
- bo = xe_bo_create(fd, 0, 4096, flags);
+ bo = xe_bo_create(fd, 0, 4096, placement, flags);
map = xe_bo_map(fd, bo, 4096);
strcpy(map, "Write some data to the BO!");
@@ -73,7 +73,7 @@ static void test_bad_flags(int fd)
uint64_t size = xe_get_default_alignment(fd);
struct drm_xe_gem_mmap_offset mmo = {
.handle = xe_bo_create(fd, 0, size,
- vram_if_possible(fd, 0) |
+ vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM),
.flags = -1u,
};
@@ -94,7 +94,7 @@ static void test_bad_extensions(int fd)
struct xe_user_extension ext;
struct drm_xe_gem_mmap_offset mmo = {
.handle = xe_bo_create(fd, 0, size,
- vram_if_possible(fd, 0) |
+ vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM),
};
@@ -116,7 +116,7 @@ static void test_bad_object(int fd)
uint64_t size = xe_get_default_alignment(fd);
struct drm_xe_gem_mmap_offset mmo = {
.handle = xe_bo_create(fd, 0, size,
- vram_if_possible(fd, 0) |
+ vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM),
};
@@ -163,12 +163,14 @@ static void test_small_bar(int fd)
/* 2BIG invalid case */
igt_assert_neq(__xe_bo_create(fd, 0, visible_size + 4096,
- visible_vram_memory(fd, 0), &bo),
+ vram_memory(fd, 0),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM,
+ &bo),
0);
/* Normal operation */
- bo = xe_bo_create(fd, 0, visible_size / 4,
- visible_vram_memory(fd, 0));
+ bo = xe_bo_create(fd, 0, visible_size / 4, vram_memory(fd, 0),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
mmo = xe_bo_mmap_offset(fd, bo);
map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
igt_assert(map != MAP_FAILED);
@@ -180,8 +182,9 @@ static void test_small_bar(int fd)
/* Normal operation with system memory spilling */
bo = xe_bo_create(fd, 0, visible_size,
- visible_vram_memory(fd, 0) |
- system_memory(fd));
+ vram_memory(fd, 0) |
+ system_memory(fd),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
mmo = xe_bo_mmap_offset(fd, bo);
map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
igt_assert(map != MAP_FAILED);
@@ -192,8 +195,7 @@ static void test_small_bar(int fd)
gem_close(fd, bo);
/* Bogus operation with SIGBUS */
- bo = xe_bo_create(fd, 0, visible_size + 4096,
- vram_memory(fd, 0));
+ bo = xe_bo_create(fd, 0, visible_size + 4096, vram_memory(fd, 0), 0);
mmo = xe_bo_mmap_offset(fd, bo);
map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
igt_assert(map != MAP_FAILED);
@@ -210,13 +212,15 @@ igt_main
fd = drm_open_driver(DRIVER_XE);
igt_subtest("system")
- test_mmap(fd, system_memory(fd));
+ test_mmap(fd, system_memory(fd), 0);
igt_subtest("vram")
- test_mmap(fd, visible_vram_memory(fd, 0));
+ test_mmap(fd, vram_memory(fd, 0),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
igt_subtest("vram-system")
- test_mmap(fd, visible_vram_memory(fd, 0) | system_memory(fd));
+ test_mmap(fd, vram_memory(fd, 0) | system_memory(fd),
+ DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
igt_subtest("bad-flags")
test_bad_flags(fd);
diff --git a/tests/intel/xe_noexec_ping_pong.c b/tests/intel/xe_noexec_ping_pong.c
index 88ef39783..5e3349247 100644
--- a/tests/intel/xe_noexec_ping_pong.c
+++ b/tests/intel/xe_noexec_ping_pong.c
@@ -71,7 +71,7 @@ static void test_ping_pong(int fd, struct drm_xe_engine_class_instance *eci)
(unsigned int) vm[i]);
bo[i][j] = xe_bo_create(fd, vm[i], bo_size,
- vram_memory(fd, 0));
+ vram_memory(fd, 0), 0);
xe_vm_bind(fd, vm[i], bo[i][j], 0, 0x40000 + j*bo_size,
bo_size, NULL, 0);
}
diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c
index df85f2c05..4f42a2c3b 100644
--- a/tests/intel/xe_pm.c
+++ b/tests/intel/xe_pm.c
@@ -272,7 +272,7 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
bo = xe_bo_create(device.fd_xe, vm, bo_size,
- vram_if_possible(device.fd_xe, eci->gt_id) |
+ vram_if_possible(device.fd_xe, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(device.fd_xe, bo, bo_size);
@@ -381,15 +381,15 @@ static void test_vram_d3cold_threshold(device_t device, int sysfs_fd)
.data = 0,
};
uint64_t vram_used_mb = 0, vram_total_mb = 0, threshold;
- uint32_t bo, flags;
+ uint32_t bo, placement;
int handle, i;
bool active;
void *map;
igt_require(xe_has_vram(device.fd_xe));
- flags = vram_memory(device.fd_xe, 0);
- igt_require_f(flags, "Device doesn't support vram memory region\n");
+ placement = vram_memory(device.fd_xe, 0);
+ igt_require_f(placement, "Device doesn't support vram memory region\n");
igt_assert_eq(igt_ioctl(device.fd_xe, DRM_IOCTL_XE_DEVICE_QUERY, &query), 0);
igt_assert_neq(query.size, 0);
@@ -410,7 +410,7 @@ static void test_vram_d3cold_threshold(device_t device, int sysfs_fd)
threshold = vram_used_mb + (SIZE / 1024 /1024);
igt_require(threshold < vram_total_mb);
- bo = xe_bo_create(device.fd_xe, 0, SIZE, flags);
+ bo = xe_bo_create(device.fd_xe, 0, SIZE, placement, 0);
map = xe_bo_map(device.fd_xe, bo, SIZE);
memset(map, 0, SIZE);
munmap(map, SIZE);
diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c
index 40a1693b8..6c9a95429 100644
--- a/tests/intel/xe_pm_residency.c
+++ b/tests/intel/xe_pm_residency.c
@@ -101,7 +101,7 @@ static void exec_load(int fd, struct drm_xe_engine_class_instance *hwe, unsigned
bo_size = xe_get_default_alignment(fd);
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, hwe->gt_id) |
+ vram_if_possible(fd, hwe->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
syncobj = syncobj_create(fd, 0);
diff --git a/tests/intel/xe_prime_self_import.c b/tests/intel/xe_prime_self_import.c
index df2d8635b..8fbf66e13 100644
--- a/tests/intel/xe_prime_self_import.c
+++ b/tests/intel/xe_prime_self_import.c
@@ -106,7 +106,7 @@ static void test_with_fd_dup(void)
fd1 = drm_open_driver(DRIVER_XE);
fd2 = drm_open_driver(DRIVER_XE);
- handle = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
+ handle = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
@@ -140,9 +140,9 @@ static void test_with_two_bos(void)
fd1 = drm_open_driver(DRIVER_XE);
fd2 = drm_open_driver(DRIVER_XE);
- handle1 = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
+ handle1 = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
- handle2 = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
+ handle2 = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd = prime_handle_to_fd(fd1, handle1);
@@ -179,7 +179,7 @@ static void test_with_one_bo_two_files(void)
fd2 = drm_open_driver(DRIVER_XE);
handle_orig = xe_bo_create(fd1, 0, BO_SIZE,
- vram_if_possible(fd1, 0) |
+ vram_if_possible(fd1, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd1 = prime_handle_to_fd(fd1, handle_orig);
@@ -212,7 +212,7 @@ static void test_with_one_bo(void)
fd1 = drm_open_driver(DRIVER_XE);
fd2 = drm_open_driver(DRIVER_XE);
- handle = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
+ handle = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd = prime_handle_to_fd(fd1, handle);
@@ -300,7 +300,7 @@ static void *thread_fn_reimport_vs_close(void *p)
fds[0] = drm_open_driver(DRIVER_XE);
handle = xe_bo_create(fds[0], 0, BO_SIZE,
- vram_if_possible(fds[0], 0) |
+ vram_if_possible(fds[0], 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
fds[1] = prime_handle_to_fd(fds[0], handle);
@@ -344,7 +344,7 @@ static void *thread_fn_export_vs_close(void *p)
igt_until_timeout(g_time_out) {
/* We want to race gem close against prime export on handle one.*/
handle = xe_bo_create(fd, 0, 4096,
- vram_if_possible(fd, 0) |
+ vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
if (handle != 1)
gem_close(fd, handle);
@@ -442,7 +442,7 @@ static void test_llseek_size(void)
int bufsz = xe_get_default_alignment(fd) << i;
handle = xe_bo_create(fd, 0, bufsz,
- vram_if_possible(fd, 0) |
+ vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd = prime_handle_to_fd(fd, handle);
@@ -472,7 +472,7 @@ static void test_llseek_bad(void)
fd = drm_open_driver(DRIVER_XE);
handle = xe_bo_create(fd, 0, BO_SIZE,
- vram_if_possible(fd, 0) |
+ vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
dma_buf_fd = prime_handle_to_fd(fd, handle);
diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index c1b161f9c..6abe700da 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -169,7 +169,7 @@ static void xe_spin_fixed_duration(int fd)
exec_queue = xe_exec_queue_create_class(fd, vm, DRM_XE_ENGINE_CLASS_COPY);
ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
bo_size = ALIGN(sizeof(*spin) + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0));
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0), 0);
spin = xe_bo_map(fd, bo, bo_size);
spin_addr = intel_allocator_alloc_with_strategy(ahnd, bo, bo_size, 0,
ALLOC_STRATEGY_LOW_TO_HIGH);
diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
index 7e66786d4..6d593c632 100644
--- a/tests/intel/xe_vm.c
+++ b/tests/intel/xe_vm.c
@@ -52,7 +52,7 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
batch_bo = xe_bo_create(fd, vm, batch_size,
- vram_if_possible(fd, 0) |
+ vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
batch_map = xe_bo_map(fd, batch_bo, batch_size);
@@ -117,7 +117,7 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
vms = malloc(sizeof(*vms) * n_addrs);
igt_assert(vms);
}
- bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0) |
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
map = xe_bo_map(fd, bo, bo_size);
memset(map, 0, bo_size);
@@ -278,7 +278,7 @@ static void unbind_all(int fd, int n_vmas)
};
vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
- bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0));
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0), 0);
for (i = 0; i < n_vmas; ++i)
xe_vm_bind_async(fd, vm, 0, bo, 0, addr + i * bo_size,
@@ -381,7 +381,7 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
for (i = 0; i < n_bo; ++i) {
bo[i] = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, eci->gt_id) |
+ vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data[i] = xe_bo_map(fd, bo[i], bo_size);
}
@@ -561,7 +561,7 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, eci->gt_id) |
+ vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
@@ -743,7 +743,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
xe_get_default_alignment(fd));
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, eci->gt_id) |
+ vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
data = xe_bo_map(fd, bo, bo_size);
@@ -942,7 +942,7 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
xe_visible_vram_size(fd, 0));
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, eci->gt_id) |
+ vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
map = xe_bo_map(fd, bo, bo_size);
}
@@ -1235,7 +1235,7 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(map != MAP_FAILED);
} else {
bo = xe_bo_create(fd, vm, bo_size,
- vram_if_possible(fd, eci->gt_id) |
+ vram_if_possible(fd, eci->gt_id),
DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
map = xe_bo_map(fd, bo, bo_size);
}
@@ -1539,9 +1539,9 @@ test_mmap_style_bind(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(map0 != MAP_FAILED);
igt_assert(map1 != MAP_FAILED);
} else {
- bo0 = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id));
+ bo0 = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id), 0);
map0 = xe_bo_map(fd, bo0, bo_size);
- bo1 = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id));
+ bo1 = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id), 0);
map1 = xe_bo_map(fd, bo1, bo_size);
}
memset(map0, 0, bo_size);
diff --git a/tests/intel/xe_waitfence.c b/tests/intel/xe_waitfence.c
index 913afcdb5..f57785aa4 100644
--- a/tests/intel/xe_waitfence.c
+++ b/tests/intel/xe_waitfence.c
@@ -22,8 +22,6 @@
* Description: Test waitfences functionality
*/
-#define MY_FLAG vram_if_possible(fd, 0)
-
uint64_t wait_fence = 0;
static void do_bind(int fd, uint32_t vm, uint32_t bo, uint64_t offset,
@@ -64,19 +62,19 @@ waitfence(int fd, enum waittype wt)
int64_t timeout;
uint32_t vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT, 0);
- bo_1 = xe_bo_create(fd, vm, 0x40000, MY_FLAG);
+ bo_1 = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0);
do_bind(fd, vm, bo_1, 0, 0x200000, 0x40000, 1);
- bo_2 = xe_bo_create(fd, vm, 0x40000, MY_FLAG);
+ bo_2 = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0);
do_bind(fd, vm, bo_2, 0, 0xc0000000, 0x40000, 2);
- bo_3 = xe_bo_create(fd, vm, 0x40000, MY_FLAG);
+ bo_3 = xe_bo_create(fd, vm, 0x40000, vram_if_possible(fd, 0), 0);
do_bind(fd, vm, bo_3, 0, 0x180000000, 0x40000, 3);
- bo_4 = xe_bo_create(fd, vm, 0x10000, MY_FLAG);
+ bo_4 = xe_bo_create(fd, vm, 0x10000, vram_if_possible(fd, 0), 0);
do_bind(fd, vm, bo_4, 0, 0x140000000, 0x10000, 4);
- bo_5 = xe_bo_create(fd, vm, 0x100000, MY_FLAG);
+ bo_5 = xe_bo_create(fd, vm, 0x100000, vram_if_possible(fd, 0), 0);
do_bind(fd, vm, bo_5, 0, 0x100000000, 0x100000, 5);
- bo_6 = xe_bo_create(fd, vm, 0x1c0000, MY_FLAG);
+ bo_6 = xe_bo_create(fd, vm, 0x1c0000, vram_if_possible(fd, 0), 0);
do_bind(fd, vm, bo_6, 0, 0xc0040000, 0x1c0000, 6);
- bo_7 = xe_bo_create(fd, vm, 0x10000, MY_FLAG);
+ bo_7 = xe_bo_create(fd, vm, 0x10000, vram_if_possible(fd, 0), 0);
do_bind(fd, vm, bo_7, 0, 0xeffff0000, 0x10000, 7);
if (wt == RELTIME) {
diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index 4f293c2ee..6814e1b8c 100644
--- a/tests/kms_addfb_basic.c
+++ b/tests/kms_addfb_basic.c
@@ -199,7 +199,7 @@ static void invalid_tests(int fd)
handle = gem_create_in_memory_regions(fd, size, REGION_SMEM);
} else {
igt_require(xe_has_vram(fd));
- handle = xe_bo_create(fd, 0, size, system_memory(fd));
+ handle = xe_bo_create(fd, 0, size, system_memory(fd), 0);
}
f.handles[0] = handle;
diff --git a/tests/kms_getfb.c b/tests/kms_getfb.c
index 1f9e813d8..6f8592d3a 100644
--- a/tests/kms_getfb.c
+++ b/tests/kms_getfb.c
@@ -149,7 +149,7 @@ static void get_ccs_fb(int fd, struct drm_mode_fb_cmd2 *ret)
if (is_i915_device(fd))
add.handles[0] = gem_buffer_create_fb_obj(fd, size);
else
- add.handles[0] = xe_bo_create(fd, 0, size, vram_if_possible(fd, 0));
+ add.handles[0] = xe_bo_create(fd, 0, size, vram_if_possible(fd, 0), 0);
igt_require(add.handles[0] != 0);
if (!HAS_FLATCCS(devid))
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 19/20] drm-uapi/xe: Align with GuC version type update
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (17 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 18/20] drm-uapi/xe: Separate bo_create placement from flags Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 20/20] drm-uapi/xe: Remove unused inaccessible memory region Francois Dugast
2023-10-12 0:20 ` [igt-dev] ✗ Fi.CI.BUILD: failure for uAPI Alignment - take 2 Patchwork
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Align with kernel commit ("drm/xe/uapi: Be more specific around GuC Version Type")
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
include/drm-uapi/xe_drm.h | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 6e29a6776..ce1a1cc2e 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -468,11 +468,23 @@ struct drm_xe_query_topology_mask {
*
* Given a uc_type this will return the major, minor, patch and branch version
* of the micro-controller firmware.
+ *
+ * The @uc_type can be:
+ * - %DRM_XE_QUERY_UC_TYPE_GUC_SUBMISSION - This is the GuC Submission Version,
+ * a.k.a 'VF version'. It is not the actual GuC blob version. A running GuC can
+ * support multiple VF APIs with different Submission Versions. This version is
+ * negotiated by the VF KMD with GuC during VF initialization. In most of the
+ * current available GuC blobs, this is a 1-1 relationship where the Submission
+ * version could be inferred from the running version and vice-versa. However,
+ * the submission version is the most useful information for the user space
+ * perspective and needs.
+ * - %DRM_XE_QUERY_TYPE_HUC - The actual HuC blob that is currently running
+ * in the platform. It returns 0 when HuC is not currently loaded.
*/
struct drm_xe_query_uc_fw_version {
/** @uc_type: The micro-controller type to query firmware version */
-#define DRM_XE_QUERY_UC_TYPE_GUC 0
-#define DRM_XE_QUERY_UC_TYPE_HUC 1
+#define DRM_XE_QUERY_UC_TYPE_GUC_SUBMISSION 0
+#define DRM_XE_QUERY_UC_TYPE_HUC 1
__u16 uc_type;
/** @pad: MBZ */
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [RFC v1 20/20] drm-uapi/xe: Remove unused inaccessible memory region
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (18 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 19/20] drm-uapi/xe: Align with GuC version type update Francois Dugast
@ 2023-10-11 14:18 ` Francois Dugast
2023-10-12 0:20 ` [igt-dev] ✗ Fi.CI.BUILD: failure for uAPI Alignment - take 2 Patchwork
20 siblings, 0 replies; 26+ messages in thread
From: Francois Dugast @ 2023-10-11 14:18 UTC (permalink / raw)
To: igt-dev
Align with commit ("drm/xe/uapi: Remove unused inaccessible memory region")
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
---
include/drm-uapi/xe_drm.h | 5 -----
tests/intel/xe_query.c | 2 --
2 files changed, 7 deletions(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index ce1a1cc2e..8d1949046 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -393,11 +393,6 @@ struct drm_xe_query_gt {
* they live on a different GPU/Tile.
*/
__u64 slow_mem_regions;
- /**
- * @inaccessible_mem_regions: Bit mask of instances from
- * drm_xe_query_mem_usage that is not accessible by this GT at all.
- */
- __u64 inaccessible_mem_regions;
/** @reserved: Reserved */
__u64 reserved[8];
};
diff --git a/tests/intel/xe_query.c b/tests/intel/xe_query.c
index c8d886bfe..29624a770 100644
--- a/tests/intel/xe_query.c
+++ b/tests/intel/xe_query.c
@@ -285,8 +285,6 @@ test_query_gt_list(int fd)
gt_list->gt_list[i].native_mem_regions);
igt_info("slow_mem_regions: 0x%016llx\n",
gt_list->gt_list[i].slow_mem_regions);
- igt_info("inaccessible_mem_regions: 0x%016llx\n",
- gt_list->gt_list[i].inaccessible_mem_regions);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] ✗ Fi.CI.BUILD: failure for uAPI Alignment - take 2
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
` (19 preceding siblings ...)
2023-10-11 14:18 ` [igt-dev] [RFC v1 20/20] drm-uapi/xe: Remove unused inaccessible memory region Francois Dugast
@ 2023-10-12 0:20 ` Patchwork
20 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2023-10-12 0:20 UTC (permalink / raw)
To: Francois Dugast; +Cc: igt-dev
== Series Details ==
Series: uAPI Alignment - take 2
URL : https://patchwork.freedesktop.org/series/124979/
State : failure
== Summary ==
Applying: drm-uapi/xe: Add documentation for query
Using index info to reconstruct a base tree...
M include/drm-uapi/xe_drm.h
Falling back to patching base and 3-way merge...
Auto-merging include/drm-uapi/xe_drm.h
CONFLICT (content): Merge conflict in include/drm-uapi/xe_drm.h
Patch failed at 0001 drm-uapi/xe: Add documentation for query
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [igt-dev] [RFC v1 11/20] drm-uapi/xe: Remove GT_TYPE_REMOTE.
2023-10-11 14:18 ` [igt-dev] [RFC v1 11/20] drm-uapi/xe: Remove GT_TYPE_REMOTE Francois Dugast
@ 2023-10-12 18:36 ` Kamil Konieczny
0 siblings, 0 replies; 26+ messages in thread
From: Kamil Konieczny @ 2023-10-12 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
Hi Francois,
On 2023-10-11 at 14:18:32 +0000, Francois Dugast wrote:
Remove dot from end of subject:
[RFC v1 11/20] drm-uapi/xe: Remove GT_TYPE_REMOTE.
-------------------------------------------------^
This should be:
[RFC v1 11/20] drm-uapi/xe: Remove GT_TYPE_REMOTE
Regards,
Kamil
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Align with commit ("drm/xe/uapi: Remove GT_TYPE_REMOTE")
>
> Cc: Francois Dugast <francois.dugast@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> include/drm-uapi/xe_drm.h | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
> index 2fc4278ae..09e6bef79 100644
> --- a/include/drm-uapi/xe_drm.h
> +++ b/include/drm-uapi/xe_drm.h
> @@ -376,9 +376,8 @@ struct drm_xe_query_config {
> */
> struct drm_xe_query_gt {
> #define DRM_XE_QUERY_GT_TYPE_MAIN 0
> -#define DRM_XE_QUERY_GT_TYPE_REMOTE 1
> -#define DRM_XE_QUERY_GT_TYPE_MEDIA 2
> - /** @type: GT type: Main, Remote, or Media */
> +#define DRM_XE_QUERY_GT_TYPE_MEDIA 1
> + /** @type: GT type: Main or Media */
> __u16 type;
> /** @gt_id: Unique ID of this GT within the PCI Device */
> __u16 gt_id;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [igt-dev] [RFC v1 13/20] drm/xe_query: Remove backward compatibility of vram_visible_size.
2023-10-11 14:18 ` [igt-dev] [RFC v1 13/20] drm/xe_query: Remove backward compatibility of vram_visible_size Francois Dugast
@ 2023-10-12 18:39 ` Kamil Konieczny
0 siblings, 0 replies; 26+ messages in thread
From: Kamil Konieczny @ 2023-10-12 18:39 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
Hi Francois,
On 2023-10-11 at 14:18:34 +0000, Francois Dugast wrote:
same here, remove dot from end of subject:
[RFC v1 13/20] drm/xe_query: Remove backward compatibility of vram_visible_size.
s/vram_visible_size./vram_visible_size/
Regards,
Kamil
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> We are breaking the uapi compatibility at this time, so this
> is useless anyway.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> lib/xe/xe_query.c | 42 +++++++-----------------------------------
> 1 file changed, 7 insertions(+), 35 deletions(-)
>
> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> index 76e245f9c..87841e8a3 100644
> --- a/lib/xe/xe_query.c
> +++ b/lib/xe/xe_query.c
> @@ -397,16 +397,6 @@ uint64_t vram_memory(int fd, int gt)
> return xe_has_vram(fd) ? native_region_for_gt(xe_dev->gt_list, gt) : 0;
> }
>
> -static uint64_t __xe_visible_vram_size(int fd, int gt)
> -{
> - struct xe_device *xe_dev;
> -
> - xe_dev = find_in_cache(fd);
> - igt_assert(xe_dev);
> -
> - return xe_dev->visible_vram_size[gt];
> -}
> -
> /**
> * visible_vram_memory:
> * @fd: xe device fd
> @@ -418,14 +408,7 @@ static uint64_t __xe_visible_vram_size(int fd, int gt)
> */
> uint64_t visible_vram_memory(int fd, int gt)
> {
> - /*
> - * TODO: Keep it backwards compat for now. Fixup once the kernel side
> - * has landed.
> - */
> - if (__xe_visible_vram_size(fd, gt))
> - return vram_memory(fd, gt) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
> - else
> - return vram_memory(fd, gt); /* older kernel */
> + return vram_memory(fd, gt) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
> }
>
> /**
> @@ -457,14 +440,7 @@ uint64_t visible_vram_if_possible(int fd, int gt)
> uint64_t system_memory = regions & 0x1;
> uint64_t vram = regions & (0x2 << gt);
>
> - /*
> - * TODO: Keep it backwards compat for now. Fixup once the kernel side
> - * has landed.
> - */
> - if (__xe_visible_vram_size(fd, gt))
> - return vram ? vram | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
> - else
> - return vram ? vram : system_memory; /* older kernel */
> + return vram ? vram | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
> }
>
> /**
> @@ -616,18 +592,14 @@ uint64_t xe_vram_size(int fd, int gt)
> */
> uint64_t xe_visible_vram_size(int fd, int gt)
> {
> - uint64_t visible_size;
> + struct xe_device *xe_dev;
>
> - /*
> - * TODO: Keep it backwards compat for now. Fixup once the kernel side
> - * has landed.
> - */
> - visible_size = __xe_visible_vram_size(fd, gt);
> - if (!visible_size) /* older kernel */
> - visible_size = xe_vram_size(fd, gt);
> + xe_dev = find_in_cache(fd);
> + igt_assert(xe_dev);
>
> - return visible_size;
> + return xe_dev->visible_vram_size[gt];
> }
> +
> /**
> * xe_vram_available:
> * @fd: xe device fd
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [igt-dev] [RFC v1 16/20] xe_query: Add missing include.
2023-10-11 14:18 ` [igt-dev] [RFC v1 16/20] xe_query: Add missing include Francois Dugast
@ 2023-10-12 18:44 ` Kamil Konieczny
0 siblings, 0 replies; 26+ messages in thread
From: Kamil Konieczny @ 2023-10-12 18:44 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
Hi Francois,
On 2023-10-11 at 14:18:37 +0000, Francois Dugast wrote:
please remove dot from end of subject:
[RFC v1 16/20] xe_query: Add missing include.
--------------------------------------------^
Also this looks like a fix, imho send this as separate patch,
without RFC in it or at least move it to take 1 or before
build break. +cc Ashutosh
Regards,
Kamil
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> When trying to use xe_for_each_mem_region from a caller
> that is not importing the igt_aux.h, the following build issue
> will occur:
>
> ../lib/xe/xe_query.h:76:38: error: implicit declaration of function ‘igt_fls’ [-Werror=implicit-function-declaration]
> 76 | for (uint64_t __i = 0; __i < igt_fls(__memreg); __i++) \
>
> So, to avoid a dependency chain, let's include from the file
> that is using the helper.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> lib/xe/xe_query.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> index 8557bb4c5..dcdfa52c2 100644
> --- a/lib/xe/xe_query.h
> +++ b/lib/xe/xe_query.h
> @@ -11,6 +11,8 @@
>
> #include <stdint.h>
> #include <xe_drm.h>
> +
> +#include "igt_aux.h"
> #include "igt_list.h"
>
> #define SZ_4K 0x1000
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [igt-dev] [RFC v1 17/20] xe_query: Kill visible_vram_if_possible
2023-10-11 14:18 ` [igt-dev] [RFC v1 17/20] xe_query: Kill visible_vram_if_possible Francois Dugast
@ 2023-10-12 18:46 ` Kamil Konieczny
0 siblings, 0 replies; 26+ messages in thread
From: Kamil Konieczny @ 2023-10-12 18:46 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi
Hi Francois,
On 2023-10-11 at 14:18:38 +0000, Francois Dugast wrote:
please add kms devs, +cc Bhanu and Juha-Pekka.
Regards,
Kamil
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Let the caller set the flag and the xe_bo_query clear if
> not needed.
>
> Although the current helper makes the code cleaner, the
> goal is to split the flags into placement and flags as two
> different arguments on xe_bo_create. So, the flag decision
> cannot be hidden under the helper.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> lib/igt_draw.c | 3 ++-
> lib/igt_fb.c | 3 ++-
> lib/intel_batchbuffer.c | 6 ++++--
> lib/xe/xe_ioctl.c | 19 +++++++++++++++++++
> lib/xe/xe_query.c | 19 -------------------
> lib/xe/xe_query.h | 1 -
> lib/xe/xe_spin.c | 7 ++++---
> tests/intel/xe_dma_buf_sync.c | 3 ++-
> tests/intel/xe_exec_balancer.c | 9 ++++++---
> tests/intel/xe_exec_basic.c | 2 +-
> tests/intel/xe_exec_compute_mode.c | 3 ++-
> tests/intel/xe_exec_fault_mode.c | 6 ++++--
> tests/intel/xe_exec_reset.c | 14 +++++++++-----
> tests/intel/xe_exec_store.c | 6 ++++--
> tests/intel/xe_exec_threads.c | 9 ++++++---
> tests/intel/xe_guc_pc.c | 3 ++-
> tests/intel/xe_mmap.c | 9 ++++++---
> tests/intel/xe_pm.c | 3 ++-
> tests/intel/xe_pm_residency.c | 3 ++-
> tests/intel/xe_prime_self_import.c | 27 ++++++++++++++++++---------
> tests/intel/xe_vm.c | 21 ++++++++++++++-------
> 21 files changed, 109 insertions(+), 67 deletions(-)
>
> diff --git a/lib/igt_draw.c b/lib/igt_draw.c
> index e37c64fd5..d02125c47 100644
> --- a/lib/igt_draw.c
> +++ b/lib/igt_draw.c
> @@ -791,7 +791,8 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,
> else
> tmp.handle = xe_bo_create(fd, 0,
> ALIGN(tmp.size, xe_get_default_alignment(fd)),
> - visible_vram_if_possible(fd, 0));
> + vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>
> tmp.stride = rect->w * pixel_size;
> tmp.bpp = buf->bpp;
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 39f623585..66f4ccdc4 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -1206,7 +1206,8 @@ static int create_bo_for_fb(struct igt_fb *fb, bool prefer_sysmem)
> igt_assert(err == 0 || err == -EOPNOTSUPP);
> } else if (is_xe_device(fd)) {
> fb->gem_handle = xe_bo_create(fd, 0, fb->size,
> - visible_vram_if_possible(fd, 0));
> + vram_if_possible(fd, 0)
> + | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> } else if (is_vc4_device(fd)) {
> fb->gem_handle = igt_vc4_create_bo(fd, fb->size);
>
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index 4ca371956..05dd6e35c 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -945,7 +945,8 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
>
> ibb->alignment = xe_get_default_alignment(fd);
> size = ALIGN(size, ibb->alignment);
> - ibb->handle = xe_bo_create(fd, 0, size, visible_vram_if_possible(fd, 0));
> + ibb->handle = xe_bo_create(fd, 0, size, vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>
> /* Limit to 48-bit due to MI_* address limitation */
> ibb->gtt_size = 1ull << min_t(uint32_t, xe_va_bits(fd), 48);
> @@ -1404,7 +1405,8 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
> ibb->handle = gem_create(ibb->fd, ibb->size);
> else
> ibb->handle = xe_bo_create(ibb->fd, 0, ibb->size,
> - visible_vram_if_possible(ibb->fd, 0));
> + vram_if_possible(ibb->fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>
> /* Reacquire offset for RELOC and SIMPLE */
> if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE ||
> diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
> index aafd77966..4e21e4c84 100644
> --- a/lib/xe/xe_ioctl.c
> +++ b/lib/xe/xe_ioctl.c
> @@ -226,6 +226,18 @@ void xe_vm_destroy(int fd, uint32_t vm)
> igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_DESTROY, &destroy), 0);
> }
>
> +static bool vram_selected(int fd, uint32_t selected_regions)
> +{
> + uint64_t regions = all_memory_regions(fd) & selected_regions;
> + uint64_t region;
> +
> + xe_for_each_mem_region(fd, regions, region)
> + if (xe_mem_region(fd, region)->mem_class == DRM_XE_MEM_REGION_CLASS_VRAM)
> + return true;
> +
> + return false;
> +}
> +
> uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags,
> uint32_t *handle)
> {
> @@ -236,6 +248,13 @@ uint32_t __xe_bo_create(int fd, uint32_t vm, uint64_t size, uint32_t flags,
> };
> int err;
>
> + /*
> + * In case vram_if_possible returned system_memory,
> + * visible VRAM cannot be requested through flags
> + */
> + if (!vram_selected(fd, flags))
> + create.flags &= ~DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
> +
> err = igt_ioctl(fd, DRM_IOCTL_XE_GEM_CREATE, &create);
> if (err)
> return err;
> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> index 87841e8a3..4329a7e80 100644
> --- a/lib/xe/xe_query.c
> +++ b/lib/xe/xe_query.c
> @@ -424,25 +424,6 @@ uint64_t vram_if_possible(int fd, int gt)
> return vram_memory(fd, gt) ?: system_memory(fd);
> }
>
> -/**
> - * visible_vram_if_possible:
> - * @fd: xe device fd
> - * @gt: gt id
> - *
> - * Returns vram memory bitmask for xe device @fd and @gt id or system memory if
> - * there's no vram memory available for @gt. Also attaches the
> - * DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
> - * when using vram.
> - */
> -uint64_t visible_vram_if_possible(int fd, int gt)
> -{
> - uint64_t regions = all_memory_regions(fd);
> - uint64_t system_memory = regions & 0x1;
> - uint64_t vram = regions & (0x2 << gt);
> -
> - return vram ? vram | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
> -}
> -
> /**
> * xe_hw_engines:
> * @fd: xe device fd
> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> index dcdfa52c2..60eddb126 100644
> --- a/lib/xe/xe_query.h
> +++ b/lib/xe/xe_query.h
> @@ -87,7 +87,6 @@ uint64_t system_memory(int fd);
> uint64_t vram_memory(int fd, int gt);
> uint64_t visible_vram_memory(int fd, int gt);
> uint64_t vram_if_possible(int fd, int gt);
> -uint64_t visible_vram_if_possible(int fd, int gt);
> struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
> struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
> struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region);
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 828938434..270b58bf5 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -220,7 +220,8 @@ xe_spin_create(int fd, const struct igt_spin_factory *opt)
> }
>
> spin->handle = xe_bo_create(fd, spin->vm, bo_size,
> - visible_vram_if_possible(fd, 0));
> + vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> xe_spin = xe_bo_map(fd, spin->handle, bo_size);
> addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
> xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
> @@ -298,8 +299,8 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
>
> vm = xe_vm_create(fd, 0, 0);
>
> - bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, hwe->gt_id));
> + bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, hwe->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> spin = xe_bo_map(fd, bo, 0x1000);
>
> xe_vm_bind_sync(fd, vm, bo, 0, addr, bo_size);
> diff --git a/tests/intel/xe_dma_buf_sync.c b/tests/intel/xe_dma_buf_sync.c
> index ac9d9d767..9318647af 100644
> --- a/tests/intel/xe_dma_buf_sync.c
> +++ b/tests/intel/xe_dma_buf_sync.c
> @@ -120,7 +120,8 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
> xe_get_default_alignment(fd[0]));
> for (i = 0; i < n_bo; ++i) {
> bo[i] = xe_bo_create(fd[0], 0, bo_size,
> - visible_vram_if_possible(fd[0], hwe0->gt_id));
> + vram_if_possible(fd[0], hwe0->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> dma_buf_fd[i] = prime_handle_to_fd(fd[0], bo[i]);
> import_bo[i] = prime_fd_to_handle(fd[1], dma_buf_fd[i]);
>
> diff --git a/tests/intel/xe_exec_balancer.c b/tests/intel/xe_exec_balancer.c
> index da34e117d..388bb6185 100644
> --- a/tests/intel/xe_exec_balancer.c
> +++ b/tests/intel/xe_exec_balancer.c
> @@ -70,7 +70,8 @@ static void test_all_active(int fd, int gt, int class)
> bo_size = sizeof(*data) * num_placements;
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> + bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < num_placements; i++) {
> @@ -224,7 +225,8 @@ test_exec(int fd, int gt, int class, int n_exec_queues, int n_execs,
> }
> memset(data, 0, bo_size);
> } else {
> - bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> + bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
> }
>
> @@ -452,7 +454,8 @@ test_cm(int fd, int gt, int class, int n_exec_queues, int n_execs,
> igt_assert(data);
> }
> } else {
> - bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> + bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> diff --git a/tests/intel/xe_exec_basic.c b/tests/intel/xe_exec_basic.c
> index 841696b68..ca287b2e5 100644
> --- a/tests/intel/xe_exec_basic.c
> +++ b/tests/intel/xe_exec_basic.c
> @@ -136,7 +136,7 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> } else {
> uint32_t bo_flags;
>
> - bo_flags = visible_vram_if_possible(fd, eci->gt_id);
> + bo_flags = vram_if_possible(fd, eci->gt_id) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
> if (flags & DEFER_ALLOC)
> bo_flags |= DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING;
>
> diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c
> index beb962f79..07a27fd29 100644
> --- a/tests/intel/xe_exec_compute_mode.c
> +++ b/tests/intel/xe_exec_compute_mode.c
> @@ -142,7 +142,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> }
> } else {
> bo = xe_bo_create(fd, flags & VM_FOR_BO ? vm : 0,
> - bo_size, visible_vram_if_possible(fd, eci->gt_id));
> + bo_size, vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c
> index 903ad430d..bfd61c4ea 100644
> --- a/tests/intel/xe_exec_fault_mode.c
> +++ b/tests/intel/xe_exec_fault_mode.c
> @@ -153,10 +153,12 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> if (flags & PREFETCH)
> bo = xe_bo_create(fd, 0, bo_size,
> all_memory_regions(fd) |
> - visible_vram_if_possible(fd, 0));
> + vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> else
> bo = xe_bo_create(fd, 0, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> diff --git a/tests/intel/xe_exec_reset.c b/tests/intel/xe_exec_reset.c
> index 704690e83..3affb19ae 100644
> --- a/tests/intel/xe_exec_reset.c
> +++ b/tests/intel/xe_exec_reset.c
> @@ -51,7 +51,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
> xe_get_default_alignment(fd));
>
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> spin = xe_bo_map(fd, bo, bo_size);
>
> exec_queue = xe_exec_queue_create(fd, vm, eci, 0);
> @@ -181,7 +182,8 @@ test_balancer(int fd, int gt, int class, int n_exec_queues, int n_execs,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> + bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, gt) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < n_exec_queues; i++) {
> @@ -368,7 +370,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
> xe_get_default_alignment(fd));
>
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < n_exec_queues; i++) {
> @@ -535,7 +537,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
> xe_get_default_alignment(fd));
>
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
> memset(data, 0, bo_size);
>
> @@ -661,7 +664,8 @@ static void submit_jobs(struct gt_thread_data *t)
> uint32_t bo;
> uint32_t *data;
>
> - bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> + bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
> data[0] = MI_BATCH_BUFFER_END;
>
> diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
> index db685178f..f999a2bb4 100644
> --- a/tests/intel/xe_exec_store.c
> +++ b/tests/intel/xe_exec_store.c
> @@ -82,7 +82,8 @@ static void store(int fd)
>
> hw_engine = xe_hw_engine(fd, 1);
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, hw_engine->gt_id));
> + vram_if_possible(fd, hw_engine->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>
> xe_vm_bind_async(fd, vm, hw_engine->gt_id, bo, 0, addr, bo_size, &sync, 1);
> data = xe_bo_map(fd, bo, bo_size);
> @@ -138,7 +139,8 @@ static void store_all(int fd, int gt, int class)
> xe_get_default_alignment(fd));
>
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, 0));
> + vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
>
> xe_for_each_hw_engine(fd, hwe) {
> diff --git a/tests/intel/xe_exec_threads.c b/tests/intel/xe_exec_threads.c
> index 6ee580c18..d6505f522 100644
> --- a/tests/intel/xe_exec_threads.c
> +++ b/tests/intel/xe_exec_threads.c
> @@ -107,7 +107,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
> }
> } else {
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, gt));
> + vram_if_possible(fd, gt) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> @@ -308,7 +309,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
> }
> } else {
> bo = xe_bo_create(fd, 0, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> @@ -511,7 +513,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
> }
> } else {
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> diff --git a/tests/intel/xe_guc_pc.c b/tests/intel/xe_guc_pc.c
> index 1e29d8905..4234475e0 100644
> --- a/tests/intel/xe_guc_pc.c
> +++ b/tests/intel/xe_guc_pc.c
> @@ -66,7 +66,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
> xe_get_default_alignment(fd));
>
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < n_exec_queues; i++) {
> diff --git a/tests/intel/xe_mmap.c b/tests/intel/xe_mmap.c
> index a805eabda..a4b53ad48 100644
> --- a/tests/intel/xe_mmap.c
> +++ b/tests/intel/xe_mmap.c
> @@ -73,7 +73,8 @@ static void test_bad_flags(int fd)
> uint64_t size = xe_get_default_alignment(fd);
> struct drm_xe_gem_mmap_offset mmo = {
> .handle = xe_bo_create(fd, 0, size,
> - visible_vram_if_possible(fd, 0)),
> + vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM),
> .flags = -1u,
> };
>
> @@ -93,7 +94,8 @@ static void test_bad_extensions(int fd)
> struct xe_user_extension ext;
> struct drm_xe_gem_mmap_offset mmo = {
> .handle = xe_bo_create(fd, 0, size,
> - visible_vram_if_possible(fd, 0)),
> + vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM),
> };
>
> mmo.extensions = to_user_pointer(&ext);
> @@ -114,7 +116,8 @@ static void test_bad_object(int fd)
> uint64_t size = xe_get_default_alignment(fd);
> struct drm_xe_gem_mmap_offset mmo = {
> .handle = xe_bo_create(fd, 0, size,
> - visible_vram_if_possible(fd, 0)),
> + vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM),
> };
>
> mmo.handle = 0xdeadbeef;
> diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c
> index d72e921cf..df85f2c05 100644
> --- a/tests/intel/xe_pm.c
> +++ b/tests/intel/xe_pm.c
> @@ -272,7 +272,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
> rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
>
> bo = xe_bo_create(device.fd_xe, vm, bo_size,
> - visible_vram_if_possible(device.fd_xe, eci->gt_id));
> + vram_if_possible(device.fd_xe, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(device.fd_xe, bo, bo_size);
>
> for (i = 0; i < n_exec_queues; i++) {
> diff --git a/tests/intel/xe_pm_residency.c b/tests/intel/xe_pm_residency.c
> index cc133f5fb..40a1693b8 100644
> --- a/tests/intel/xe_pm_residency.c
> +++ b/tests/intel/xe_pm_residency.c
> @@ -101,7 +101,8 @@ static void exec_load(int fd, struct drm_xe_engine_class_instance *hwe, unsigned
> bo_size = xe_get_default_alignment(fd);
>
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, hwe->gt_id));
> + vram_if_possible(fd, hwe->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
> syncobj = syncobj_create(fd, 0);
>
> diff --git a/tests/intel/xe_prime_self_import.c b/tests/intel/xe_prime_self_import.c
> index bcecd2fcd..df2d8635b 100644
> --- a/tests/intel/xe_prime_self_import.c
> +++ b/tests/intel/xe_prime_self_import.c
> @@ -106,7 +106,8 @@ static void test_with_fd_dup(void)
> fd1 = drm_open_driver(DRIVER_XE);
> fd2 = drm_open_driver(DRIVER_XE);
>
> - handle = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
> + handle = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>
> dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
> gem_close(fd1, handle);
> @@ -139,8 +140,10 @@ static void test_with_two_bos(void)
> fd1 = drm_open_driver(DRIVER_XE);
> fd2 = drm_open_driver(DRIVER_XE);
>
> - handle1 = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
> - handle2 = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
> + handle1 = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + handle2 = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>
> dma_buf_fd = prime_handle_to_fd(fd1, handle1);
> handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
> @@ -176,7 +179,8 @@ static void test_with_one_bo_two_files(void)
> fd2 = drm_open_driver(DRIVER_XE);
>
> handle_orig = xe_bo_create(fd1, 0, BO_SIZE,
> - visible_vram_if_possible(fd1, 0));
> + vram_if_possible(fd1, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> dma_buf_fd1 = prime_handle_to_fd(fd1, handle_orig);
>
> flink_name = gem_flink(fd1, handle_orig);
> @@ -208,7 +212,8 @@ static void test_with_one_bo(void)
> fd1 = drm_open_driver(DRIVER_XE);
> fd2 = drm_open_driver(DRIVER_XE);
>
> - handle = xe_bo_create(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
> + handle = xe_bo_create(fd1, 0, BO_SIZE, vram_if_possible(fd1, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>
> dma_buf_fd = prime_handle_to_fd(fd1, handle);
> handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
> @@ -295,7 +300,8 @@ static void *thread_fn_reimport_vs_close(void *p)
> fds[0] = drm_open_driver(DRIVER_XE);
>
> handle = xe_bo_create(fds[0], 0, BO_SIZE,
> - visible_vram_if_possible(fds[0], 0));
> + vram_if_possible(fds[0], 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>
> fds[1] = prime_handle_to_fd(fds[0], handle);
> pthread_barrier_init(&g_barrier, NULL, num_threads);
> @@ -338,7 +344,8 @@ static void *thread_fn_export_vs_close(void *p)
> igt_until_timeout(g_time_out) {
> /* We want to race gem close against prime export on handle one.*/
> handle = xe_bo_create(fd, 0, 4096,
> - visible_vram_if_possible(fd, 0));
> + vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> if (handle != 1)
> gem_close(fd, handle);
>
> @@ -435,7 +442,8 @@ static void test_llseek_size(void)
> int bufsz = xe_get_default_alignment(fd) << i;
>
> handle = xe_bo_create(fd, 0, bufsz,
> - visible_vram_if_possible(fd, 0));
> + vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> dma_buf_fd = prime_handle_to_fd(fd, handle);
>
> gem_close(fd, handle);
> @@ -464,7 +472,8 @@ static void test_llseek_bad(void)
> fd = drm_open_driver(DRIVER_XE);
>
> handle = xe_bo_create(fd, 0, BO_SIZE,
> - visible_vram_if_possible(fd, 0));
> + vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> dma_buf_fd = prime_handle_to_fd(fd, handle);
>
> gem_close(fd, handle);
> diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
> index 1f71182fe..7e66786d4 100644
> --- a/tests/intel/xe_vm.c
> +++ b/tests/intel/xe_vm.c
> @@ -52,7 +52,8 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
> batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
> batch_bo = xe_bo_create(fd, vm, batch_size,
> - visible_vram_if_possible(fd, 0));
> + vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> batch_map = xe_bo_map(fd, batch_bo, batch_size);
>
> for (i = 0; i < n_dwords; i++) {
> @@ -116,7 +117,8 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
> vms = malloc(sizeof(*vms) * n_addrs);
> igt_assert(vms);
> }
> - bo = xe_bo_create(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> + bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> map = xe_bo_map(fd, bo, bo_size);
> memset(map, 0, bo_size);
>
> @@ -379,7 +381,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
>
> for (i = 0; i < n_bo; ++i) {
> bo[i] = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data[i] = xe_bo_map(fd, bo[i], bo_size);
> }
>
> @@ -558,7 +561,8 @@ test_bind_execqueues_independent(int fd, struct drm_xe_engine_class_instance *ec
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < N_EXEC_QUEUES; i++) {
> @@ -739,7 +743,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
> xe_get_default_alignment(fd));
>
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> data = xe_bo_map(fd, bo, bo_size);
>
> if (flags & BIND_ARRAY_BIND_EXEC_QUEUE_FLAG)
> @@ -937,7 +942,8 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
> xe_visible_vram_size(fd, 0));
>
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> map = xe_bo_map(fd, bo, bo_size);
> }
>
> @@ -1229,7 +1235,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
> igt_assert(map != MAP_FAILED);
> } else {
> bo = xe_bo_create(fd, vm, bo_size,
> - visible_vram_if_possible(fd, eci->gt_id));
> + vram_if_possible(fd, eci->gt_id) |
> + DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> map = xe_bo_map(fd, bo, bo_size);
> }
> memset(map, 0, bo_size);
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2023-10-12 18:46 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-11 14:18 [igt-dev] [RFC v1 00/20] uAPI Alignment - take 2 Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 01/20] drm-uapi/xe: Add documentation for query Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 02/20] drm-uapi/xe: Extend drm_xe_vm_bind_op Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 03/20] drm-uapi/xe: Add uAPI to query micro-controler firmware version Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 04/20] drm-uapi/xe: Document DRM_XE_DEVICE_QUERY_HWCONFIG Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 05/20] drm-uapi/xe: Extend uAPI to query HuC micro-controler firmware version Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 06/20] drm-uapi/xe: Remove useless query config num_params Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 07/20] drm-uapi/xe: Add missing DRM_ prefix in uAPI constants Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 08/20] drm-uapi/xe: Add _FLAG to uAPI constants usable for flags Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 09/20] drm-uapi/xe: Make constant comments visible in kernel doc Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 10/20] fixup! tests/intel/xe_query: Add a test for querying engine cycles Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 11/20] drm-uapi/xe: Remove GT_TYPE_REMOTE Francois Dugast
2023-10-12 18:36 ` Kamil Konieczny
2023-10-11 14:18 ` [igt-dev] [RFC v1 12/20] drm-uapi/xe: Kill VM_MADVISE IOCTL and the atomic tests Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 13/20] drm/xe_query: Remove backward compatibility of vram_visible_size Francois Dugast
2023-10-12 18:39 ` Kamil Konieczny
2023-10-11 14:18 ` [igt-dev] [RFC v1 14/20] xe_ioctl: Converge bo_create to the most used version Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 15/20] xe_ioctl: Rename *xe_bo_create_flags to simply xe_bo_create Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 16/20] xe_query: Add missing include Francois Dugast
2023-10-12 18:44 ` Kamil Konieczny
2023-10-11 14:18 ` [igt-dev] [RFC v1 17/20] xe_query: Kill visible_vram_if_possible Francois Dugast
2023-10-12 18:46 ` Kamil Konieczny
2023-10-11 14:18 ` [igt-dev] [RFC v1 18/20] drm-uapi/xe: Separate bo_create placement from flags Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 19/20] drm-uapi/xe: Align with GuC version type update Francois Dugast
2023-10-11 14:18 ` [igt-dev] [RFC v1 20/20] drm-uapi/xe: Remove unused inaccessible memory region Francois Dugast
2023-10-12 0:20 ` [igt-dev] ✗ Fi.CI.BUILD: failure for uAPI Alignment - take 2 Patchwork
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