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From: Swati Sharma <swati2.sharma@intel.com>
To: igt-dev@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com, Swati Sharma <swati2.sharma@intel.com>
Subject: [PATCH i-g-t 5/5] tests/intel/kms_cdclk: Use igt_get_max_cdclk()
Date: Tue, 18 Feb 2025 03:05:31 +0530	[thread overview]
Message-ID: <20250217213531.402162-6-swati2.sharma@intel.com> (raw)
In-Reply-To: <20250217213531.402162-1-swati2.sharma@intel.com>

Replace hardcoded max cdclk freq with one computed from debugfs.
in igt_get_max_cdclk(). Also, add same condition for
all_outputs subtest.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 tests/intel/kms_cdclk.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tests/intel/kms_cdclk.c b/tests/intel/kms_cdclk.c
index b84ec5cae..22561ab5c 100644
--- a/tests/intel/kms_cdclk.c
+++ b/tests/intel/kms_cdclk.c
@@ -53,7 +53,6 @@ IGT_TEST_DESCRIPTION("Test cdclk features : crawling and squashing");
 #define HDISPLAY_4K	3840
 #define VDISPLAY_4K	2160
 #define VREFRESH	60
-#define MAX_CDCLK_4K	307200
 
 /* Test flags */
 enum {
@@ -227,7 +226,7 @@ static void test_mode_transition(data_t *data, enum pipe pipe, igt_output_t *out
 	igt_info("CD clock frequency %d -> %d\n", cdclk_ref, cdclk_new);
 
 	/* cdclk should bump */
-	if (cdclk_new != MAX_CDCLK_4K)
+	if (cdclk_new != igt_get_max_cdclk(data->drm_fd))
 		igt_assert_lt(cdclk_ref, cdclk_new);
 
 	/* cleanup */
@@ -314,7 +313,8 @@ static void test_mode_transition_on_all_outputs(data_t *data)
 	igt_info("CD clock frequency %d -> %d\n", cdclk_ref, cdclk_new);
 
 	/* cdclk should bump */
-	igt_assert_lt(cdclk_ref, cdclk_new);
+	if (cdclk_new != igt_get_max_cdclk(data->drm_fd))
+		igt_assert_lt(cdclk_ref, cdclk_new);
 
 	do_cleanup_display(display);
 	igt_remove_fb(data->drm_fd, &fb);
-- 
2.25.1


  parent reply	other threads:[~2025-02-17 21:30 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-17 21:35 [PATCH i-g-t 0/5] tests/intel/kms_cdclk: Refactor mode setting and CD clock verification Swati Sharma
2025-02-17 21:35 ` [PATCH i-g-t 1/5] lib/igt_kms: Add func() to read and parse cdclk debugfs Swati Sharma
2025-02-23 12:01   ` Nautiyal, Ankit K
2025-02-17 21:35 ` [PATCH i-g-t 2/5] lib/igt_kms: Add highres() and lowres() func Swati Sharma
2025-02-17 21:35 ` [PATCH i-g-t 3/5] tests/intel/kms_cdclk: Add conditions to filter valid outputs Swati Sharma
2025-02-17 21:35 ` [PATCH i-g-t 4/5] tests/intel/kms_cdclk: Introduce set_mode() Swati Sharma
2025-02-17 21:35 ` Swati Sharma [this message]
2025-02-18  0:06 ` ✓ Xe.CI.BAT: success for tests/intel/kms_cdclk: Refactor mode setting and CD clock verification (rev4) Patchwork
2025-02-18  0:23 ` ✗ i915.CI.BAT: failure " Patchwork
2025-02-18 18:10 ` ✗ Xe.CI.Full: " Patchwork
2025-02-23 12:11 ` [PATCH i-g-t 0/5] tests/intel/kms_cdclk: Refactor mode setting and CD clock verification Nautiyal, Ankit K
  -- strict thread matches above, loose matches on Subject: below --
2025-02-13 11:08 Swati Sharma
2025-02-13 11:08 ` [PATCH i-g-t 5/5] tests/intel/kms_cdclk: Use igt_get_max_cdclk() Swati Sharma
2025-02-17  8:36   ` Nautiyal, Ankit K

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