From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: igt-dev@lists.freedesktop.org, Ashutosh Dixit <ashutosh.dixit@intel.com>
Subject: [PATCH i-g-t CI run 11/14] tests/intel/xe_oa: Enable unprivileged-single-ctx-counters and fix it
Date: Tue, 18 Feb 2025 12:28:09 -0800 [thread overview]
Message-ID: <20250218202812.1679653-12-umesh.nerlige.ramappa@intel.com> (raw)
In-Reply-To: <20250218202812.1679653-1-umesh.nerlige.ramappa@intel.com>
unprivileged-single-ctx-counters was hardcoded for a format size of 256
bytes. Fix it up for generic format size.
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
tests/intel/xe_oa.c | 93 +++++++++++++++++++++++----------------------
1 file changed, 48 insertions(+), 45 deletions(-)
diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index c6c1c2358..ff1b873d5 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -2961,6 +2961,16 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
struct accumulator accumulator = {
.format = fmt
};
+ uint32_t ctx_id_offset, counter_offset, dst_buf_size;
+ struct oa_format format = get_oa_format(fmt);
+
+ if (format.report_hdr_64bit) {
+ ctx_id_offset = 4;
+ counter_offset = 8;
+ } else {
+ ctx_id_offset = 2;
+ counter_offset = 4;
+ }
bops = buf_ops_create(drm_fd);
@@ -2989,25 +2999,29 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
stream_fd = __perf_open(drm_fd, ¶m, false);
set_fd_flags(stream_fd, O_CLOEXEC);
- dst_buf = intel_buf_create(bops, 4096, 1, 8, 64,
+#define FOUR_REPORTS (4 * format.size)
+#define BO_REPORT_OFFSET(_r) (_r * format.size)
+
+#define FOUR_TIMESTAMPS (4 * 8)
+#define BO_TIMESTAMP_OFFSET(_r) (FOUR_REPORTS + (_r * 8))
+
+ dst_buf_size = FOUR_REPORTS + FOUR_TIMESTAMPS;
+ dst_buf = intel_buf_create(bops, dst_buf_size, 1, 8, 64,
I915_TILING_NONE,
I915_COMPRESSION_NONE);
/* Set write domain to cpu briefly to fill the buffer with 80s */
buf_map(drm_fd, dst_buf, true /* write enable */);
- memset(dst_buf->ptr, 0x80, 2048);
- memset((uint8_t *) dst_buf->ptr + 2048, 0, 2048);
+ memset(dst_buf->ptr, 0, dst_buf_size);
+ memset(dst_buf->ptr, 0x80, FOUR_REPORTS);
intel_buf_unmap(dst_buf);
/* Submit an mi-rpc to context0 before measurable work */
-#define BO_TIMESTAMP_OFFSET0 1024
-#define BO_REPORT_OFFSET0 0
-#define BO_REPORT_ID0 0xdeadbeef
emit_stall_timestamp_and_rpc(ibb0,
dst_buf,
- BO_TIMESTAMP_OFFSET0,
- BO_REPORT_OFFSET0,
- BO_REPORT_ID0);
+ BO_TIMESTAMP_OFFSET(0),
+ BO_REPORT_OFFSET(0),
+ 0xdeadbeef);
intel_bb_flush_render(ibb0);
/* Remove intel_buf from ibb0 added implicitly in rendercopy */
@@ -3025,14 +3039,11 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
* all zeroes, since the counters will only increment for the
* context passed to perf open ioctl
*/
-#define BO_TIMESTAMP_OFFSET2 1040
-#define BO_REPORT_OFFSET2 512
-#define BO_REPORT_ID2 0x00c0ffee
emit_stall_timestamp_and_rpc(ibb1,
dst_buf,
- BO_TIMESTAMP_OFFSET2,
- BO_REPORT_OFFSET2,
- BO_REPORT_ID2);
+ BO_TIMESTAMP_OFFSET(2),
+ BO_REPORT_OFFSET(2),
+ 0x00c0ffee);
intel_bb_flush_render(ibb1);
/* Submit two copies on the other context to avoid a false
@@ -3049,28 +3060,22 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
intel_bb_flush_render(ibb1);
/* Submit an mi-rpc to context1 after all work */
-#define BO_TIMESTAMP_OFFSET3 1048
-#define BO_REPORT_OFFSET3 768
-#define BO_REPORT_ID3 0x01c0ffee
emit_stall_timestamp_and_rpc(ibb1,
dst_buf,
- BO_TIMESTAMP_OFFSET3,
- BO_REPORT_OFFSET3,
- BO_REPORT_ID3);
+ BO_TIMESTAMP_OFFSET(3),
+ BO_REPORT_OFFSET(3),
+ 0x01c0ffee);
intel_bb_flush_render(ibb1);
/* Remove intel_buf from ibb1 added implicitly in rendercopy */
intel_bb_remove_intel_buf(ibb1, dst_buf);
/* Submit an mi-rpc to context0 after all measurable work */
-#define BO_TIMESTAMP_OFFSET1 1032
-#define BO_REPORT_OFFSET1 256
-#define BO_REPORT_ID1 0xbeefbeef
emit_stall_timestamp_and_rpc(ibb0,
dst_buf,
- BO_TIMESTAMP_OFFSET1,
- BO_REPORT_OFFSET1,
- BO_REPORT_ID1);
+ BO_TIMESTAMP_OFFSET(1),
+ BO_REPORT_OFFSET(1),
+ 0xbeefbeef);
intel_bb_flush_render(ibb0);
intel_bb_sync(ibb0);
intel_bb_sync(ibb1);
@@ -3090,33 +3095,32 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
report0_32 = dst_buf->ptr;
igt_assert_eq(report0_32[0], 0xdeadbeef);
igt_assert(oa_timestamp(report0_32, fmt));
- ctx0_id = report0_32[2];
+ ctx0_id = report0_32[ctx_id_offset];
igt_debug("MI_RPC(start) CTX ID: %u\n", ctx0_id);
- dump_report(report0_32, 64, "report0_32");
+ dump_report(report0_32, format.size / 4, "report0_32");
- report1_32 = report0_32 + 64;
+ report1_32 = report0_32 + format.size / 4;
igt_assert_eq(report1_32[0], 0xbeefbeef);
igt_assert(oa_timestamp(report1_32, fmt));
- ctx1_id = report1_32[2];
+ ctx1_id = report1_32[ctx_id_offset];
igt_debug("CTX ID1: %u\n", ctx1_id);
- dump_report(report1_32, 64, "report1_32");
+ dump_report(report1_32, format.size / 4, "report1_32");
/* Verify that counters in context1 are all zeroes */
- report2_32 = report0_32 + 128;
+ report2_32 = report1_32 + format.size / 4;
igt_assert_eq(report2_32[0], 0x00c0ffee);
igt_assert(oa_timestamp(report2_32, fmt));
- dump_report(report2_32, 64, "report2_32");
- igt_assert_eq(0, memcmp(&report2_32[4],
- (uint8_t *) dst_buf->ptr + 2048,
- 240));
+ dump_report(report2_32, format.size / 4, "report2_32");
- report3_32 = report0_32 + 192;
+ report3_32 = report2_32 + format.size / 4;
igt_assert_eq(report3_32[0], 0x01c0ffee);
igt_assert(oa_timestamp(report3_32, fmt));
- dump_report(report3_32, 64, "report3_32");
- igt_assert_eq(0, memcmp(&report3_32[4],
- (uint8_t *) dst_buf->ptr + 2048,
- 240));
+ dump_report(report3_32, format.size / 4, "report3_32");
+
+ for (int k = counter_offset; k < format.size / 4; k++) {
+ igt_assert_f(report2_32[k] == 0, "Failed counter %d check\n", k);
+ igt_assert_f(report3_32[k] == 0, "Failed counter %d check\n", k);
+ }
/* Accumulate deltas for counters - A0, A21 and A26 */
memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
@@ -3135,8 +3139,8 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
* the OA report timestamps should be almost identical but
* allow a 500 nanoseconds margin.
*/
- timestamp0_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET0);
- timestamp1_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET1);
+ timestamp0_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET(0));
+ timestamp1_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET(1));
igt_debug("ts_timestamp64 0 = %"PRIu64"\n", timestamp0_64);
igt_debug("ts_timestamp64 1 = %"PRIu64"\n", timestamp1_64);
@@ -4781,7 +4785,6 @@ igt_main
igt_subtest_with_dynamic("unprivileged-single-ctx-counters") {
igt_require_f(render_copy, "no render-copy function\n");
- igt_require(intel_graphics_ver(devid) < IP_VER(20, 0));
__for_one_render_engine(hwe)
test_single_ctx_render_target_writes_a_counter(hwe);
}
--
2.34.1
next prev parent reply other threads:[~2025-02-18 20:28 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-18 20:27 [PATCH i-g-t CI run 00/14] CI run only Umesh Nerlige Ramappa
2025-02-18 20:27 ` [PATCH i-g-t CI run 01/14] tests/intel/xe_oa: Use static for global variables Umesh Nerlige Ramappa
2025-02-18 20:28 ` [PATCH i-g-t CI run 02/14] tests/intel/xe_oa: Drop unused macro Umesh Nerlige Ramappa
2025-02-18 20:28 ` [PATCH i-g-t CI run 03/14] tests/intel/xe_oa: Rename oa_exp_1_millisec to oa_exponent_default Umesh Nerlige Ramappa
2025-02-22 0:24 ` Dixit, Ashutosh
2025-02-22 0:29 ` Umesh Nerlige Ramappa
2025-02-22 0:31 ` Dixit, Ashutosh
2025-02-18 20:28 ` [PATCH i-g-t CI run 04/14] tests/intel/xe_oa: Use default exponent for some tests Umesh Nerlige Ramappa
2025-02-22 0:29 ` Dixit, Ashutosh
2025-02-22 0:37 ` Umesh Nerlige Ramappa
2025-02-22 0:43 ` Dixit, Ashutosh
2025-02-22 0:46 ` Umesh Nerlige Ramappa
2025-02-22 3:39 ` Dixit, Ashutosh
2025-02-18 20:28 ` [PATCH i-g-t CI run 05/14] tests/intel/xe_oa: Use same render copy width and height across tests Umesh Nerlige Ramappa
2025-02-18 20:28 ` [PATCH i-g-t CI run 06/14] tests/intel/xe_oa: Rewrite the polling small buf test Umesh Nerlige Ramappa
2025-02-24 20:11 ` Dixit, Ashutosh
2025-02-24 22:56 ` Umesh Nerlige Ramappa
2025-02-25 0:02 ` Umesh Nerlige Ramappa
2025-02-25 4:30 ` Dixit, Ashutosh
2025-02-18 20:28 ` [PATCH i-g-t CI run 07/14] tests/intel/xe_oa: Simplify the buffer-fill test Umesh Nerlige Ramappa
2025-02-24 21:31 ` Dixit, Ashutosh
2025-02-18 20:28 ` [PATCH i-g-t CI run 08/14] tests/intel/xe_oa: Use default buffer size for non-zero reason Umesh Nerlige Ramappa
2025-02-18 20:28 ` [PATCH i-g-t CI run 09/14] tests/intel/xe_oa: Test oa buffer sizes Umesh Nerlige Ramappa
2025-02-18 20:28 ` [PATCH i-g-t CI run 10/14] tests/intel/xe_oa: Rewrite enable-disable test Umesh Nerlige Ramappa
2025-02-18 20:28 ` Umesh Nerlige Ramappa [this message]
2025-02-18 20:28 ` [PATCH i-g-t CI run 12/14] tests/intel/xe_oa: Fix mmio_trigger_reports testing Umesh Nerlige Ramappa
2025-02-18 20:28 ` [PATCH i-g-t CI run 13/14] tests/intel/xe_oa: Set boundaries for OA exponent test Umesh Nerlige Ramappa
2025-02-18 20:28 ` [PATCH i-g-t CI run 14/14] tests/intel/xe_oa: Try largest buffer size and Xe1 Umesh Nerlige Ramappa
2025-02-18 23:35 ` ✓ Xe.CI.BAT: success for CI run only Patchwork
2025-02-18 23:40 ` ✗ i915.CI.BAT: failure " Patchwork
2025-02-19 18:05 ` ✗ Xe.CI.Full: " Patchwork
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