[igt-dev] [PATCH i-g-t 1/6] tools/intel_watermark: Bump number of planes to 8 for icl

[igt-dev] [PATCH i-g-t 1/6] tools/intel_watermark: Bump number of planes to 8 for icl

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

icl has 8 planes per pipe. Bump the limits to match.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_watermark.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 3fd37441cba7..b61a26f1cd57 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -137,7 +137,9 @@ static int is_hsw_plus(uint32_t d)
 
 static int skl_num_planes(uint32_t d, int pipe)
 {
-	if (IS_GEN10(d) || IS_GEMINILAKE(d))
+	if (IS_GEN11(d))
+		return 8;
+	else if (IS_GEN10(d) || IS_GEMINILAKE(d))
 		return 5;
 	else if (IS_BROXTON(d))
 		return pipe == 2 ? 4 : 5;
@@ -147,7 +149,9 @@ static int skl_num_planes(uint32_t d, int pipe)
 
 static int skl_max_planes(uint32_t d)
 {
-	if (IS_GEN10(d) || IS_GEMINILAKE(d) || IS_BROXTON(d))
+	if (IS_GEN11(d))
+		return 8;
+	else if (IS_GEN10(d) || IS_GEMINILAKE(d) || IS_BROXTON(d))
 		return 5;
 	else
 		return 4;
-- 
2.19.2

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[igt-dev] [PATCH i-g-t 2/6] tools/intel_watermark: More biths for PLANE_BUF_CFG

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On icl PLANE_BUF_CFG fields are 11 bits. Decode them correctly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_watermark.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index b61a26f1cd57..c98b8649cc9c 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -349,20 +349,20 @@ static void skl_wm_dump(void)
 
 		printf("\nstart");
 		for (plane = 0; plane < num_planes; plane++) {
-			start = REG_DECODE1(buf_cfg[pipe][plane], 0, 10);
+			start = REG_DECODE1(buf_cfg[pipe][plane], 0, 11);
 			printf("%10d", start);
 		}
 
 		printf("\n  end");
 		for (plane = 0; plane < num_planes; plane++) {
-			end = REG_DECODE1(buf_cfg[pipe][plane], 16, 10);
+			end = REG_DECODE1(buf_cfg[pipe][plane], 16, 11);
 			printf("%10d", end);
 		}
 
 		printf("\n size");
 		for (plane = 0; plane < num_planes; plane++) {
-			start = REG_DECODE1(buf_cfg[pipe][plane], 0, 10);
-			end =  REG_DECODE1(buf_cfg[pipe][plane], 16, 10);
+			start = REG_DECODE1(buf_cfg[pipe][plane], 0, 11);
+			end =  REG_DECODE1(buf_cfg[pipe][plane], 16, 11);
 			size = end - start + 1;
 			printf("%10d", (end == 0 && size == 1) ? 0 : size);
 		}
-- 
2.19.2

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Re: [igt-dev] [PATCH i-g-t 2/6] tools/intel_watermark: More biths for PLANE_BUF_CFG

[Souza, Jose]

[-- Attachment #1.1: Type: text/plain, Size: 1612 bytes --]

"biths"? I guess this is a typo.

Other than that LGTM:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

On Mon, 2019-01-28 at 22:01 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On icl PLANE_BUF_CFG fields are 11 bits. Decode them correctly.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  tools/intel_watermark.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index b61a26f1cd57..c98b8649cc9c 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -349,20 +349,20 @@ static void skl_wm_dump(void)
>  
>  		printf("\nstart");
>  		for (plane = 0; plane < num_planes; plane++) {
> -			start = REG_DECODE1(buf_cfg[pipe][plane], 0,
> 10);
> +			start = REG_DECODE1(buf_cfg[pipe][plane], 0,
> 11);
>  			printf("%10d", start);
>  		}
>  
>  		printf("\n  end");
>  		for (plane = 0; plane < num_planes; plane++) {
> -			end = REG_DECODE1(buf_cfg[pipe][plane], 16,
> 10);
> +			end = REG_DECODE1(buf_cfg[pipe][plane], 16,
> 11);
>  			printf("%10d", end);
>  		}
>  
>  		printf("\n size");
>  		for (plane = 0; plane < num_planes; plane++) {
> -			start = REG_DECODE1(buf_cfg[pipe][plane], 0,
> 10);
> -			end =  REG_DECODE1(buf_cfg[pipe][plane], 16,
> 10);
> +			start = REG_DECODE1(buf_cfg[pipe][plane], 0,
> 11);
> +			end =  REG_DECODE1(buf_cfg[pipe][plane], 16,
> 11);
>  			size = end - start + 1;
>  			printf("%10d", (end == 0 && size == 1) ? 0 :
> size);
>  		}

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[igt-dev] [PATCH i-g-t 3/6] tools/intel_watermark: Decode wm blocks correctly

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Bump up the width of the wm blocks to 11 bits, which it is on icl.
On earlier platforms it was actually 10 bits but the code decoded
it as 9 bits.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_watermark.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index c98b8649cc9c..97b769250927 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -319,7 +319,7 @@ static void skl_wm_dump(void)
 		for (level = 0; level < num_levels; level++) {
 			printf("%5d", level);
 			for (plane = 0; plane < num_planes; plane++) {
-				blocks = REG_DECODE1(wm[level][pipe][plane], 0, 9);
+				blocks = REG_DECODE1(wm[level][pipe][plane], 0, 11);
 				lines = REG_DECODE1(wm[level][pipe][plane], 14, 5);
 				enable = REG_DECODE1(wm[level][pipe][plane], 31, 1);
 
@@ -334,7 +334,7 @@ static void skl_wm_dump(void)
 
 		printf("TRANS");
 		for (plane = 0; plane < num_planes; plane++) {
-			blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 9);
+			blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 11);
 			lines = REG_DECODE1(wm_trans[pipe][plane], 14, 5);
 			enable = REG_DECODE1(wm_trans[pipe][plane], 31, 1);
 
-- 
2.19.2

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Re: [igt-dev] [PATCH i-g-t 3/6] tools/intel_watermark: Decode wm blocks correctly

[Souza, Jose]

[-- Attachment #1.1: Type: text/plain, Size: 1575 bytes --]

On Mon, 2019-01-28 at 22:01 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Bump up the width of the wm blocks to 11 bits, which it is on icl.
> On earlier platforms it was actually 10 bits but the code decoded
> it as 9 bits.

11? Where did you get that? BSpec says ICL still uses 10 bits and
kernel is also using 10 bits for ICL.
BSpec: 7670

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  tools/intel_watermark.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index c98b8649cc9c..97b769250927 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -319,7 +319,7 @@ static void skl_wm_dump(void)
>  		for (level = 0; level < num_levels; level++) {
>  			printf("%5d", level);
>  			for (plane = 0; plane < num_planes; plane++) {
> -				blocks =
> REG_DECODE1(wm[level][pipe][plane], 0, 9);
> +				blocks =
> REG_DECODE1(wm[level][pipe][plane], 0, 11);
>  				lines =
> REG_DECODE1(wm[level][pipe][plane], 14, 5);
>  				enable =
> REG_DECODE1(wm[level][pipe][plane], 31, 1);
>  
> @@ -334,7 +334,7 @@ static void skl_wm_dump(void)
>  
>  		printf("TRANS");
>  		for (plane = 0; plane < num_planes; plane++) {
> -			blocks = REG_DECODE1(wm_trans[pipe][plane], 0,
> 9);
> +			blocks = REG_DECODE1(wm_trans[pipe][plane], 0,
> 11);
>  			lines = REG_DECODE1(wm_trans[pipe][plane], 14,
> 5);
>  			enable = REG_DECODE1(wm_trans[pipe][plane], 31,
> 1);
>  

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Re: [igt-dev] [PATCH i-g-t 3/6] tools/intel_watermark: Decode wm blocks correctly

[Ville Syrjälä]

On Mon, Jan 28, 2019 at 10:30:18PM +0000, Souza, Jose wrote:
> On Mon, 2019-01-28 at 22:01 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Bump up the width of the wm blocks to 11 bits, which it is on icl.
> > On earlier platforms it was actually 10 bits but the code decoded
> > it as 9 bits.
> 
> 11? Where did you get that? BSpec says ICL still uses 10 bits and
> kernel is also using 10 bits for ICL.
> BSpec: 7670

My bspec clearly says 11. Are you looking at the pre-icl field?

I guess I'll have to go fix the kernel too then.

> 
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  tools/intel_watermark.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> > index c98b8649cc9c..97b769250927 100644
> > --- a/tools/intel_watermark.c
> > +++ b/tools/intel_watermark.c
> > @@ -319,7 +319,7 @@ static void skl_wm_dump(void)
> >  		for (level = 0; level < num_levels; level++) {
> >  			printf("%5d", level);
> >  			for (plane = 0; plane < num_planes; plane++) {
> > -				blocks =
> > REG_DECODE1(wm[level][pipe][plane], 0, 9);
> > +				blocks =
> > REG_DECODE1(wm[level][pipe][plane], 0, 11);
> >  				lines =
> > REG_DECODE1(wm[level][pipe][plane], 14, 5);
> >  				enable =
> > REG_DECODE1(wm[level][pipe][plane], 31, 1);
> >  
> > @@ -334,7 +334,7 @@ static void skl_wm_dump(void)
> >  
> >  		printf("TRANS");
> >  		for (plane = 0; plane < num_planes; plane++) {
> > -			blocks = REG_DECODE1(wm_trans[pipe][plane], 0,
> > 9);
> > +			blocks = REG_DECODE1(wm_trans[pipe][plane], 0,
> > 11);
> >  			lines = REG_DECODE1(wm_trans[pipe][plane], 14,
> > 5);
> >  			enable = REG_DECODE1(wm_trans[pipe][plane], 31,
> > 1);
> >  



-- 
Ville Syrjälä
Intel
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Re: [igt-dev] [PATCH i-g-t 3/6] tools/intel_watermark: Decode wm blocks correctly

[Souza, Jose]

[-- Attachment #1.1: Type: text/plain, Size: 2157 bytes --]

On Tue, 2019-01-29 at 15:23 +0200, Ville Syrjälä wrote:
> On Mon, Jan 28, 2019 at 10:30:18PM +0000, Souza, Jose wrote:
> > On Mon, 2019-01-28 at 22:01 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Bump up the width of the wm blocks to 11 bits, which it is on
> > > icl.
> > > On earlier platforms it was actually 10 bits but the code decoded
> > > it as 9 bits.
> > 
> > 11? Where did you get that? BSpec says ICL still uses 10 bits and
> > kernel is also using 10 bits for ICL.
> > BSpec: 7670
> 
> My bspec clearly says 11. Are you looking at the pre-icl field?

My bad, this is right.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> I guess I'll have to go fix the kernel too then.

Cc me or if you want I can send this patch.

> 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  tools/intel_watermark.c | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> > > index c98b8649cc9c..97b769250927 100644
> > > --- a/tools/intel_watermark.c
> > > +++ b/tools/intel_watermark.c
> > > @@ -319,7 +319,7 @@ static void skl_wm_dump(void)
> > >  		for (level = 0; level < num_levels; level++) {
> > >  			printf("%5d", level);
> > >  			for (plane = 0; plane < num_planes; plane++) {
> > > -				blocks =
> > > REG_DECODE1(wm[level][pipe][plane], 0, 9);
> > > +				blocks =
> > > REG_DECODE1(wm[level][pipe][plane], 0, 11);
> > >  				lines =
> > > REG_DECODE1(wm[level][pipe][plane], 14, 5);
> > >  				enable =
> > > REG_DECODE1(wm[level][pipe][plane], 31, 1);
> > >  
> > > @@ -334,7 +334,7 @@ static void skl_wm_dump(void)
> > >  
> > >  		printf("TRANS");
> > >  		for (plane = 0; plane < num_planes; plane++) {
> > > -			blocks = REG_DECODE1(wm_trans[pipe][plane], 0,
> > > 9);
> > > +			blocks = REG_DECODE1(wm_trans[pipe][plane], 0,
> > > 11);
> > >  			lines = REG_DECODE1(wm_trans[pipe][plane], 14,
> > > 5);
> > >  			enable = REG_DECODE1(wm_trans[pipe][plane], 31,
> > > 1);
> > >  
> 
> 

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[igt-dev] [PATCH i-g-t 4/6] tools/intel_watermark: Show whether each plane is enabled

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

To make it easier to spot errors with watermarks vs. plane
being enabled/disabled indicate which planes are actually
enabled and which are not.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_watermark.c | 40 ++++++++++++++++++++++++++++++++++++++--
 1 file changed, 38 insertions(+), 2 deletions(-)

diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 97b769250927..8405d6489628 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -180,6 +180,20 @@ static const char *skl_wm_linetime_reg_name(int pipe)
 	return reg_name;
 }
 
+static const char *skl_plane_ctl_reg_name(int pipe, int plane)
+{
+	static char reg_name[32];
+
+	if (plane == 0)
+		snprintf(reg_name, sizeof(reg_name), "CUR_CTL_%c",
+			 pipe_name(pipe));
+	else
+		snprintf(reg_name, sizeof(reg_name), "PLANE_CTL_%1d_%c",
+			 plane, pipe_name(pipe));
+
+	return reg_name;
+}
+
 static const char *skl_wm_reg_name(int pipe, int plane, int level)
 {
 	static char reg_name[32];
@@ -231,6 +245,7 @@ static void skl_wm_dump(void)
 	uint32_t wm[num_levels][num_pipes][max_planes];
 	uint32_t wm_trans[num_pipes][max_planes];
 	uint32_t buf_cfg[num_pipes][max_planes];
+	uint32_t plane_ctl[num_pipes][max_planes];
 	uint32_t wm_linetime[num_pipes];
 
 	intel_register_access_init(intel_get_pci_device(), 0, -1);
@@ -243,6 +258,7 @@ static void skl_wm_dump(void)
 		for (plane = 0; plane < num_planes; plane++) {
 			addr =  base_addr +  pipe * 0x1000 + plane * 0x100;
 
+			plane_ctl[pipe][plane] = read_reg(addr + 0x80);
 			wm_trans[pipe][plane] = read_reg(addr + 0x00168);
 			buf_cfg[pipe][plane] = read_reg(addr + 0x0017C);
 			for (level = 0; level < num_levels; level++) {
@@ -259,6 +275,19 @@ static void skl_wm_dump(void)
 	}
 	printf("\n\n");
 
+	for (plane = 0; plane < max_planes; plane++) {
+		for (pipe = 0; pipe < num_pipes; pipe++) {
+			if (plane >= skl_num_planes(devid, pipe))
+				break;
+
+			printf("%18s 0x%08x\t" ,
+			       skl_plane_ctl_reg_name(pipe, plane),
+			       plane_ctl[pipe][plane]);
+		}
+		printf("\n");
+	}
+	printf("\n");
+
 	for (plane = 0; plane < max_planes; plane++) {
 		for (level = 0; level < num_levels; level++) {
 			for (pipe = 0; pipe < num_pipes; pipe++) {
@@ -312,8 +341,15 @@ static void skl_wm_dump(void)
 		printf("LINETIME: %d (%.3f usec)\n", linetime, linetime* 0.125f);
 
 		printf("LEVEL");
-		for (plane = 0; plane < num_planes; plane++)
-			printf("%10s", skl_plane_name(pipe, plane));
+		for (plane = 0; plane < num_planes; plane++) {
+			if (plane == 0)
+				enable = REG_DECODE1(plane_ctl[pipe][plane], 0, 3) ||
+					REG_DECODE1(plane_ctl[pipe][plane], 5, 1);
+			else
+				enable = REG_DECODE1(plane_ctl[pipe][plane], 31, 1);
+			printf("%9s%c", skl_plane_name(pipe, plane),
+			       endis_ast(enable));
+		}
 		printf("\n");
 
 		for (level = 0; level < num_levels; level++) {
-- 
2.19.2

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Re: [igt-dev] [PATCH i-g-t 4/6] tools/intel_watermark: Show whether each plane is enabled

[Souza, Jose]

[-- Attachment #1.1: Type: text/plain, Size: 3523 bytes --]

On Mon, 2019-01-28 at 22:01 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> To make it easier to spot errors with watermarks vs. plane
> being enabled/disabled indicate which planes are actually
> enabled and which are not.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  tools/intel_watermark.c | 40 ++++++++++++++++++++++++++++++++++++++-
> -
>  1 file changed, 38 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 97b769250927..8405d6489628 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -180,6 +180,20 @@ static const char *skl_wm_linetime_reg_name(int
> pipe)
>  	return reg_name;
>  }
>  
> +static const char *skl_plane_ctl_reg_name(int pipe, int plane)
> +{
> +	static char reg_name[32];
> +
> +	if (plane == 0)
> +		snprintf(reg_name, sizeof(reg_name), "CUR_CTL_%c",
> +			 pipe_name(pipe));
> +	else
> +		snprintf(reg_name, sizeof(reg_name),
> "PLANE_CTL_%1d_%c",
> +			 plane, pipe_name(pipe));
> +
> +	return reg_name;
> +}
> +
>  static const char *skl_wm_reg_name(int pipe, int plane, int level)
>  {
>  	static char reg_name[32];
> @@ -231,6 +245,7 @@ static void skl_wm_dump(void)
>  	uint32_t wm[num_levels][num_pipes][max_planes];
>  	uint32_t wm_trans[num_pipes][max_planes];
>  	uint32_t buf_cfg[num_pipes][max_planes];
> +	uint32_t plane_ctl[num_pipes][max_planes];
>  	uint32_t wm_linetime[num_pipes];
>  
>  	intel_register_access_init(intel_get_pci_device(), 0, -1);
> @@ -243,6 +258,7 @@ static void skl_wm_dump(void)
>  		for (plane = 0; plane < num_planes; plane++) {
>  			addr =  base_addr +  pipe * 0x1000 + plane *
> 0x100;
>  
> +			plane_ctl[pipe][plane] = read_reg(addr + 0x80);
>  			wm_trans[pipe][plane] = read_reg(addr +
> 0x00168);
>  			buf_cfg[pipe][plane] = read_reg(addr +
> 0x0017C);
>  			for (level = 0; level < num_levels; level++) {
> @@ -259,6 +275,19 @@ static void skl_wm_dump(void)
>  	}
>  	printf("\n\n");
>  
> +	for (plane = 0; plane < max_planes; plane++) {
> +		for (pipe = 0; pipe < num_pipes; pipe++) {
> +			if (plane >= skl_num_planes(devid, pipe))
> +				break;
> +
> +			printf("%18s 0x%08x\t" ,
> +			       skl_plane_ctl_reg_name(pipe, plane),
> +			       plane_ctl[pipe][plane]);
> +		}
> +		printf("\n");
> +	}
> +	printf("\n");
> +
>  	for (plane = 0; plane < max_planes; plane++) {
>  		for (level = 0; level < num_levels; level++) {
>  			for (pipe = 0; pipe < num_pipes; pipe++) {
> @@ -312,8 +341,15 @@ static void skl_wm_dump(void)
>  		printf("LINETIME: %d (%.3f usec)\n", linetime,
> linetime* 0.125f);
>  
>  		printf("LEVEL");
> -		for (plane = 0; plane < num_planes; plane++)
> -			printf("%10s", skl_plane_name(pipe, plane));
> +		for (plane = 0; plane < num_planes; plane++) {
> +			if (plane == 0)
> +				enable =
> REG_DECODE1(plane_ctl[pipe][plane], 0, 3) ||
> +					REG_DECODE1(plane_ctl[pipe][pla
> ne], 5, 1);

I guess we only enabled ARGB and AND/XOR cursors?! But why not keep it
simple and check for REG_DECODE1(plane_ctl[pipe][plane], 0, 5)?

Other than that LGTM:

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


> +			else
> +				enable =
> REG_DECODE1(plane_ctl[pipe][plane], 31, 1);
> +			printf("%9s%c", skl_plane_name(pipe, plane),
> +			       endis_ast(enable));
> +		}
>  		printf("\n");
>  
>  		for (level = 0; level < num_levels; level++) {

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Re: [igt-dev] [PATCH i-g-t 4/6] tools/intel_watermark: Show whether each plane is enabled

[Ville Syrjälä]

On Mon, Jan 28, 2019 at 10:53:33PM +0000, Souza, Jose wrote:
> On Mon, 2019-01-28 at 22:01 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > To make it easier to spot errors with watermarks vs. plane
> > being enabled/disabled indicate which planes are actually
> > enabled and which are not.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  tools/intel_watermark.c | 40 ++++++++++++++++++++++++++++++++++++++-
> > -
> >  1 file changed, 38 insertions(+), 2 deletions(-)
> > 
> > diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> > index 97b769250927..8405d6489628 100644
> > --- a/tools/intel_watermark.c
> > +++ b/tools/intel_watermark.c
> > @@ -180,6 +180,20 @@ static const char *skl_wm_linetime_reg_name(int
> > pipe)
> >  	return reg_name;
> >  }
> >  
> > +static const char *skl_plane_ctl_reg_name(int pipe, int plane)
> > +{
> > +	static char reg_name[32];
> > +
> > +	if (plane == 0)
> > +		snprintf(reg_name, sizeof(reg_name), "CUR_CTL_%c",
> > +			 pipe_name(pipe));
> > +	else
> > +		snprintf(reg_name, sizeof(reg_name),
> > "PLANE_CTL_%1d_%c",
> > +			 plane, pipe_name(pipe));
> > +
> > +	return reg_name;
> > +}
> > +
> >  static const char *skl_wm_reg_name(int pipe, int plane, int level)
> >  {
> >  	static char reg_name[32];
> > @@ -231,6 +245,7 @@ static void skl_wm_dump(void)
> >  	uint32_t wm[num_levels][num_pipes][max_planes];
> >  	uint32_t wm_trans[num_pipes][max_planes];
> >  	uint32_t buf_cfg[num_pipes][max_planes];
> > +	uint32_t plane_ctl[num_pipes][max_planes];
> >  	uint32_t wm_linetime[num_pipes];
> >  
> >  	intel_register_access_init(intel_get_pci_device(), 0, -1);
> > @@ -243,6 +258,7 @@ static void skl_wm_dump(void)
> >  		for (plane = 0; plane < num_planes; plane++) {
> >  			addr =  base_addr +  pipe * 0x1000 + plane *
> > 0x100;
> >  
> > +			plane_ctl[pipe][plane] = read_reg(addr + 0x80);
> >  			wm_trans[pipe][plane] = read_reg(addr +
> > 0x00168);
> >  			buf_cfg[pipe][plane] = read_reg(addr +
> > 0x0017C);
> >  			for (level = 0; level < num_levels; level++) {
> > @@ -259,6 +275,19 @@ static void skl_wm_dump(void)
> >  	}
> >  	printf("\n\n");
> >  
> > +	for (plane = 0; plane < max_planes; plane++) {
> > +		for (pipe = 0; pipe < num_pipes; pipe++) {
> > +			if (plane >= skl_num_planes(devid, pipe))
> > +				break;
> > +
> > +			printf("%18s 0x%08x\t" ,
> > +			       skl_plane_ctl_reg_name(pipe, plane),
> > +			       plane_ctl[pipe][plane]);
> > +		}
> > +		printf("\n");
> > +	}
> > +	printf("\n");
> > +
> >  	for (plane = 0; plane < max_planes; plane++) {
> >  		for (level = 0; level < num_levels; level++) {
> >  			for (pipe = 0; pipe < num_pipes; pipe++) {
> > @@ -312,8 +341,15 @@ static void skl_wm_dump(void)
> >  		printf("LINETIME: %d (%.3f usec)\n", linetime,
> > linetime* 0.125f);
> >  
> >  		printf("LEVEL");
> > -		for (plane = 0; plane < num_planes; plane++)
> > -			printf("%10s", skl_plane_name(pipe, plane));
> > +		for (plane = 0; plane < num_planes; plane++) {
> > +			if (plane == 0)
> > +				enable =
> > REG_DECODE1(plane_ctl[pipe][plane], 0, 3) ||
> > +					REG_DECODE1(plane_ctl[pipe][pla
> > ne], 5, 1);
> 
> I guess we only enabled ARGB and AND/XOR cursors?! But why not keep it
> simple and check for REG_DECODE1(plane_ctl[pipe][plane], 0, 5)?

Because bits 3 and 4 aren't part of the cursor format. Well, apparently
they are now even though they are always 0. I wonder when that was
respecified... apparently for HSW. OK, been like that for a while then
:)

> 
> Other than that LGTM:
> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> 
> 
> > +			else
> > +				enable =
> > REG_DECODE1(plane_ctl[pipe][plane], 31, 1);
> > +			printf("%9s%c", skl_plane_name(pipe, plane),
> > +			       endis_ast(enable));
> > +		}
> >  		printf("\n");
> >  
> >  		for (level = 0; level < num_levels; level++) {



-- 
Ville Syrjälä
Intel
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[igt-dev] [PATCH i-g-t 5/6] tools/intel_watermark: Dump NV12_BUF_CFG

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On pre-icl we have two registers for the DDB allocations
for NV12. Dump the second set of allocations as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_watermark.c | 56 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 8405d6489628..6a47b33c438c 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -235,6 +235,16 @@ static const char *skl_buf_cfg_reg_name(int pipe, int plane)
 	return reg_name;
 }
 
+static const char *skl_nv12_buf_cfg_reg_name(int pipe, int plane)
+{
+	static char reg_name[32];
+
+	snprintf(reg_name, sizeof(reg_name), "PLANE_NV12_BUF_CFG_%1d_%c",
+		 plane, pipe_name(pipe));
+
+	return reg_name;
+}
+
 static void skl_wm_dump(void)
 {
 	int pipe, plane, level;
@@ -245,6 +255,7 @@ static void skl_wm_dump(void)
 	uint32_t wm[num_levels][num_pipes][max_planes];
 	uint32_t wm_trans[num_pipes][max_planes];
 	uint32_t buf_cfg[num_pipes][max_planes];
+	uint32_t nv12_buf_cfg[num_pipes][max_planes];
 	uint32_t plane_ctl[num_pipes][max_planes];
 	uint32_t wm_linetime[num_pipes];
 
@@ -261,6 +272,10 @@ static void skl_wm_dump(void)
 			plane_ctl[pipe][plane] = read_reg(addr + 0x80);
 			wm_trans[pipe][plane] = read_reg(addr + 0x00168);
 			buf_cfg[pipe][plane] = read_reg(addr + 0x0017C);
+			if (plane != 0 && intel_gen(devid) < 11)
+				nv12_buf_cfg[pipe][plane] = read_reg(addr + 0x00178);
+			else
+				nv12_buf_cfg[pipe][plane] = 0;
 			for (level = 0; level < num_levels; level++) {
 				wm_offset = addr + 0x00140 + level * 0x4;
 				wm[level][pipe][plane] = read_reg(wm_offset);
@@ -326,6 +341,22 @@ static void skl_wm_dump(void)
 			       buf_cfg[pipe][plane]);
 		}
 		printf("\n");
+
+		if (intel_gen(devid) >= 11)
+			continue;
+
+		if (plane == 0)
+			continue;
+
+		for (pipe = 0; pipe < num_pipes; pipe++) {
+			if (plane >= skl_num_planes(devid, pipe))
+				break;
+
+			printf("%18s 0x%08x\t",
+			       skl_nv12_buf_cfg_reg_name(pipe, plane),
+			       nv12_buf_cfg[pipe][plane]);
+		}
+		printf("\n");
 	}
 	printf("\n");
 
@@ -402,6 +433,31 @@ static void skl_wm_dump(void)
 			size = end - start + 1;
 			printf("%10d", (end == 0 && size == 1) ? 0 : size);
 		}
+		printf("\n");
+
+		if (intel_gen(devid) < 11) {
+			printf("\nNV12 DDB allocation:");
+
+			printf("\nstart");
+			for (plane = 0; plane < num_planes; plane++) {
+				start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 11);
+				printf("%10d", start);
+			}
+
+			printf("\n  end");
+			for (plane = 0; plane < num_planes; plane++) {
+				end = REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 11);
+				printf("%10d", end);
+			}
+
+			printf("\n size");
+			for (plane = 0; plane < num_planes; plane++) {
+				start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 11);
+				end =  REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 11);
+				size = end - start + 1;
+				printf("%10d", (end == 0 && size == 1) ? 0 : size);
+			}
+		}
 
 		printf("\n\n\n");
 	}
-- 
2.19.2

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Re: [igt-dev] [PATCH i-g-t 5/6] tools/intel_watermark: Dump NV12_BUF_CFG

[Souza, Jose]

[-- Attachment #1.1: Type: text/plain, Size: 3541 bytes --]

On Mon, 2019-01-28 at 22:01 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On pre-icl we have two registers for the DDB allocations
> for NV12. Dump the second set of allocations as well.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  tools/intel_watermark.c | 56
> +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 56 insertions(+)
> 
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 8405d6489628..6a47b33c438c 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -235,6 +235,16 @@ static const char *skl_buf_cfg_reg_name(int
> pipe, int plane)
>  	return reg_name;
>  }
>  
> +static const char *skl_nv12_buf_cfg_reg_name(int pipe, int plane)
> +{
> +	static char reg_name[32];
> +
> +	snprintf(reg_name, sizeof(reg_name),
> "PLANE_NV12_BUF_CFG_%1d_%c",
> +		 plane, pipe_name(pipe));
> +
> +	return reg_name;
> +}
> +
>  static void skl_wm_dump(void)
>  {
>  	int pipe, plane, level;
> @@ -245,6 +255,7 @@ static void skl_wm_dump(void)
>  	uint32_t wm[num_levels][num_pipes][max_planes];
>  	uint32_t wm_trans[num_pipes][max_planes];
>  	uint32_t buf_cfg[num_pipes][max_planes];
> +	uint32_t nv12_buf_cfg[num_pipes][max_planes];
>  	uint32_t plane_ctl[num_pipes][max_planes];
>  	uint32_t wm_linetime[num_pipes];
>  
> @@ -261,6 +272,10 @@ static void skl_wm_dump(void)
>  			plane_ctl[pipe][plane] = read_reg(addr + 0x80);
>  			wm_trans[pipe][plane] = read_reg(addr +
> 0x00168);
>  			buf_cfg[pipe][plane] = read_reg(addr +
> 0x0017C);
> +			if (plane != 0 && intel_gen(devid) < 11)
> +				nv12_buf_cfg[pipe][plane] =
> read_reg(addr + 0x00178);
> +			else
> +				nv12_buf_cfg[pipe][plane] = 0;
>  			for (level = 0; level < num_levels; level++) {
>  				wm_offset = addr + 0x00140 + level *
> 0x4;
>  				wm[level][pipe][plane] =
> read_reg(wm_offset);
> @@ -326,6 +341,22 @@ static void skl_wm_dump(void)
>  			       buf_cfg[pipe][plane]);
>  		}
>  		printf("\n");
> +
> +		if (intel_gen(devid) >= 11)
> +			continue;
> +
> +		if (plane == 0)
> +			continue;
> +
> +		for (pipe = 0; pipe < num_pipes; pipe++) {
> +			if (plane >= skl_num_planes(devid, pipe))
> +				break;
> +
> +			printf("%18s 0x%08x\t",
> +			       skl_nv12_buf_cfg_reg_name(pipe, plane),
> +			       nv12_buf_cfg[pipe][plane]);
> +		}
> +		printf("\n");
>  	}
>  	printf("\n");
>  
> @@ -402,6 +433,31 @@ static void skl_wm_dump(void)
>  			size = end - start + 1;
>  			printf("%10d", (end == 0 && size == 1) ? 0 :
> size);
>  		}
> +		printf("\n");
> +
> +		if (intel_gen(devid) < 11) {
> +			printf("\nNV12 DDB allocation:");
> +
> +			printf("\nstart");
> +			for (plane = 0; plane < num_planes; plane++) {
> +				start =
> REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 11);
> +				printf("%10d", start);
> +			}
> +
> +			printf("\n  end");
> +			for (plane = 0; plane < num_planes; plane++) {
> +				end =
> REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 11);
> +				printf("%10d", end);
> +			}
> +
> +			printf("\n size");
> +			for (plane = 0; plane < num_planes; plane++) {
> +				start =
> REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 11);
> +				end
> =  REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 11);
> +				size = end - start + 1;
> +				printf("%10d", (end == 0 && size == 1)
> ? 0 : size);
> +			}
> +		}
>  
>  		printf("\n\n\n");
>  	}

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[igt-dev] [PATCH i-g-t 6/6] tools/intel_watermark: Clean up the platform checks in the ilk+ code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the old hand rolled platform check funcs with somehting
more standard.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_watermark.c | 42 ++++++++++++++++-------------------------
 1 file changed, 16 insertions(+), 26 deletions(-)

diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 6a47b33c438c..e71c3d9cff6d 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -125,16 +125,6 @@ static char endis_ast(bool enabled)
 	return enabled ? '*' : ' ';
 }
 
-static int is_gen7_plus(uint32_t d)
-{
-	return !(IS_GEN5(d) || IS_GEN6(d));
-}
-
-static int is_hsw_plus(uint32_t d)
-{
-	return !(IS_GEN5(d) || IS_GEN6(d) || IS_IVYBRIDGE(d));
-}
-
 static int skl_num_planes(uint32_t d, int pipe)
 {
 	if (IS_GEN11(d))
@@ -476,14 +466,14 @@ static void ilk_wm_dump(void)
 	uint32_t wm_lp[3];
 	uint32_t wm_lp_spr[3];
 	uint32_t arb_ctl, arb_ctl2, wm_misc = 0;
-	int num_pipes = is_gen7_plus(devid) ? 3 : 2;
+	int num_pipes = intel_gen(devid) >= 7 ? 3 : 2;
 	struct ilk_wm wm = {};
 
 	intel_register_access_init(intel_get_pci_device(), 0, -1);
 
 	for (i = 0; i < num_pipes; i++) {
 		dspcntr[i] = read_reg(0x70180 + i * 0x1000);
-		if (is_gen7_plus(devid))
+		if (intel_gen(devid) >= 7)
 			spcntr[i] = read_reg(0x70280 + i * 0x1000);
 		else
 			spcntr[i] = read_reg(0x72180 + i * 0x1000);
@@ -494,7 +484,7 @@ static void ilk_wm_dump(void)
 	if (num_pipes == 3)
 		wm_pipe[2] = read_reg(0x45200);
 
-	if (is_hsw_plus(devid)) {
+	if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
 		wm_linetime[0] = read_reg(0x45270);
 		wm_linetime[1] = read_reg(0x45274);
 		wm_linetime[2] = read_reg(0x45278);
@@ -505,21 +495,21 @@ static void ilk_wm_dump(void)
 	wm_lp[2] = read_reg(0x45110);
 
 	wm_lp_spr[0] = read_reg(0x45120);
-	if (is_gen7_plus(devid)) {
+	if (intel_gen(devid) >= 7) {
 		wm_lp_spr[1] = read_reg(0x45124);
 		wm_lp_spr[2] = read_reg(0x45128);
 	}
 
 	arb_ctl = read_reg(0x45000);
 	arb_ctl2 = read_reg(0x45004);
-	if (is_hsw_plus(devid))
+	if (IS_BROADWELL(devid) || IS_HASWELL(devid))
 		wm_misc = read_reg(0x45260);
 
 	intel_register_access_fini();
 
 	for (i = 0; i < num_pipes; i++)
 		printf("    WM_PIPE_%c = 0x%08x\n", pipe_name(i), wm_pipe[i]);
-	if (is_hsw_plus(devid)) {
+	if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
 		for (i = 0; i < num_pipes; i++)
 			printf("WM_LINETIME_%c = 0x%08x\n", pipe_name(i), wm_linetime[i]);
 	}
@@ -527,13 +517,13 @@ static void ilk_wm_dump(void)
 	printf("       WM_LP2 = 0x%08x\n", wm_lp[1]);
 	printf("       WM_LP3 = 0x%08x\n", wm_lp[2]);
 	printf("   WM_LP1_SPR = 0x%08x\n", wm_lp_spr[0]);
-	if (is_gen7_plus(devid)) {
+	if (intel_gen(devid) >= 7) {
 		printf("   WM_LP2_SPR = 0x%08x\n", wm_lp_spr[1]);
 		printf("   WM_LP3_SPR = 0x%08x\n", wm_lp_spr[2]);
 	}
 	printf("      ARB_CTL = 0x%08x\n", arb_ctl);
 	printf("     ARB_CTL2 = 0x%08x\n", arb_ctl2);
-	if (is_hsw_plus(devid))
+	if (IS_BROADWELL(devid) || IS_HASWELL(devid))
 		printf("      WM_MISC = 0x%08x\n", wm_misc);
 
 	for (i = 0 ; i < num_pipes; i++) {
@@ -541,7 +531,7 @@ static void ilk_wm_dump(void)
 		wm.pipe[i].sprite = REG_DECODE1(wm_pipe[i], 8, 8);
 		wm.pipe[i].cursor = REG_DECODE1(wm_pipe[i], 0, 6);
 
-		if (is_hsw_plus(devid)) {
+		if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
 			wm.linetime[i].linetime = REG_DECODE1(wm_linetime[i], 0, 9);
 			wm.linetime[i].ips = REG_DECODE1(wm_linetime[i], 16, 9);
 		}
@@ -556,15 +546,15 @@ static void ilk_wm_dump(void)
 	for (i = 0; i < 3; i++) {
 		wm.lp[i].enabled = REG_DECODE1(wm_lp[i], 31, 1);
 		wm.lp[i].latency = REG_DECODE1(wm_lp[i], 24, 7);
-		if (IS_GEN8(devid))
+		if (IS_BROADWELL(devid))
 			wm.lp[i].fbc = REG_DECODE1(wm_lp[i], 19, 5);
 		else
 			wm.lp[i].fbc = REG_DECODE1(wm_lp[i], 20, 4);
 		wm.lp[i].primary = REG_DECODE1(wm_lp[i], 8, 11);
 		wm.lp[i].cursor = REG_DECODE1(wm_lp[i], 0, 8);
 
-		if (i == 0 || is_gen7_plus(devid)) {
-			if (!is_gen7_plus(devid))
+		if (i == 0 || intel_gen(devid) >= 7) {
+			if (intel_gen(devid) < 7)
 				wm.lp[i].sprite_enabled = REG_DECODE1(wm_lp_spr[i], 31, 1);
 			wm.lp[i].sprite = REG_DECODE1(wm_lp_spr[i], 0, 11);
 		}
@@ -574,7 +564,7 @@ static void ilk_wm_dump(void)
 		printf("WM_PIPE_%c: primary=%d, cursor=%d, sprite=%d\n",
 		       pipe_name(i), wm.pipe[i].primary, wm.pipe[i].cursor, wm.pipe[i].sprite);
 	}
-	if (is_hsw_plus(devid)) {
+	if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
 		for (i = 0; i < num_pipes; i++) {
 			printf("WM_LINETIME_%c: line time=%d (%.3f usec), ips line time=%d (%.3f usec)\n",
 			       pipe_name(i),
@@ -582,7 +572,7 @@ static void ilk_wm_dump(void)
 			       wm.linetime[i].ips, wm.linetime[i].ips * 0.125f);
 		}
 	}
-	if (is_gen7_plus(devid)) {
+	if (intel_gen(devid) >= 7) {
 		for (i = 0; i < 3; i++) {
 			printf("WM_LP%d: %s, latency=%d, fbc=%d, primary=%d, cursor=%d, sprite=%d\n",
 			       i + 1, endis(wm.lp[i].enabled), wm.lp[i].latency, wm.lp[i].fbc,
@@ -607,10 +597,10 @@ static void ilk_wm_dump(void)
 			printf("Sprite %c trickle feed = %s\n",
 			       pipe_name(i), endis(!wm.pipe[i].sprite_trickle_feed_dis));
 	}
-	if (is_hsw_plus(devid)) {
+	if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
 		printf("DDB partitioning = %s\n",
 		       REG_DECODE1(wm_misc, 0, 1) ? "5/6" : "1/2");
-	} else if (is_gen7_plus(devid)) {
+	} else if (intel_gen(devid) >= 7) {
 		printf("DDB partitioning = %s\n",
 		       REG_DECODE1(arb_ctl2, 6, 1) ? "5/6" : "1/2");
 	}
-- 
2.19.2

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Re: [igt-dev] [PATCH i-g-t 6/6] tools/intel_watermark: Clean up the platform checks in the ilk+ code

[Souza, Jose]

[-- Attachment #1.1: Type: text/plain, Size: 6114 bytes --]

On Mon, 2019-01-28 at 22:01 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Replace the old hand rolled platform check funcs with somehting
> more standard.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  tools/intel_watermark.c | 42 ++++++++++++++++-----------------------
> --
>  1 file changed, 16 insertions(+), 26 deletions(-)
> 
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 6a47b33c438c..e71c3d9cff6d 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -125,16 +125,6 @@ static char endis_ast(bool enabled)
>  	return enabled ? '*' : ' ';
>  }
>  
> -static int is_gen7_plus(uint32_t d)
> -{
> -	return !(IS_GEN5(d) || IS_GEN6(d));
> -}
> -
> -static int is_hsw_plus(uint32_t d)
> -{
> -	return !(IS_GEN5(d) || IS_GEN6(d) || IS_IVYBRIDGE(d));
> -}
> -
>  static int skl_num_planes(uint32_t d, int pipe)
>  {
>  	if (IS_GEN11(d))
> @@ -476,14 +466,14 @@ static void ilk_wm_dump(void)
>  	uint32_t wm_lp[3];
>  	uint32_t wm_lp_spr[3];
>  	uint32_t arb_ctl, arb_ctl2, wm_misc = 0;
> -	int num_pipes = is_gen7_plus(devid) ? 3 : 2;
> +	int num_pipes = intel_gen(devid) >= 7 ? 3 : 2;
>  	struct ilk_wm wm = {};
>  
>  	intel_register_access_init(intel_get_pci_device(), 0, -1);
>  
>  	for (i = 0; i < num_pipes; i++) {
>  		dspcntr[i] = read_reg(0x70180 + i * 0x1000);
> -		if (is_gen7_plus(devid))
> +		if (intel_gen(devid) >= 7)
>  			spcntr[i] = read_reg(0x70280 + i * 0x1000);
>  		else
>  			spcntr[i] = read_reg(0x72180 + i * 0x1000);
> @@ -494,7 +484,7 @@ static void ilk_wm_dump(void)
>  	if (num_pipes == 3)
>  		wm_pipe[2] = read_reg(0x45200);
>  
> -	if (is_hsw_plus(devid)) {
> +	if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
>  		wm_linetime[0] = read_reg(0x45270);
>  		wm_linetime[1] = read_reg(0x45274);
>  		wm_linetime[2] = read_reg(0x45278);
> @@ -505,21 +495,21 @@ static void ilk_wm_dump(void)
>  	wm_lp[2] = read_reg(0x45110);
>  
>  	wm_lp_spr[0] = read_reg(0x45120);
> -	if (is_gen7_plus(devid)) {
> +	if (intel_gen(devid) >= 7) {
>  		wm_lp_spr[1] = read_reg(0x45124);
>  		wm_lp_spr[2] = read_reg(0x45128);
>  	}
>  
>  	arb_ctl = read_reg(0x45000);
>  	arb_ctl2 = read_reg(0x45004);
> -	if (is_hsw_plus(devid))
> +	if (IS_BROADWELL(devid) || IS_HASWELL(devid))
>  		wm_misc = read_reg(0x45260);
>  
>  	intel_register_access_fini();
>  
>  	for (i = 0; i < num_pipes; i++)
>  		printf("    WM_PIPE_%c = 0x%08x\n", pipe_name(i),
> wm_pipe[i]);
> -	if (is_hsw_plus(devid)) {
> +	if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
>  		for (i = 0; i < num_pipes; i++)
>  			printf("WM_LINETIME_%c = 0x%08x\n",
> pipe_name(i), wm_linetime[i]);
>  	}
> @@ -527,13 +517,13 @@ static void ilk_wm_dump(void)
>  	printf("       WM_LP2 = 0x%08x\n", wm_lp[1]);
>  	printf("       WM_LP3 = 0x%08x\n", wm_lp[2]);
>  	printf("   WM_LP1_SPR = 0x%08x\n", wm_lp_spr[0]);
> -	if (is_gen7_plus(devid)) {
> +	if (intel_gen(devid) >= 7) {
>  		printf("   WM_LP2_SPR = 0x%08x\n", wm_lp_spr[1]);
>  		printf("   WM_LP3_SPR = 0x%08x\n", wm_lp_spr[2]);
>  	}
>  	printf("      ARB_CTL = 0x%08x\n", arb_ctl);
>  	printf("     ARB_CTL2 = 0x%08x\n", arb_ctl2);
> -	if (is_hsw_plus(devid))
> +	if (IS_BROADWELL(devid) || IS_HASWELL(devid))
>  		printf("      WM_MISC = 0x%08x\n", wm_misc);
>  
>  	for (i = 0 ; i < num_pipes; i++) {
> @@ -541,7 +531,7 @@ static void ilk_wm_dump(void)
>  		wm.pipe[i].sprite = REG_DECODE1(wm_pipe[i], 8, 8);
>  		wm.pipe[i].cursor = REG_DECODE1(wm_pipe[i], 0, 6);
>  
> -		if (is_hsw_plus(devid)) {
> +		if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
>  			wm.linetime[i].linetime =
> REG_DECODE1(wm_linetime[i], 0, 9);
>  			wm.linetime[i].ips =
> REG_DECODE1(wm_linetime[i], 16, 9);
>  		}
> @@ -556,15 +546,15 @@ static void ilk_wm_dump(void)
>  	for (i = 0; i < 3; i++) {
>  		wm.lp[i].enabled = REG_DECODE1(wm_lp[i], 31, 1);
>  		wm.lp[i].latency = REG_DECODE1(wm_lp[i], 24, 7);
> -		if (IS_GEN8(devid))
> +		if (IS_BROADWELL(devid))
>  			wm.lp[i].fbc = REG_DECODE1(wm_lp[i], 19, 5);
>  		else
>  			wm.lp[i].fbc = REG_DECODE1(wm_lp[i], 20, 4);
>  		wm.lp[i].primary = REG_DECODE1(wm_lp[i], 8, 11);
>  		wm.lp[i].cursor = REG_DECODE1(wm_lp[i], 0, 8);
>  
> -		if (i == 0 || is_gen7_plus(devid)) {
> -			if (!is_gen7_plus(devid))
> +		if (i == 0 || intel_gen(devid) >= 7) {
> +			if (intel_gen(devid) < 7)
>  				wm.lp[i].sprite_enabled =
> REG_DECODE1(wm_lp_spr[i], 31, 1);
>  			wm.lp[i].sprite = REG_DECODE1(wm_lp_spr[i], 0,
> 11);
>  		}
> @@ -574,7 +564,7 @@ static void ilk_wm_dump(void)
>  		printf("WM_PIPE_%c: primary=%d, cursor=%d,
> sprite=%d\n",
>  		       pipe_name(i), wm.pipe[i].primary,
> wm.pipe[i].cursor, wm.pipe[i].sprite);
>  	}
> -	if (is_hsw_plus(devid)) {
> +	if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
>  		for (i = 0; i < num_pipes; i++) {
>  			printf("WM_LINETIME_%c: line time=%d (%.3f
> usec), ips line time=%d (%.3f usec)\n",
>  			       pipe_name(i),
> @@ -582,7 +572,7 @@ static void ilk_wm_dump(void)
>  			       wm.linetime[i].ips, wm.linetime[i].ips *
> 0.125f);
>  		}
>  	}
> -	if (is_gen7_plus(devid)) {
> +	if (intel_gen(devid) >= 7) {
>  		for (i = 0; i < 3; i++) {
>  			printf("WM_LP%d: %s, latency=%d, fbc=%d,
> primary=%d, cursor=%d, sprite=%d\n",
>  			       i + 1, endis(wm.lp[i].enabled),
> wm.lp[i].latency, wm.lp[i].fbc,
> @@ -607,10 +597,10 @@ static void ilk_wm_dump(void)
>  			printf("Sprite %c trickle feed = %s\n",
>  			       pipe_name(i),
> endis(!wm.pipe[i].sprite_trickle_feed_dis));
>  	}
> -	if (is_hsw_plus(devid)) {
> +	if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
>  		printf("DDB partitioning = %s\n",
>  		       REG_DECODE1(wm_misc, 0, 1) ? "5/6" : "1/2");
> -	} else if (is_gen7_plus(devid)) {
> +	} else if (intel_gen(devid) >= 7) {
>  		printf("DDB partitioning = %s\n",
>  		       REG_DECODE1(arb_ctl2, 6, 1) ? "5/6" : "1/2");
>  	}

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[igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/6] tools/intel_watermark: Bump number of planes to 8 for icl

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/6] tools/intel_watermark: Bump number of planes to 8 for icl
URL   : https://patchwork.freedesktop.org/series/55862/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5498 -> IGTPW_2310
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/55862/revisions/1/mbox/

Known issues
------------

  Here are the changes found in IGTPW_2310 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@kms_busy@basic-flip-b:
    - fi-gdg-551:         PASS -> FAIL [fdo#103182]

  * igt@kms_flip@basic-flip-vs-dpms:
    - fi-skl-6700hq:      PASS -> DMESG-WARN [fdo#105998]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  
#### Possible fixes ####

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         INCOMPLETE [fdo#103927] -> PASS

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       FAIL [fdo#109485] -> PASS

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  * igt@pm_rpm@basic-pci-d3-state:
    - fi-byt-j1900:       {SKIP} [fdo#109271] -> PASS

  * igt@pm_rpm@basic-rte:
    - fi-byt-j1900:       FAIL [fdo#108800] -> PASS

  
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485


Participating hosts (44 -> 41)
------------------------------

  Missing    (3): fi-kbl-soraka fi-ilk-m540 fi-bsw-cyan 


Build changes
-------------

    * IGT: IGT_4796 -> IGTPW_2310

  CI_DRM_5498: bebd74b74f0c62ff61036fc2d349fc470502b565 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2310: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2310/
  IGT_4796: d1bd9c6ad6f3482bbccf4aa6417dd449e9efbe39 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2310/
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Re: [igt-dev] [PATCH i-g-t 1/6] tools/intel_watermark: Bump number of planes to 8 for icl

[Souza, Jose]

[-- Attachment #1.1: Type: text/plain, Size: 1239 bytes --]

On Mon, 2019-01-28 at 22:01 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> icl has 8 planes per pipe. Bump the limits to match.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  tools/intel_watermark.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 3fd37441cba7..b61a26f1cd57 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -137,7 +137,9 @@ static int is_hsw_plus(uint32_t d)
>  
>  static int skl_num_planes(uint32_t d, int pipe)
>  {
> -	if (IS_GEN10(d) || IS_GEMINILAKE(d))
> +	if (IS_GEN11(d))
> +		return 8;
> +	else if (IS_GEN10(d) || IS_GEMINILAKE(d))
>  		return 5;
>  	else if (IS_BROXTON(d))
>  		return pipe == 2 ? 4 : 5;
> @@ -147,7 +149,9 @@ static int skl_num_planes(uint32_t d, int pipe)
>  
>  static int skl_max_planes(uint32_t d)
>  {
> -	if (IS_GEN10(d) || IS_GEMINILAKE(d) || IS_BROXTON(d))
> +	if (IS_GEN11(d))
> +		return 8;
> +	else if (IS_GEN10(d) || IS_GEMINILAKE(d) || IS_BROXTON(d))
>  		return 5;
>  	else
>  		return 4;

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[igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/6] tools/intel_watermark: Bump number of planes to 8 for icl

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/6] tools/intel_watermark: Bump number of planes to 8 for icl
URL   : https://patchwork.freedesktop.org/series/55862/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5498_full -> IGTPW_2310_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with IGTPW_2310_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_2310_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/55862/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_2310_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_vblank@crtc-id:
    - shard-snb:          {SKIP} [fdo#109271] -> FAIL

  
Known issues
------------

  Here are the changes found in IGTPW_2310_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@reset-stress:
    - shard-kbl:          PASS -> INCOMPLETE [fdo#103665]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-apl:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_cursor_crc@cursor-256x256-onscreen:
    - shard-kbl:          PASS -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-256x256-random:
    - shard-glk:          PASS -> FAIL [fdo#103232] +9

  * igt@kms_cursor_crc@cursor-256x256-suspend:
    - shard-apl:          PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_cursor_crc@cursor-256x85-onscreen:
    - shard-apl:          PASS -> FAIL [fdo#103232] +3

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-hsw:          PASS -> DMESG-FAIL [fdo#102614] / [fdo#103060]

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - shard-glk:          PASS -> FAIL [fdo#108948]

  * igt@kms_plane@plane-position-covered-pipe-c-planes:
    - shard-apl:          PASS -> FAIL [fdo#103166] +3

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
    - shard-glk:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-kbl:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
    - shard-glk:          PASS -> FAIL [fdo#103166] +5

  * igt@kms_properties@connector-properties-legacy:
    - shard-kbl:          PASS -> DMESG-WARN [fdo#103313] / [fdo#105345]

  * igt@kms_universal_plane@universal-plane-pipe-a-functional:
    - shard-kbl:          PASS -> FAIL [fdo#103166]

  
#### Possible fixes ####

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
    - shard-kbl:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_chv_cursor_fail@pipe-a-256x256-bottom-edge:
    - shard-snb:          {SKIP} [fdo#109271] / [fdo#109278] -> PASS

  * igt@kms_color@pipe-a-legacy-gamma:
    - shard-apl:          FAIL [fdo#104782] / [fdo#108145] -> PASS +1

  * igt@kms_color@pipe-c-legacy-gamma:
    - shard-kbl:          FAIL [fdo#104782] -> PASS
    - shard-apl:          FAIL [fdo#104782] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-suspend:
    - shard-apl:          FAIL [fdo#103191] / [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-256x85-random:
    - shard-apl:          FAIL [fdo#103232] -> PASS +5
    - shard-glk:          FAIL [fdo#103232] -> PASS +2

  * igt@kms_cursor_crc@cursor-256x85-sliding:
    - shard-kbl:          FAIL [fdo#103232] -> PASS +3

  * igt@kms_cursor_crc@cursor-64x64-suspend:
    - shard-kbl:          FAIL [fdo#103191] / [fdo#103232] -> PASS

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-glk:          FAIL [fdo#108145] -> PASS +1

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-apl:          FAIL [fdo#108145] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
    - shard-glk:          FAIL [fdo#103166] -> PASS
    - shard-apl:          FAIL [fdo#103166] -> PASS +2

  * igt@kms_setmode@basic:
    - shard-apl:          FAIL [fdo#99912] -> PASS

  
#### Warnings ####

  * igt@i915_suspend@shrink:
    - shard-kbl:          INCOMPLETE [fdo#103665] / [fdo#106886] -> DMESG-WARN [fdo#109244]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#105345]: https://bugs.freedesktop.org/show_bug.cgi?id=105345
  [fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
  [fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (6 -> 5)
------------------------------

  Missing    (1): shard-skl 


Build changes
-------------

    * IGT: IGT_4796 -> IGTPW_2310
    * Piglit: piglit_4509 -> None

  CI_DRM_5498: bebd74b74f0c62ff61036fc2d349fc470502b565 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2310: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2310/
  IGT_4796: d1bd9c6ad6f3482bbccf4aa6417dd449e9efbe39 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2310/
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