* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-06-13 22:06 vitaly.prosyak
2023-06-13 23:43 ` [igt-dev] ✗ GitLab.Pipeline: warning for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 20+ messages in thread
From: vitaly.prosyak @ 2023-06-13 22:06 UTC (permalink / raw)
To: igt-dev; +Cc: alexander.deucher, michael.strawbridge, christian.koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
tests/amdgpu/amd_syncobj.c | 293 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 294 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..d178c2600
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,293 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+
+#include "igt.h"
+#include "drmtest.h"
+#include "lib/amdgpu/amd_PM4.h" // GFX_COMPUTE_NOP
+#include "lib/amdgpu/amd_sdma.h" // SDMA_NOP
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include "lib/amdgpu/amd_memory.h"
+#include <pthread.h>
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static int
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal,
+ uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE,0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+
+ return r;
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+ int r;
+
+ r = syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+ igt_assert_eq(r, 0);
+
+ return (void *)(long)r;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+ int r;
+
+ r = syncobj_command_submission_helper(sp->device,sp->syncobj_handle, false,
+ sp->point);
+ igt_assert_eq(r, 0);
+
+ return (void *)(long)r;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 0x10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 7fff7602f..7342bb714 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -5,6 +5,7 @@ if libdrm_amdgpu.found()
amdgpu_progs += [ 'amd_abm',
'amd_assr',
'amd_basic',
+ 'amd_syncobj',
'amd_bypass',
'amd_deadlock',
'amd_pci_unplug',
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: warning for tests/amdgpu: add sync object tests
2023-06-13 22:06 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
@ 2023-06-13 23:43 ` Patchwork
2023-06-14 0:05 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-06-13 23:43 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
== Series Details ==
Series: tests/amdgpu: add sync object tests
URL : https://patchwork.freedesktop.org/series/119304/
State : warning
== Summary ==
Pipeline status: FAILED.
see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/908415 for the overview.
build:tests-debian-meson has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/43729110):
amdgpu_cs_syncobj_export_sync_file
../tests/amdgpu/amd_syncobj.c:240:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_export_sync_file2’ [-Wnested-externs]
../tests/amdgpu/amd_syncobj.c:245:6: error: implicit declaration of function ‘amdgpu_cs_syncobj_import_sync_file2’; did you mean ‘amdgpu_cs_syncobj_import_sync_file’? [-Werror=implicit-function-declaration]
r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
amdgpu_cs_syncobj_import_sync_file
../tests/amdgpu/amd_syncobj.c:245:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_import_sync_file2’ [-Wnested-externs]
../tests/amdgpu/amd_syncobj.c:255:6: error: implicit declaration of function ‘amdgpu_cs_syncobj_timeline_signal’; did you mean ‘amdgpu_cs_syncobj_signal’? [-Werror=implicit-function-declaration]
r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
amdgpu_cs_syncobj_signal
../tests/amdgpu/amd_syncobj.c:255:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_timeline_signal’ [-Wnested-externs]
cc1: some warnings being treated as errors
ninja: build stopped: subcommand failed.
section_end:1686699605:step_script
section_start:1686699605:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1686699606:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-debian-meson-arm64 has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/43729113):
amdgpu_cs_syncobj_export_sync_file
../tests/amdgpu/amd_syncobj.c:240:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_export_sync_file2’ [-Wnested-externs]
../tests/amdgpu/amd_syncobj.c:245:6: error: implicit declaration of function ‘amdgpu_cs_syncobj_import_sync_file2’; did you mean ‘amdgpu_cs_syncobj_import_sync_file’? [-Werror=implicit-function-declaration]
r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
amdgpu_cs_syncobj_import_sync_file
../tests/amdgpu/amd_syncobj.c:245:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_import_sync_file2’ [-Wnested-externs]
../tests/amdgpu/amd_syncobj.c:255:6: error: implicit declaration of function ‘amdgpu_cs_syncobj_timeline_signal’; did you mean ‘amdgpu_cs_syncobj_signal’? [-Werror=implicit-function-declaration]
r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
amdgpu_cs_syncobj_signal
../tests/amdgpu/amd_syncobj.c:255:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_timeline_signal’ [-Wnested-externs]
cc1: some warnings being treated as errors
ninja: build stopped: subcommand failed.
section_end:1686699609:step_script
section_start:1686699609:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1686699610:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-debian-meson-armhf has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/43729112):
amdgpu_cs_syncobj_export_sync_file
../tests/amdgpu/amd_syncobj.c:240:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_export_sync_file2’ [-Wnested-externs]
../tests/amdgpu/amd_syncobj.c:245:6: error: implicit declaration of function ‘amdgpu_cs_syncobj_import_sync_file2’; did you mean ‘amdgpu_cs_syncobj_import_sync_file’? [-Werror=implicit-function-declaration]
r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
amdgpu_cs_syncobj_import_sync_file
../tests/amdgpu/amd_syncobj.c:245:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_import_sync_file2’ [-Wnested-externs]
../tests/amdgpu/amd_syncobj.c:255:6: error: implicit declaration of function ‘amdgpu_cs_syncobj_timeline_signal’; did you mean ‘amdgpu_cs_syncobj_signal’? [-Werror=implicit-function-declaration]
r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
amdgpu_cs_syncobj_signal
../tests/amdgpu/amd_syncobj.c:255:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_timeline_signal’ [-Wnested-externs]
cc1: some warnings being treated as errors
ninja: build stopped: subcommand failed.
section_end:1686699602:step_script
section_start:1686699602:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1686699603:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-debian-meson-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/43729114):
amdgpu_cs_syncobj_export_sync_file
../tests/amdgpu/amd_syncobj.c:240:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_export_sync_file2’ [-Wnested-externs]
../tests/amdgpu/amd_syncobj.c:245:6: error: implicit declaration of function ‘amdgpu_cs_syncobj_import_sync_file2’; did you mean ‘amdgpu_cs_syncobj_import_sync_file’? [-Werror=implicit-function-declaration]
r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
amdgpu_cs_syncobj_import_sync_file
../tests/amdgpu/amd_syncobj.c:245:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_import_sync_file2’ [-Wnested-externs]
../tests/amdgpu/amd_syncobj.c:255:6: error: implicit declaration of function ‘amdgpu_cs_syncobj_timeline_signal’; did you mean ‘amdgpu_cs_syncobj_signal’? [-Werror=implicit-function-declaration]
r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
amdgpu_cs_syncobj_signal
../tests/amdgpu/amd_syncobj.c:255:6: warning: nested extern declaration of ‘amdgpu_cs_syncobj_timeline_signal’ [-Wnested-externs]
cc1: some warnings being treated as errors
ninja: build stopped: subcommand failed.
section_end:1686699619:step_script
section_start:1686699619:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1686699621:cleanup_file_variables
ERROR: Job failed: exit code 1
== Logs ==
For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/908415
^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for tests/amdgpu: add sync object tests
2023-06-13 22:06 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
2023-06-13 23:43 ` [igt-dev] ✗ GitLab.Pipeline: warning for " Patchwork
@ 2023-06-14 0:05 ` Patchwork
2023-06-14 5:13 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-06-14 0:05 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 4478 bytes --]
== Series Details ==
Series: tests/amdgpu: add sync object tests
URL : https://patchwork.freedesktop.org/series/119304/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13269 -> IGTPW_9164
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/index.html
Participating hosts (40 -> 39)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_9164 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_mocs:
- bat-mtlp-8: [PASS][1] -> [DMESG-FAIL][2] ([i915#7059])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
- bat-mtlp-6: [PASS][3] -> [DMESG-FAIL][4] ([i915#7059])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: NOTRUN -> [ABORT][5] ([i915#4983] / [i915#7461] / [i915#7981] / [i915#8347] / [i915#8384])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@i915_selftest@live@slpc:
- bat-mtlp-6: [PASS][6] -> [DMESG-WARN][7] ([i915#6367])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/bat-mtlp-6/igt@i915_selftest@live@slpc.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/bat-mtlp-6/igt@i915_selftest@live@slpc.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-6: [PASS][8] -> [DMESG-FAIL][9] ([i915#6763])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- bat-mtlp-8: [DMESG-FAIL][10] ([i915#8497]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/bat-mtlp-8/igt@i915_selftest@live@requests.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/bat-mtlp-8/igt@i915_selftest@live@requests.html
- bat-rpls-1: [ABORT][12] ([i915#7911] / [i915#7920]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/bat-rpls-1/igt@i915_selftest@live@requests.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/bat-rpls-1/igt@i915_selftest@live@requests.html
#### Warnings ####
* igt@i915_module_load@load:
- bat-adlp-11: [DMESG-WARN][14] ([i915#4423]) -> [ABORT][15] ([i915#4423])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/bat-adlp-11/igt@i915_module_load@load.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/bat-adlp-11/igt@i915_module_load@load.html
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
[i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7327 -> IGTPW_9164
CI-20190529: 20190529
CI_DRM_13269: c73de42e50dc07f5ae9342b28be76f2ee015e5af @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9164: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/index.html
IGT_7327: 34e48b7d6402c3d7af19a40d8951eae017cf64df @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/index.html
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for tests/amdgpu: add sync object tests
2023-06-13 22:06 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
2023-06-13 23:43 ` [igt-dev] ✗ GitLab.Pipeline: warning for " Patchwork
2023-06-14 0:05 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-06-14 5:13 ` Patchwork
2023-06-14 9:57 ` [igt-dev] [PATCH] " Christian König
2023-06-14 11:09 ` Kamil Konieczny
4 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-06-14 5:13 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 31856 bytes --]
== Series Details ==
Series: tests/amdgpu: add sync object tests
URL : https://patchwork.freedesktop.org/series/119304/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13269_full -> IGTPW_9164_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/index.html
Participating hosts (8 -> 7)
------------------------------
Missing (1): shard-rkl0
Known issues
------------
Here are the changes found in IGTPW_9164_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- shard-tglu: NOTRUN -> [SKIP][1] ([i915#7456])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-6/igt@debugfs_test@basic-hwmon.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][2] -> [FAIL][3] ([i915#7742])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_basic@multigpu-create-close:
- shard-rkl: NOTRUN -> [SKIP][4] ([i915#7697]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@gem_basic@multigpu-create-close.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-tglu: NOTRUN -> [SKIP][5] ([i915#4579] / [i915#5325])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-7/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: [PASS][6] -> [ABORT][7] ([i915#180])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-apl6/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-apl6/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-apl: [PASS][8] -> [DMESG-WARN][9] ([i915#180])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-apl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-apl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_ctx_persistence@smoketest:
- shard-tglu: [PASS][10] -> [FAIL][11] ([i915#5099])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-tglu-10/igt@gem_ctx_persistence@smoketest.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-9/igt@gem_ctx_persistence@smoketest.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][12] ([i915#7975] / [i915#8213])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-4/igt@gem_eio@hibernate.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-rkl: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: [PASS][16] -> [FAIL][17] ([i915#2842]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-6/igt@gem_exec_fair@basic-none@bcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-1/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_reloc@basic-gtt-wc:
- shard-rkl: NOTRUN -> [SKIP][18] ([i915#3281]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-wc.html
* igt@gem_exec_whisper@basic-fds-priority-all:
- shard-tglu: [PASS][19] -> [INCOMPLETE][20] ([i915#6755] / [i915#7392] / [i915#7967])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-tglu-5/igt@gem_exec_whisper@basic-fds-priority-all.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-10/igt@gem_exec_whisper@basic-fds-priority-all.html
* igt@gem_huc_copy@huc-copy:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#2190])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-glk: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-glk1/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-rkl: NOTRUN -> [SKIP][23] ([i915#4613])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-6/igt@gem_lmem_swapping@parallel-random-verify.html
- shard-tglu: NOTRUN -> [SKIP][24] ([i915#4613])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-10/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_pread@snoop:
- shard-rkl: NOTRUN -> [SKIP][25] ([i915#3282])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@gem_pread@snoop.html
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-rkl: NOTRUN -> [SKIP][26] ([i915#4270])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@gem_pxp@reject-modify-context-protection-off-1.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-rkl: NOTRUN -> [SKIP][27] ([fdo#109312])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-3/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglu: NOTRUN -> [SKIP][28] ([fdo#110542])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-9/igt@gem_userptr_blits@coherency-sync.html
* igt@gen7_exec_parse@load-register-reg:
- shard-tglu: NOTRUN -> [SKIP][29] ([fdo#109289])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-7/igt@gen7_exec_parse@load-register-reg.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][30] -> [ABORT][31] ([i915#5566])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-glk9/igt@gen9_exec_parse@allowed-single.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-glk8/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-param:
- shard-rkl: NOTRUN -> [SKIP][32] ([i915#2527])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-1/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-rkl: [PASS][33] -> [SKIP][34] ([i915#1397])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-4/igt@i915_pm_rpm@modeset-non-lpsp.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_power@sanity:
- shard-rkl: NOTRUN -> [SKIP][35] ([i915#7984])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-3/igt@i915_power@sanity.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-rkl: NOTRUN -> [SKIP][36] ([i915#5286]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][37] ([fdo#111614] / [i915#3638])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-tglu: NOTRUN -> [SKIP][38] ([fdo#111615])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-9/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-rkl: NOTRUN -> [SKIP][39] ([fdo#110723]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_joiner@basic:
- shard-rkl: NOTRUN -> [SKIP][40] ([i915#2705])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-2/igt@kms_big_joiner@basic.html
- shard-tglu: NOTRUN -> [SKIP][41] ([i915#2705])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-2/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][42] ([i915#3734] / [i915#5354] / [i915#6095])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][43] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-4/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][44] ([i915#3689] / [i915#5354] / [i915#6095])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#5354] / [i915#6095]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][46] ([i915#3886] / [i915#5354] / [i915#6095])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-3/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-glk3/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc:
- shard-rkl: NOTRUN -> [SKIP][48] ([i915#5354]) +7 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-6/igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs:
- shard-tglu: NOTRUN -> [SKIP][49] ([i915#5354] / [i915#6095]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-2/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs.html
* igt@kms_chamelium_color@ctm-blue-to-red:
- shard-rkl: NOTRUN -> [SKIP][50] ([fdo#111827])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@kms_chamelium_color@ctm-blue-to-red.html
* igt@kms_chamelium_color@ctm-max:
- shard-tglu: NOTRUN -> [SKIP][51] ([fdo#111827])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-7/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_hpd@dp-hpd:
- shard-rkl: NOTRUN -> [SKIP][52] ([i915#7828])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@kms_chamelium_hpd@dp-hpd.html
* igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
- shard-tglu: NOTRUN -> [SKIP][53] ([i915#7828])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-6/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-rkl: NOTRUN -> [SKIP][54] ([fdo#109279] / [i915#3359])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-tglu: NOTRUN -> [SKIP][55] ([fdo#109274])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][56] -> [FAIL][57] ([i915#2346])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-rkl: NOTRUN -> [SKIP][58] ([i915#4103])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-rkl: NOTRUN -> [SKIP][59] ([fdo#111825]) +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-3/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][60] -> [FAIL][61] ([i915#79])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-plain-flip-fb-recreate@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][62] -> [FAIL][63] ([i915#2122])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-glk9/igt@kms_flip@2x-plain-flip-fb-recreate@bc-hdmi-a1-hdmi-a2.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-glk6/igt@kms_flip@2x-plain-flip-fb-recreate@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][64] ([i915#2587] / [i915#2672] / [i915#4579])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-rkl: NOTRUN -> [SKIP][65] ([fdo#111825] / [i915#1825]) +7 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt:
- shard-tglu: NOTRUN -> [SKIP][66] ([fdo#109280]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][67] ([i915#3023]) +4 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][68] ([i915#5439])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
- shard-tglu: NOTRUN -> [SKIP][69] ([fdo#110189]) +5 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-2/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#3555] / [i915#4579])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c:
- shard-rkl: NOTRUN -> [SKIP][71] ([fdo#109289]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-6/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][72] ([i915#5176]) +3 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#4579] / [i915#5176]) +3 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][74] ([fdo#109271]) +16 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-snb7/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#4579]) +11 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-snb2/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][76] ([fdo#109271]) +53 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-glk2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-rkl: NOTRUN -> [SKIP][77] ([fdo#111068] / [i915#658]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-6/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr@sprite_mmap_gtt:
- shard-rkl: NOTRUN -> [SKIP][78] ([i915#1072]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-3/igt@kms_psr@sprite_mmap_gtt.html
* igt@kms_scaling_modes@scaling-mode-full:
- shard-glk: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#4579]) +6 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-glk1/igt@kms_scaling_modes@scaling-mode-full.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-tglu: NOTRUN -> [SKIP][80] ([i915#3555] / [i915#4579])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-3/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglu: NOTRUN -> [SKIP][81] ([i915#8623])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vblank@pipe-c-wait-forked-busy-hang:
- shard-rkl: NOTRUN -> [SKIP][82] ([i915#4070] / [i915#6768]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-2/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
* igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend:
- shard-rkl: NOTRUN -> [SKIP][83] ([i915#4070] / [i915#533] / [i915#6768]) +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html
* igt@v3d/v3d_submit_csd@single-out-sync:
- shard-rkl: NOTRUN -> [SKIP][84] ([fdo#109315]) +3 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-4/igt@v3d/v3d_submit_csd@single-out-sync.html
- shard-tglu: NOTRUN -> [SKIP][85] ([fdo#109315] / [i915#2575])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-9/igt@v3d/v3d_submit_csd@single-out-sync.html
* igt@vc4/vc4_perfmon@create-two-perfmon:
- shard-rkl: NOTRUN -> [SKIP][86] ([i915#7711]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-1/igt@vc4/vc4_perfmon@create-two-perfmon.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [FAIL][87] ([i915#7742]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [FAIL][89] ([i915#6268]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-6/igt@gem_ctx_exec@basic-nohangcheck.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@unwedge-stress:
- {shard-dg1}: [FAIL][91] ([i915#5784]) -> [PASS][92] +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-dg1-18/igt@gem_eio@unwedge-stress.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-dg1-18/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][93] ([i915#2842]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [FAIL][95] ([i915#2842]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-4/igt@gem_exec_fair@basic-pace@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-6/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-tglu: [ABORT][97] ([i915#7975] / [i915#8213]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-tglu-2/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-rkl: [SKIP][99] ([i915#1937] / [i915#4579]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-rkl-3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@i2c:
- shard-glk: [FAIL][101] ([i915#5466]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-glk6/igt@i915_pm_rpm@i2c.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-glk6/igt@i915_pm_rpm@i2c.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- {shard-dg1}: [SKIP][103] ([i915#1397]) -> [PASS][104] +2 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-dg1-15/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-2:
- shard-glk: [FAIL][105] ([i915#2521]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-glk9/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-2.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-glk1/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-2.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][107] ([i915#2346]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@single-bo@pipe-b:
- {shard-dg1}: [INCOMPLETE][109] ([i915#8011] / [i915#8347]) -> [PASS][110] +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13269/shard-dg1-19/igt@kms_cursor_legacy@single-bo@pipe-b.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/shard-dg1-16/igt@kms_cursor_legacy@single-bo@pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5466]: https://gitlab.freedesktop.org/drm/intel/issues/5466
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7967]: https://gitlab.freedesktop.org/drm/intel/issues/7967
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7327 -> IGTPW_9164
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13269: c73de42e50dc07f5ae9342b28be76f2ee015e5af @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9164: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/index.html
IGT_7327: 34e48b7d6402c3d7af19a40d8951eae017cf64df @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9164/index.html
[-- Attachment #2: Type: text/html, Size: 36828 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-06-13 22:06 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
` (2 preceding siblings ...)
2023-06-14 5:13 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
@ 2023-06-14 9:57 ` Christian König
2023-06-14 11:09 ` Kamil Konieczny
4 siblings, 0 replies; 20+ messages in thread
From: Christian König @ 2023-06-14 9:57 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: alexander.deucher, michael.strawbridge
Am 14.06.23 um 00:06 schrieb vitaly.prosyak@amd.com:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 293 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 294 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..d178c2600
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,293 @@
> +/* SPDX-License-Identifier: MIT
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> +*/
> +
> +
> +#include "igt.h"
> +#include "drmtest.h"
> +#include "lib/amdgpu/amd_PM4.h" // GFX_COMPUTE_NOP
> +#include "lib/amdgpu/amd_sdma.h" // SDMA_NOP
A long long time ago in a different job comments on preprocessor lines
were extremely frowned on.
Could be that modern compilers doesn't have a problem with that any
more, but I wouldn't bet on it.
Apart from that looks good to me,
Christian.
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +#include "lib/amdgpu/amd_memory.h"
> +#include <pthread.h>
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static int
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal,
> + uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE,0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +
> + return r;
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device,sp->syncobj_handle, false,
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 0x10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 7fff7602f..7342bb714 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -5,6 +5,7 @@ if libdrm_amdgpu.found()
> amdgpu_progs += [ 'amd_abm',
> 'amd_assr',
> 'amd_basic',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_deadlock',
> 'amd_pci_unplug',
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-06-13 22:06 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
` (3 preceding siblings ...)
2023-06-14 9:57 ` [igt-dev] [PATCH] " Christian König
@ 2023-06-14 11:09 ` Kamil Konieczny
4 siblings, 0 replies; 20+ messages in thread
From: Kamil Konieczny @ 2023-06-14 11:09 UTC (permalink / raw)
To: igt-dev; +Cc: alexander.deucher, michael.strawbridge, christian.koenig
Hi Vitaly,
On 2023-06-13 at 18:06:36 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 293 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 294 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..d178c2600
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,293 @@
> +/* SPDX-License-Identifier: MIT
-- ^^
Should be '//'
See for example tests/device_reset.c
Please use checkpatch.pl from Linux kernel scripts for finding
some problems, you can ignore 'line too long'.
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
----- ^
Delete this, it is replaced by SPDX above and the reason for
using SPDX was to drop such full licence texts.
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
----- ^
> + *
> +*/
-- ^^
Add space before so as to keep '*' aligned.
> +
> +
> +#include "igt.h"
----------- ^
Move igt includes after system ones.
> +#include "drmtest.h"
------------ ^
Sort includes alpabetically (in their sections).
> +#include "lib/amdgpu/amd_PM4.h" // GFX_COMPUTE_NOP
---------------------------------- ^
Maybe better to add comments before ?
> +#include "lib/amdgpu/amd_sdma.h" // SDMA_NOP
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
Put system includes first.
> +#include "lib/amdgpu/amd_memory.h"
----------- ^^
Move to igt include section.
> +#include <pthread.h>
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static int
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
------------------------------------ ^
> + uint32_t syncobj_handle, bool wait_or_signal,
----------------------------------------------------------------- ^
Align it to above amdgpu_device
> + uint64_t point)
Same here, align.
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
-------------------------------------------------------- ^
Add space before ':'
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE,0, &expired);
----------------------------------------------- ^
Space after ","
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
--------------------- ^ ^
> +
> + return r;
Why do you need to return 0 ? imho better make this a void
function.
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device,sp->syncobj_handle, false,
-------------------------------------------------------- ^
Space after ","
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
----------------------------- ^^^^^^^^^^^^^
> + timeout += 0x10000000000; //10s
------------------ ^^^
This is hex and above you use decimal ? Maybe use define or const.
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
------- ^
Add additional tab before, like
igt_subtest("amdgpu_syncobj_timeline")
amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
--------------- ^
drm_close_driver(fd);
Regards,
Kamil
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 7fff7602f..7342bb714 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -5,6 +5,7 @@ if libdrm_amdgpu.found()
> amdgpu_progs += [ 'amd_abm',
> 'amd_assr',
> 'amd_basic',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_deadlock',
> 'amd_pci_unplug',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-07-02 1:22 vitaly.prosyak
2023-07-03 7:39 ` Kamil Konieczny
0 siblings, 1 reply; 20+ messages in thread
From: vitaly.prosyak @ 2023-07-02 1:22 UTC (permalink / raw)
To: igt-dev; +Cc: Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v1->v2. Fixed style issues - Christian.
Fixed formatting issues - Kamil.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Acked-by: Christian Koenig <christian.koenig@amd.com>
Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 266 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..7cab093c9
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <pthread.h>
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 24843de73..02096934d 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
'amd_assr',
'amd_basic',
'amd_bo',
+ 'amd_syncobj',
'amd_bypass',
'amd_color',
'amd_cp_dma_misc',
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-07-02 1:22 vitaly.prosyak
@ 2023-07-03 7:39 ` Kamil Konieczny
2023-07-03 11:15 ` Prosyak, Vitaly
0 siblings, 1 reply; 20+ messages in thread
From: Kamil Konieczny @ 2023-07-03 7:39 UTC (permalink / raw)
To: igt-dev; +Cc: Christian Koenig
Hi Vitaly,
On 2023-07-01 at 21:22:30 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v1->v2. Fixed style issues - Christian.
> Fixed formatting issues - Kamil.
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Acked-by: Christian Koenig <christian.koenig@amd.com>
> Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Please do not merge this until you address GitLab compilation
issue.
Regards,
Kamil
> ---
> tests/amdgpu/amd_syncobj.c | 266 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..7cab093c9
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,266 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <pthread.h>
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 24843de73..02096934d 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
> 'amd_assr',
> 'amd_basic',
> 'amd_bo',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_color',
> 'amd_cp_dma_misc',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-07-03 7:39 ` Kamil Konieczny
@ 2023-07-03 11:15 ` Prosyak, Vitaly
0 siblings, 0 replies; 20+ messages in thread
From: Prosyak, Vitaly @ 2023-07-03 11:15 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev@lists.freedesktop.org; +Cc: Koenig, Christian
[-- Attachment #1: Type: text/plain, Size: 11622 bytes --]
[Public]
Hi Kamil,
Yes, sure,
I will work on this using your suggestion in the previous email.
Thanks, Vitaly
________________________________
From: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Sent: Monday, July 3, 2023 3:39 AM
To: igt-dev@lists.freedesktop.org <igt-dev@lists.freedesktop.org>
Cc: Prosyak, Vitaly <Vitaly.Prosyak@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>
Subject: Re: [PATCH] tests/amdgpu: add sync object tests
Hi Vitaly,
On 2023-07-01 at 21:22:30 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v1->v2. Fixed style issues - Christian.
> Fixed formatting issues - Kamil.
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Acked-by: Christian Koenig <christian.koenig@amd.com>
> Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Please do not merge this until you address GitLab compilation
issue.
Regards,
Kamil
> ---
> tests/amdgpu/amd_syncobj.c | 266 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..7cab093c9
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,266 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <pthread.h>
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 24843de73..02096934d 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
> 'amd_assr',
> 'amd_basic',
> 'amd_bo',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_color',
> 'amd_cp_dma_misc',
> --
> 2.25.1
>
[-- Attachment #2: Type: text/html, Size: 23964 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-22 21:17 vitaly.prosyak
2023-08-23 16:34 ` Kamil Konieczny
0 siblings, 1 reply; 20+ messages in thread
From: vitaly.prosyak @ 2023-08-22 21:17 UTC (permalink / raw)
To: igt-dev
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 263 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e83b5c5ad
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+
+#include <pthread.h>
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..1c4f5030b 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
'amd_assr',
'amd_basic',
'amd_bo',
+ 'amd_syncobj',
'amd_bypass',
'amd_color',
'amd_cp_dma_misc',
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-22 21:17 vitaly.prosyak
@ 2023-08-23 16:34 ` Kamil Konieczny
2023-08-24 0:42 ` vitaly prosyak
0 siblings, 1 reply; 20+ messages in thread
From: Kamil Konieczny @ 2023-08-23 16:34 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
Hi vitaly.prosyak,
On 2023-08-22 at 17:17:11 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
This is not building on some CI images, please fix this before merge.
Steps to reproduce:
on some images your test will not build,
to reproduce:
follow links from failed build to find out what container image was used,
for example here: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/47872456
click on failed run to show error log
install podman, enter to igt-tools source dir,
then run script:
POD_IGT=registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian:commit-1af4386ff3086df670e10af3a2bfd89993af3b0a
# search error log for line starting with:
# Using docker image sha256:... for registry.freedesktop.org/... with digest ...
# --------------------------------- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
# copy this string for POD_IGT above
mkdir -p /tmp/igt-build
cp -R * /tmp/igt-build/
sudo podman run -i -t -v /tmp/igt-build/:/opt/builds --privileged ${POD_IGT}
## end of script
now you will have root prompt '#' inside podman image (debian),
enter commands:
# cd /opt/builds
# meson build
# ninja -C build
and you can debug it yourself.
Regards,
Kamil
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 263 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e83b5c5ad
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +
> +#include <pthread.h>
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..1c4f5030b 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
> 'amd_assr',
> 'amd_basic',
> 'amd_bo',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_color',
> 'amd_cp_dma_misc',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-23 16:34 ` Kamil Konieczny
@ 2023-08-24 0:42 ` vitaly prosyak
0 siblings, 0 replies; 20+ messages in thread
From: vitaly prosyak @ 2023-08-24 0:42 UTC (permalink / raw)
To: Kamil Konieczny, vitaly.prosyak, igt-dev
Thanks a lot, Kamil for the explanation and useful commands.
I was delayed in dealing with this problem, now I have to finish .
Thanks, Vitaly
On 2023-08-23 12:34, Kamil Konieczny wrote:
> Hi vitaly.prosyak,
> On 2023-08-22 at 17:17:11 -0400, vitaly.prosyak@amd.com wrote:
>> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>>
>> Using worker thread to wait on point and then signal point on other thread.
>> Another test uses a worker thread to signal point and wait on the main
>> thread using amdgpu_cs_syncobj_timeline_wait.
>>
>> The command consists of two chunks :
>> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
>> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
>> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
>> point number .
>>
>> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
>> ---
>> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> This is not building on some CI images, please fix this before merge.
>
> Steps to reproduce:
>
> on some images your test will not build,
> to reproduce:
>
> follow links from failed build to find out what container image was used,
> for example here: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/47872456
> click on failed run to show error log
>
> install podman, enter to igt-tools source dir,
> then run script:
>
> POD_IGT=registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian:commit-1af4386ff3086df670e10af3a2bfd89993af3b0a
> # search error log for line starting with:
> # Using docker image sha256:... for registry.freedesktop.org/... with digest ...
> # --------------------------------- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> # copy this string for POD_IGT above
>
> mkdir -p /tmp/igt-build
> cp -R * /tmp/igt-build/
> sudo podman run -i -t -v /tmp/igt-build/:/opt/builds --privileged ${POD_IGT}
>
> ## end of script
>
> now you will have root prompt '#' inside podman image (debian),
> enter commands:
>
> # cd /opt/builds
> # meson build
> # ninja -C build
>
> and you can debug it yourself.
>
> Regards,
> Kamil
>
>> tests/amdgpu/meson.build | 1 +
>> 2 files changed, 263 insertions(+)
>> create mode 100644 tests/amdgpu/amd_syncobj.c
>>
>> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
>> new file mode 100644
>> index 000000000..e83b5c5ad
>> --- /dev/null
>> +++ b/tests/amdgpu/amd_syncobj.c
>> @@ -0,0 +1,262 @@
>> +// SPDX-License-Identifier: MIT
>> +
>> +#include <pthread.h>
>> +#include <amdgpu.h>
>> +#include <amdgpu_drm.h>
>> +
>> +#include "igt.h"
>> +#include "lib/amdgpu/amd_PM4.h"
>> +#include "lib/amdgpu/amd_sdma.h"
>> +#include "lib/amdgpu/amd_memory.h"
>> +
>> +struct syncobj_point {
>> + amdgpu_device_handle device;
>> + uint32_t syncobj_handle;
>> + uint64_t point;
>> +};
>> +
>> +
>> +static bool
>> +syncobj_timeline_enable(int fd)
>> +{
>> + int r;
>> + bool ret = false;
>> + uint64_t cap = 0;
>> +
>> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
>> + if (r || cap == 0)
>> + return ret;
>> + ret = true;
>> +
>> + return ret;
>> +}
>> +
>> +static void
>> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
>> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
>> +{
>> + amdgpu_context_handle context_handle;
>> + amdgpu_bo_handle ib_result_handle;
>> + void *ib_result_cpu;
>> + uint64_t ib_result_mc_address;
>> + struct drm_amdgpu_cs_chunk chunks[2];
>> + struct drm_amdgpu_cs_chunk_data chunk_data;
>> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
>> + struct amdgpu_cs_fence fence_status;
>> + amdgpu_bo_list_handle bo_list;
>> + amdgpu_va_handle va_handle;
>> + uint32_t expired;
>> + int i, r;
>> + uint64_t seq_no;
>> + uint32_t *ptr;
>> +
>> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
>> + AMDGPU_GEM_DOMAIN_GTT, 0,
>> + &ib_result_handle, &ib_result_cpu,
>> + &ib_result_mc_address, &va_handle);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
>> + igt_assert_eq(r, 0);
>> +
>> + ptr = ib_result_cpu;
>> +
>> + for (i = 0; i < 16; ++i)
>> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
>> +
>> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
>> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
>> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
>> + chunk_data.ib_data._pad = 0;
>> + chunk_data.ib_data.va_start = ib_result_mc_address;
>> + chunk_data.ib_data.ib_bytes = 16 * 4;
>> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
>> + chunk_data.ib_data.ip_instance = 0;
>> + chunk_data.ib_data.ring = 0;
>> + chunk_data.ib_data.flags = 0;
>> +
>> + chunks[1].chunk_id = wait_or_signal ?
>> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
>> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
>> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
>> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
>> + syncobj_data.handle = syncobj_handle;
>> + syncobj_data.point = point;
>> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
>> +
>> + r = amdgpu_cs_submit_raw(device_handle,
>> + context_handle,
>> + bo_list,
>> + 2,
>> + chunks,
>> + &seq_no);
>> + igt_assert_eq(r, 0);
>> +
>> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
>> + fence_status.context = context_handle;
>> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
>> + fence_status.ip_instance = 0;
>> + fence_status.ring = 0;
>> + fence_status.fence = seq_no;
>> +
>> + r = amdgpu_cs_query_fence_status(&fence_status,
>> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_list_destroy(bo_list);
>> + igt_assert_eq(r, 0);
>> +
>> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
>> + ib_result_mc_address, 4096);
>> +
>> + r = amdgpu_cs_ctx_free(context_handle);
>> + igt_assert_eq(r, 0);
>> +}
>> +
>> +static void *
>> +syncobj_wait(void *data)
>> +{
>> + struct syncobj_point *sp = (struct syncobj_point *)data;
>> +
>> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
>> + sp->point);
>> +
>> + return (void *)0;
>> +}
>> +
>> +static void *
>> +syncobj_signal(void *data)
>> +{
>> + struct syncobj_point *sp = (struct syncobj_point *)data;
>> +
>> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
>> + sp->point);
>> +
>> + return (void *)0;
>> +}
>> +
>> +static void
>> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
>> +{
>> + static pthread_t wait_thread;
>> + static pthread_t signal_thread;
>> + static pthread_t c_thread;
>> + struct syncobj_point sp1, sp2, sp3;
>> + uint32_t syncobj_handle;
>> + uint64_t payload;
>> + uint64_t wait_point, signal_point;
>> + uint64_t timeout;
>> + struct timespec tp;
>> + int r, sync_fd;
>> + void *tmp, *tmp2;
>> +
>> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
>> + igt_assert_eq(r, 0);
>> +
>> + // wait on point 5
>> + sp1.syncobj_handle = syncobj_handle;
>> + sp1.device = device_handle;
>> + sp1.point = 5;
>> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
>> + igt_assert_eq(r, 0);
>> +
>> + // signal on point 10
>> + sp2.syncobj_handle = syncobj_handle;
>> + sp2.device = device_handle;
>> + sp2.point = 10;
>> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
>> + igt_assert_eq(r, 0);
>> +
>> + r = pthread_join(signal_thread, &tmp);
>> + igt_assert_eq(r, 0);
>> +
>> + r = pthread_join(wait_thread, &tmp2);
>> + igt_assert_eq(r, 0);
>> +
>> + //query timeline payload
>> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> + &payload, 1);
>> + igt_assert_eq(r, 0);
>> + igt_assert_eq(payload, 10);
>> +
>> + //signal on point 16
>> + sp3.syncobj_handle = syncobj_handle;
>> + sp3.device = device_handle;
>> + sp3.point = 16;
>> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
>> + igt_assert_eq(r, 0);
>> +
>> + //CPU wait on point 16
>> + wait_point = 16;
>> + timeout = 0;
>> + clock_gettime(CLOCK_MONOTONIC, &tp);
>> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
>> + timeout += 10000000000; //10s
>> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
>> + &wait_point, 1, timeout,
>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>> + NULL);
>> +
>> + igt_assert_eq(r, 0);
>> + r = pthread_join(c_thread, &tmp);
>> + igt_assert_eq(r, 0);
>> +
>> + // export point 16 and import to point 18
>> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
>> + 16,
>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>> + &sync_fd);
>> + igt_assert_eq(r, 0);
>> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
>> + 18, sync_fd);
>> + igt_assert_eq(r, 0);
>> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> + &payload, 1);
>> + igt_assert_eq(r, 0);
>> + igt_assert_eq(payload, 18);
>> +
>> + // CPU signal on point 20
>> + signal_point = 20;
>> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
>> + &signal_point, 1);
>> + igt_assert_eq(r, 0);
>> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> + &payload, 1);
>> + igt_assert_eq(r, 0);
>> + igt_assert_eq(payload, 20);
>> +
>> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
>> + igt_assert_eq(r, 0);
>> +
>> +}
>> +
>> +igt_main
>> +{
>> + amdgpu_device_handle device;
>> + int fd = -1;
>> +
>> + igt_fixture {
>> + uint32_t major, minor;
>> + int err;
>> +
>> + fd = drm_open_driver(DRIVER_AMDGPU);
>> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
>> + igt_require(err == 0);
>> + igt_require(syncobj_timeline_enable(fd));
>> + igt_info("Initialized amdgpu, driver version %d.%d\n",
>> + major, minor);
>> +
>> + }
>> +
>> + igt_subtest("amdgpu_syncobj_timeline")
>> + amdgpu_syncobj_timeline(device);
>> +
>> + igt_fixture {
>> + amdgpu_device_deinitialize(device);
>> + close(fd);
>> + }
>> +}
>> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
>> index 6032a38e8..1c4f5030b 100644
>> --- a/tests/amdgpu/meson.build
>> +++ b/tests/amdgpu/meson.build
>> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
>> 'amd_assr',
>> 'amd_basic',
>> 'amd_bo',
>> + 'amd_syncobj',
>> 'amd_bypass',
>> 'amd_color',
>> 'amd_cp_dma_misc',
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-29 4:40 vitaly.prosyak
2023-08-29 12:24 ` Kamil Konieczny
2023-08-29 17:18 ` Luben Tuikov
0 siblings, 2 replies; 20+ messages in thread
From: vitaly.prosyak @ 2023-08-29 4:40 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e83b5c5ad
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+
+#include <pthread.h>
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..1520c34bd 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, no amd_syncobj test')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-29 4:40 vitaly.prosyak
@ 2023-08-29 12:24 ` Kamil Konieczny
2023-08-29 17:18 ` Luben Tuikov
1 sibling, 0 replies; 20+ messages in thread
From: Kamil Konieczny @ 2023-08-29 12:24 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
Hi Vitaly,
On 2023-08-29 at 00:40:06 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e83b5c5ad
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
Add Copyright here.
> +
> +#include <pthread.h>
------------ ^
Sort alphabetically (after amdgpu_drm.h)
Regards,
Kamil
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..1520c34bd 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, no amd_syncobj test')
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-29 4:40 vitaly.prosyak
2023-08-29 12:24 ` Kamil Konieczny
@ 2023-08-29 17:18 ` Luben Tuikov
1 sibling, 0 replies; 20+ messages in thread
From: Luben Tuikov @ 2023-08-29 17:18 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: Alex Deucher, Christian Koenig
Hi Vitaly,
Good work--thanks for working on this.
Inlined:
On 2023-08-29 00:40, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e83b5c5ad
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +
Should probably include the standard AMD copyright notice.
/* Copyright (C) 2023 Advanced Micro Devices Inc. */
> +#include <pthread.h>
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
In the function above, you don't need "ret"--the compiler optimizes it away
as follows:
static bool
syncobj_timeline_enable(int fd)
{
uint64_t cap = 0;
int r;
r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
return !(r || cap == 0);
}
Or you can use "!!!(r || cap == 0);" if the/a compiler complains.
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
Very nice. :-)
One question: Is it possible we hang indefinitely in
pthread_create()-->syncobj_signal/wait()-->amdgpu_cs_query_fence_status()?
If yes, is there a way to mitigate this and timeout the test, if run
from a nightly script for instance?
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..1520c34bd 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, no amd_syncobj test')
I'd probably print:
'libdrm <= 2.4.97 found, amd_syncobj test not applicable'
to clarify that for libdrm versions less than or equal to the one indicated,
the test while available is not applicable.
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
With these changes applied, this patch is,
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
--
Regards,
Luben
^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-30 14:55 vitaly.prosyak
2023-08-30 15:06 ` Luben Tuikov
0 siblings, 1 reply; 20+ messages in thread
From: vitaly.prosyak @ 2023-08-30 14:55 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
v3 : Kamil suggested sort alphabetically includes.
Luben suggested code and meson script improvements.
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e1d80758e
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include <pthread.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+
+ return !(r || cap == 0);
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..ebf52bf38 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-30 14:55 vitaly.prosyak
@ 2023-08-30 15:06 ` Luben Tuikov
0 siblings, 0 replies; 20+ messages in thread
From: Luben Tuikov @ 2023-08-30 15:06 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: Alex Deucher, Christian Koenig
Looks great--thanks! :-)
Regards,
Luben
On 2023-08-30 10:55, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
> v3 : Kamil suggested sort alphabetically includes.
> Luben suggested code and meson script improvements.
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
> Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e1d80758e
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +#include <pthread.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> +
> + return !(r || cap == 0);
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..ebf52bf38 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
--
Regards,
Luben
^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-31 0:24 vitaly.prosyak
0 siblings, 0 replies; 20+ messages in thread
From: vitaly.prosyak @ 2023-08-31 0:24 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
v3 : Kamil suggested sort alphabetically includes.
Luben suggested code and meson script improvements.
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e1d80758e
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include <pthread.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+
+ return !(r || cap == 0);
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..ebf52bf38 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-31 3:31 vitaly.prosyak
2023-08-31 13:07 ` Luben Tuikov
0 siblings, 1 reply; 20+ messages in thread
From: vitaly.prosyak @ 2023-08-31 3:31 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
v3 : Kamil suggested sort alphabetically includes.
Luben suggested code and meson script improvements.
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e1d80758e
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include <pthread.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+
+ return !(r || cap == 0);
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..ebf52bf38 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-31 3:31 vitaly.prosyak
@ 2023-08-31 13:07 ` Luben Tuikov
0 siblings, 0 replies; 20+ messages in thread
From: Luben Tuikov @ 2023-08-31 13:07 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: Alex Deucher, Christian Koenig
Looks good.
Regards,
Luben
On 2023-08-30 23:31, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
> v3 : Kamil suggested sort alphabetically includes.
> Luben suggested code and meson script improvements.
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
> Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e1d80758e
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +#include <pthread.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> +
> + return !(r || cap == 0);
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..ebf52bf38 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2023-08-31 13:07 UTC | newest]
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2023-06-13 22:06 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
2023-06-13 23:43 ` [igt-dev] ✗ GitLab.Pipeline: warning for " Patchwork
2023-06-14 0:05 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2023-06-14 5:13 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2023-06-14 9:57 ` [igt-dev] [PATCH] " Christian König
2023-06-14 11:09 ` Kamil Konieczny
-- strict thread matches above, loose matches on Subject: below --
2023-07-02 1:22 vitaly.prosyak
2023-07-03 7:39 ` Kamil Konieczny
2023-07-03 11:15 ` Prosyak, Vitaly
2023-08-22 21:17 vitaly.prosyak
2023-08-23 16:34 ` Kamil Konieczny
2023-08-24 0:42 ` vitaly prosyak
2023-08-29 4:40 vitaly.prosyak
2023-08-29 12:24 ` Kamil Konieczny
2023-08-29 17:18 ` Luben Tuikov
2023-08-30 14:55 vitaly.prosyak
2023-08-30 15:06 ` Luben Tuikov
2023-08-31 0:24 vitaly.prosyak
2023-08-31 3:31 vitaly.prosyak
2023-08-31 13:07 ` Luben Tuikov
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