* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-06-13 22:06 vitaly.prosyak
2023-06-14 9:57 ` Christian König
2023-06-14 11:09 ` Kamil Konieczny
0 siblings, 2 replies; 21+ messages in thread
From: vitaly.prosyak @ 2023-06-13 22:06 UTC (permalink / raw)
To: igt-dev; +Cc: alexander.deucher, michael.strawbridge, christian.koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
tests/amdgpu/amd_syncobj.c | 293 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 294 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..d178c2600
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,293 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+
+#include "igt.h"
+#include "drmtest.h"
+#include "lib/amdgpu/amd_PM4.h" // GFX_COMPUTE_NOP
+#include "lib/amdgpu/amd_sdma.h" // SDMA_NOP
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include "lib/amdgpu/amd_memory.h"
+#include <pthread.h>
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static int
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal,
+ uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE,0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+
+ return r;
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+ int r;
+
+ r = syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+ igt_assert_eq(r, 0);
+
+ return (void *)(long)r;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+ int r;
+
+ r = syncobj_command_submission_helper(sp->device,sp->syncobj_handle, false,
+ sp->point);
+ igt_assert_eq(r, 0);
+
+ return (void *)(long)r;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 0x10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 7fff7602f..7342bb714 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -5,6 +5,7 @@ if libdrm_amdgpu.found()
amdgpu_progs += [ 'amd_abm',
'amd_assr',
'amd_basic',
+ 'amd_syncobj',
'amd_bypass',
'amd_deadlock',
'amd_pci_unplug',
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-06-13 22:06 vitaly.prosyak
@ 2023-06-14 9:57 ` Christian König
2023-06-14 11:09 ` Kamil Konieczny
1 sibling, 0 replies; 21+ messages in thread
From: Christian König @ 2023-06-14 9:57 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: alexander.deucher, michael.strawbridge
Am 14.06.23 um 00:06 schrieb vitaly.prosyak@amd.com:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 293 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 294 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..d178c2600
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,293 @@
> +/* SPDX-License-Identifier: MIT
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> +*/
> +
> +
> +#include "igt.h"
> +#include "drmtest.h"
> +#include "lib/amdgpu/amd_PM4.h" // GFX_COMPUTE_NOP
> +#include "lib/amdgpu/amd_sdma.h" // SDMA_NOP
A long long time ago in a different job comments on preprocessor lines
were extremely frowned on.
Could be that modern compilers doesn't have a problem with that any
more, but I wouldn't bet on it.
Apart from that looks good to me,
Christian.
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +#include "lib/amdgpu/amd_memory.h"
> +#include <pthread.h>
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static int
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal,
> + uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE,0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +
> + return r;
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device,sp->syncobj_handle, false,
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 0x10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 7fff7602f..7342bb714 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -5,6 +5,7 @@ if libdrm_amdgpu.found()
> amdgpu_progs += [ 'amd_abm',
> 'amd_assr',
> 'amd_basic',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_deadlock',
> 'amd_pci_unplug',
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-06-13 22:06 vitaly.prosyak
2023-06-14 9:57 ` Christian König
@ 2023-06-14 11:09 ` Kamil Konieczny
1 sibling, 0 replies; 21+ messages in thread
From: Kamil Konieczny @ 2023-06-14 11:09 UTC (permalink / raw)
To: igt-dev; +Cc: alexander.deucher, michael.strawbridge, christian.koenig
Hi Vitaly,
On 2023-06-13 at 18:06:36 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 293 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 294 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..d178c2600
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,293 @@
> +/* SPDX-License-Identifier: MIT
-- ^^
Should be '//'
See for example tests/device_reset.c
Please use checkpatch.pl from Linux kernel scripts for finding
some problems, you can ignore 'line too long'.
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
----- ^
Delete this, it is replaced by SPDX above and the reason for
using SPDX was to drop such full licence texts.
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
----- ^
> + *
> +*/
-- ^^
Add space before so as to keep '*' aligned.
> +
> +
> +#include "igt.h"
----------- ^
Move igt includes after system ones.
> +#include "drmtest.h"
------------ ^
Sort includes alpabetically (in their sections).
> +#include "lib/amdgpu/amd_PM4.h" // GFX_COMPUTE_NOP
---------------------------------- ^
Maybe better to add comments before ?
> +#include "lib/amdgpu/amd_sdma.h" // SDMA_NOP
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
Put system includes first.
> +#include "lib/amdgpu/amd_memory.h"
----------- ^^
Move to igt include section.
> +#include <pthread.h>
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static int
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
------------------------------------ ^
> + uint32_t syncobj_handle, bool wait_or_signal,
----------------------------------------------------------------- ^
Align it to above amdgpu_device
> + uint64_t point)
Same here, align.
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
-------------------------------------------------------- ^
Add space before ':'
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE,0, &expired);
----------------------------------------------- ^
Space after ","
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
--------------------- ^ ^
> +
> + return r;
Why do you need to return 0 ? imho better make this a void
function.
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device,sp->syncobj_handle, false,
-------------------------------------------------------- ^
Space after ","
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
----------------------------- ^^^^^^^^^^^^^
> + timeout += 0x10000000000; //10s
------------------ ^^^
This is hex and above you use decimal ? Maybe use define or const.
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
------- ^
Add additional tab before, like
igt_subtest("amdgpu_syncobj_timeline")
amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
--------------- ^
drm_close_driver(fd);
Regards,
Kamil
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 7fff7602f..7342bb714 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -5,6 +5,7 @@ if libdrm_amdgpu.found()
> amdgpu_progs += [ 'amd_abm',
> 'amd_assr',
> 'amd_basic',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_deadlock',
> 'amd_pci_unplug',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-07-02 1:22 vitaly.prosyak
2023-07-03 7:39 ` Kamil Konieczny
0 siblings, 1 reply; 21+ messages in thread
From: vitaly.prosyak @ 2023-07-02 1:22 UTC (permalink / raw)
To: igt-dev; +Cc: Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v1->v2. Fixed style issues - Christian.
Fixed formatting issues - Kamil.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Acked-by: Christian Koenig <christian.koenig@amd.com>
Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 266 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..7cab093c9
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <pthread.h>
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 24843de73..02096934d 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
'amd_assr',
'amd_basic',
'amd_bo',
+ 'amd_syncobj',
'amd_bypass',
'amd_color',
'amd_cp_dma_misc',
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-07-02 1:22 vitaly.prosyak
@ 2023-07-03 7:39 ` Kamil Konieczny
2023-07-03 11:15 ` Prosyak, Vitaly
0 siblings, 1 reply; 21+ messages in thread
From: Kamil Konieczny @ 2023-07-03 7:39 UTC (permalink / raw)
To: igt-dev; +Cc: Christian Koenig
Hi Vitaly,
On 2023-07-01 at 21:22:30 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v1->v2. Fixed style issues - Christian.
> Fixed formatting issues - Kamil.
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Acked-by: Christian Koenig <christian.koenig@amd.com>
> Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Please do not merge this until you address GitLab compilation
issue.
Regards,
Kamil
> ---
> tests/amdgpu/amd_syncobj.c | 266 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..7cab093c9
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,266 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <pthread.h>
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 24843de73..02096934d 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
> 'amd_assr',
> 'amd_basic',
> 'amd_bo',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_color',
> 'amd_cp_dma_misc',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-07-03 7:39 ` Kamil Konieczny
@ 2023-07-03 11:15 ` Prosyak, Vitaly
0 siblings, 0 replies; 21+ messages in thread
From: Prosyak, Vitaly @ 2023-07-03 11:15 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev@lists.freedesktop.org; +Cc: Koenig, Christian
[-- Attachment #1: Type: text/plain, Size: 11622 bytes --]
[Public]
Hi Kamil,
Yes, sure,
I will work on this using your suggestion in the previous email.
Thanks, Vitaly
________________________________
From: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Sent: Monday, July 3, 2023 3:39 AM
To: igt-dev@lists.freedesktop.org <igt-dev@lists.freedesktop.org>
Cc: Prosyak, Vitaly <Vitaly.Prosyak@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>
Subject: Re: [PATCH] tests/amdgpu: add sync object tests
Hi Vitaly,
On 2023-07-01 at 21:22:30 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v1->v2. Fixed style issues - Christian.
> Fixed formatting issues - Kamil.
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Acked-by: Christian Koenig <christian.koenig@amd.com>
> Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Please do not merge this until you address GitLab compilation
issue.
Regards,
Kamil
> ---
> tests/amdgpu/amd_syncobj.c | 266 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..7cab093c9
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,266 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <pthread.h>
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 24843de73..02096934d 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
> 'amd_assr',
> 'amd_basic',
> 'amd_bo',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_color',
> 'amd_cp_dma_misc',
> --
> 2.25.1
>
[-- Attachment #2: Type: text/html, Size: 23964 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-22 21:17 vitaly.prosyak
2023-08-23 16:34 ` Kamil Konieczny
0 siblings, 1 reply; 21+ messages in thread
From: vitaly.prosyak @ 2023-08-22 21:17 UTC (permalink / raw)
To: igt-dev
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 263 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e83b5c5ad
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+
+#include <pthread.h>
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..1c4f5030b 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
'amd_assr',
'amd_basic',
'amd_bo',
+ 'amd_syncobj',
'amd_bypass',
'amd_color',
'amd_cp_dma_misc',
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-22 21:17 vitaly.prosyak
@ 2023-08-23 16:34 ` Kamil Konieczny
2023-08-24 0:42 ` vitaly prosyak
0 siblings, 1 reply; 21+ messages in thread
From: Kamil Konieczny @ 2023-08-23 16:34 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
Hi vitaly.prosyak,
On 2023-08-22 at 17:17:11 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
This is not building on some CI images, please fix this before merge.
Steps to reproduce:
on some images your test will not build,
to reproduce:
follow links from failed build to find out what container image was used,
for example here: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/47872456
click on failed run to show error log
install podman, enter to igt-tools source dir,
then run script:
POD_IGT=registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian:commit-1af4386ff3086df670e10af3a2bfd89993af3b0a
# search error log for line starting with:
# Using docker image sha256:... for registry.freedesktop.org/... with digest ...
# --------------------------------- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
# copy this string for POD_IGT above
mkdir -p /tmp/igt-build
cp -R * /tmp/igt-build/
sudo podman run -i -t -v /tmp/igt-build/:/opt/builds --privileged ${POD_IGT}
## end of script
now you will have root prompt '#' inside podman image (debian),
enter commands:
# cd /opt/builds
# meson build
# ninja -C build
and you can debug it yourself.
Regards,
Kamil
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 263 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e83b5c5ad
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +
> +#include <pthread.h>
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..1c4f5030b 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
> 'amd_assr',
> 'amd_basic',
> 'amd_bo',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_color',
> 'amd_cp_dma_misc',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-23 16:34 ` Kamil Konieczny
@ 2023-08-24 0:42 ` vitaly prosyak
0 siblings, 0 replies; 21+ messages in thread
From: vitaly prosyak @ 2023-08-24 0:42 UTC (permalink / raw)
To: Kamil Konieczny, vitaly.prosyak, igt-dev
Thanks a lot, Kamil for the explanation and useful commands.
I was delayed in dealing with this problem, now I have to finish .
Thanks, Vitaly
On 2023-08-23 12:34, Kamil Konieczny wrote:
> Hi vitaly.prosyak,
> On 2023-08-22 at 17:17:11 -0400, vitaly.prosyak@amd.com wrote:
>> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>>
>> Using worker thread to wait on point and then signal point on other thread.
>> Another test uses a worker thread to signal point and wait on the main
>> thread using amdgpu_cs_syncobj_timeline_wait.
>>
>> The command consists of two chunks :
>> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
>> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
>> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
>> point number .
>>
>> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
>> ---
>> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> This is not building on some CI images, please fix this before merge.
>
> Steps to reproduce:
>
> on some images your test will not build,
> to reproduce:
>
> follow links from failed build to find out what container image was used,
> for example here: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/47872456
> click on failed run to show error log
>
> install podman, enter to igt-tools source dir,
> then run script:
>
> POD_IGT=registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian:commit-1af4386ff3086df670e10af3a2bfd89993af3b0a
> # search error log for line starting with:
> # Using docker image sha256:... for registry.freedesktop.org/... with digest ...
> # --------------------------------- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> # copy this string for POD_IGT above
>
> mkdir -p /tmp/igt-build
> cp -R * /tmp/igt-build/
> sudo podman run -i -t -v /tmp/igt-build/:/opt/builds --privileged ${POD_IGT}
>
> ## end of script
>
> now you will have root prompt '#' inside podman image (debian),
> enter commands:
>
> # cd /opt/builds
> # meson build
> # ninja -C build
>
> and you can debug it yourself.
>
> Regards,
> Kamil
>
>> tests/amdgpu/meson.build | 1 +
>> 2 files changed, 263 insertions(+)
>> create mode 100644 tests/amdgpu/amd_syncobj.c
>>
>> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
>> new file mode 100644
>> index 000000000..e83b5c5ad
>> --- /dev/null
>> +++ b/tests/amdgpu/amd_syncobj.c
>> @@ -0,0 +1,262 @@
>> +// SPDX-License-Identifier: MIT
>> +
>> +#include <pthread.h>
>> +#include <amdgpu.h>
>> +#include <amdgpu_drm.h>
>> +
>> +#include "igt.h"
>> +#include "lib/amdgpu/amd_PM4.h"
>> +#include "lib/amdgpu/amd_sdma.h"
>> +#include "lib/amdgpu/amd_memory.h"
>> +
>> +struct syncobj_point {
>> + amdgpu_device_handle device;
>> + uint32_t syncobj_handle;
>> + uint64_t point;
>> +};
>> +
>> +
>> +static bool
>> +syncobj_timeline_enable(int fd)
>> +{
>> + int r;
>> + bool ret = false;
>> + uint64_t cap = 0;
>> +
>> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
>> + if (r || cap == 0)
>> + return ret;
>> + ret = true;
>> +
>> + return ret;
>> +}
>> +
>> +static void
>> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
>> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
>> +{
>> + amdgpu_context_handle context_handle;
>> + amdgpu_bo_handle ib_result_handle;
>> + void *ib_result_cpu;
>> + uint64_t ib_result_mc_address;
>> + struct drm_amdgpu_cs_chunk chunks[2];
>> + struct drm_amdgpu_cs_chunk_data chunk_data;
>> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
>> + struct amdgpu_cs_fence fence_status;
>> + amdgpu_bo_list_handle bo_list;
>> + amdgpu_va_handle va_handle;
>> + uint32_t expired;
>> + int i, r;
>> + uint64_t seq_no;
>> + uint32_t *ptr;
>> +
>> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
>> + AMDGPU_GEM_DOMAIN_GTT, 0,
>> + &ib_result_handle, &ib_result_cpu,
>> + &ib_result_mc_address, &va_handle);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
>> + igt_assert_eq(r, 0);
>> +
>> + ptr = ib_result_cpu;
>> +
>> + for (i = 0; i < 16; ++i)
>> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
>> +
>> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
>> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
>> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
>> + chunk_data.ib_data._pad = 0;
>> + chunk_data.ib_data.va_start = ib_result_mc_address;
>> + chunk_data.ib_data.ib_bytes = 16 * 4;
>> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
>> + chunk_data.ib_data.ip_instance = 0;
>> + chunk_data.ib_data.ring = 0;
>> + chunk_data.ib_data.flags = 0;
>> +
>> + chunks[1].chunk_id = wait_or_signal ?
>> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
>> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
>> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
>> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
>> + syncobj_data.handle = syncobj_handle;
>> + syncobj_data.point = point;
>> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
>> +
>> + r = amdgpu_cs_submit_raw(device_handle,
>> + context_handle,
>> + bo_list,
>> + 2,
>> + chunks,
>> + &seq_no);
>> + igt_assert_eq(r, 0);
>> +
>> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
>> + fence_status.context = context_handle;
>> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
>> + fence_status.ip_instance = 0;
>> + fence_status.ring = 0;
>> + fence_status.fence = seq_no;
>> +
>> + r = amdgpu_cs_query_fence_status(&fence_status,
>> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_list_destroy(bo_list);
>> + igt_assert_eq(r, 0);
>> +
>> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
>> + ib_result_mc_address, 4096);
>> +
>> + r = amdgpu_cs_ctx_free(context_handle);
>> + igt_assert_eq(r, 0);
>> +}
>> +
>> +static void *
>> +syncobj_wait(void *data)
>> +{
>> + struct syncobj_point *sp = (struct syncobj_point *)data;
>> +
>> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
>> + sp->point);
>> +
>> + return (void *)0;
>> +}
>> +
>> +static void *
>> +syncobj_signal(void *data)
>> +{
>> + struct syncobj_point *sp = (struct syncobj_point *)data;
>> +
>> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
>> + sp->point);
>> +
>> + return (void *)0;
>> +}
>> +
>> +static void
>> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
>> +{
>> + static pthread_t wait_thread;
>> + static pthread_t signal_thread;
>> + static pthread_t c_thread;
>> + struct syncobj_point sp1, sp2, sp3;
>> + uint32_t syncobj_handle;
>> + uint64_t payload;
>> + uint64_t wait_point, signal_point;
>> + uint64_t timeout;
>> + struct timespec tp;
>> + int r, sync_fd;
>> + void *tmp, *tmp2;
>> +
>> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
>> + igt_assert_eq(r, 0);
>> +
>> + // wait on point 5
>> + sp1.syncobj_handle = syncobj_handle;
>> + sp1.device = device_handle;
>> + sp1.point = 5;
>> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
>> + igt_assert_eq(r, 0);
>> +
>> + // signal on point 10
>> + sp2.syncobj_handle = syncobj_handle;
>> + sp2.device = device_handle;
>> + sp2.point = 10;
>> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
>> + igt_assert_eq(r, 0);
>> +
>> + r = pthread_join(signal_thread, &tmp);
>> + igt_assert_eq(r, 0);
>> +
>> + r = pthread_join(wait_thread, &tmp2);
>> + igt_assert_eq(r, 0);
>> +
>> + //query timeline payload
>> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> + &payload, 1);
>> + igt_assert_eq(r, 0);
>> + igt_assert_eq(payload, 10);
>> +
>> + //signal on point 16
>> + sp3.syncobj_handle = syncobj_handle;
>> + sp3.device = device_handle;
>> + sp3.point = 16;
>> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
>> + igt_assert_eq(r, 0);
>> +
>> + //CPU wait on point 16
>> + wait_point = 16;
>> + timeout = 0;
>> + clock_gettime(CLOCK_MONOTONIC, &tp);
>> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
>> + timeout += 10000000000; //10s
>> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
>> + &wait_point, 1, timeout,
>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>> + NULL);
>> +
>> + igt_assert_eq(r, 0);
>> + r = pthread_join(c_thread, &tmp);
>> + igt_assert_eq(r, 0);
>> +
>> + // export point 16 and import to point 18
>> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
>> + 16,
>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>> + &sync_fd);
>> + igt_assert_eq(r, 0);
>> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
>> + 18, sync_fd);
>> + igt_assert_eq(r, 0);
>> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> + &payload, 1);
>> + igt_assert_eq(r, 0);
>> + igt_assert_eq(payload, 18);
>> +
>> + // CPU signal on point 20
>> + signal_point = 20;
>> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
>> + &signal_point, 1);
>> + igt_assert_eq(r, 0);
>> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> + &payload, 1);
>> + igt_assert_eq(r, 0);
>> + igt_assert_eq(payload, 20);
>> +
>> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
>> + igt_assert_eq(r, 0);
>> +
>> +}
>> +
>> +igt_main
>> +{
>> + amdgpu_device_handle device;
>> + int fd = -1;
>> +
>> + igt_fixture {
>> + uint32_t major, minor;
>> + int err;
>> +
>> + fd = drm_open_driver(DRIVER_AMDGPU);
>> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
>> + igt_require(err == 0);
>> + igt_require(syncobj_timeline_enable(fd));
>> + igt_info("Initialized amdgpu, driver version %d.%d\n",
>> + major, minor);
>> +
>> + }
>> +
>> + igt_subtest("amdgpu_syncobj_timeline")
>> + amdgpu_syncobj_timeline(device);
>> +
>> + igt_fixture {
>> + amdgpu_device_deinitialize(device);
>> + close(fd);
>> + }
>> +}
>> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
>> index 6032a38e8..1c4f5030b 100644
>> --- a/tests/amdgpu/meson.build
>> +++ b/tests/amdgpu/meson.build
>> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
>> 'amd_assr',
>> 'amd_basic',
>> 'amd_bo',
>> + 'amd_syncobj',
>> 'amd_bypass',
>> 'amd_color',
>> 'amd_cp_dma_misc',
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-29 4:40 vitaly.prosyak
2023-08-29 4:54 ` [igt-dev] ✗ GitLab.Pipeline: warning for tests/amdgpu: add sync object tests (rev4) Patchwork
` (5 more replies)
0 siblings, 6 replies; 21+ messages in thread
From: vitaly.prosyak @ 2023-08-29 4:40 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e83b5c5ad
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+
+#include <pthread.h>
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..1520c34bd 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, no amd_syncobj test')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: warning for tests/amdgpu: add sync object tests (rev4)
2023-08-29 4:40 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
@ 2023-08-29 4:54 ` Patchwork
2023-08-29 5:24 ` [igt-dev] ✓ CI.xeBAT: success " Patchwork
` (4 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-08-29 4:54 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
== Series Details ==
Series: tests/amdgpu: add sync object tests (rev4)
URL : https://patchwork.freedesktop.org/series/119304/
State : warning
== Summary ==
Pipeline status: FAILED.
see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/972106 for the overview.
build-containers:build-debian has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48129632):
time="2023-08-29T04:51:18Z" level=fatal msg="Error determining repository tags: Invalid status code returned when fetching tags list 503 (Service Unavailable)"
Building!
STEP 1: FROM debian:buster
Getting image source signatures
Copying blob sha256:d6b7393fb4f375905c31c483d81ce2a2905f88aba8cb198874da2b54035bc41d
Copying config sha256:de08540e8ff0e470ff7956df4bed403725a5f45c186e9bf495da5344ff8fbe84
Writing manifest to image destination
Storing signatures
STEP 2: RUN apt-get update
error running container: error creating container for [/bin/sh -c apt-get update]: time="2023-08-29T04:51:23Z" level=warning msg="signal: killed"
time="2023-08-29T04:51:23Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
: exit status 1
Error: error building at STEP "RUN apt-get update": error while running runtime: exit status 1
section_end:1693284684:step_script
section_start:1693284684:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1693284685:cleanup_file_variables
ERROR: Job failed: exit code 1
build-containers:build-debian-arm64 has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48129634):
time="2023-08-29T04:52:40Z" level=fatal msg="Error determining repository tags: Invalid status code returned when fetching tags list 503 (Service Unavailable)"
Building!
STEP 1: FROM debian:buster
Getting image source signatures
Copying blob sha256:d6b7393fb4f375905c31c483d81ce2a2905f88aba8cb198874da2b54035bc41d
Copying config sha256:de08540e8ff0e470ff7956df4bed403725a5f45c186e9bf495da5344ff8fbe84
Writing manifest to image destination
Storing signatures
STEP 2: RUN apt-get update
error running container: error creating container for [/bin/sh -c apt-get update]: time="2023-08-29T04:52:45Z" level=warning msg="signal: killed"
time="2023-08-29T04:52:45Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
: exit status 1
Error: error building at STEP "RUN apt-get update": error while running runtime: exit status 1
section_end:1693284765:step_script
section_start:1693284765:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1693284767:cleanup_file_variables
ERROR: Job failed: exit code 1
build-containers:build-debian-armhf has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48129633):
section_end:1693284519:prepare_executor
section_start:1693284519:prepare_script
Preparing environment
Running on runner-yyhtcik-project-3185-concurrent-0 via 6811c9562478...
section_end:1693284520:prepare_script
section_start:1693284520:get_sources
Getting source from Git repository
$ /host/bin/curl -s -L --cacert /host/ca-certificates.crt --retry 4 -f --retry-delay 60 https://gitlab.freedesktop.org/freedesktop/helm-gitlab-infra/-/raw/main/runner-gating/runner-gating.sh | sh -s -- pre_get_sources_script
Checking if the user of the pipeline is allowed...
Checking if the job's project is part of a well-known group...
Thank you for contributing to freedesktop.org
Fetching changes...
Reinitialized existing Git repository in /builds/gfx-ci/igt-ci-tags/.git/
fatal: unable to access 'https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags.git/': Failed to connect to gitlab.freedesktop.org port 443 after 129356 ms: Couldn't connect to server
section_end:1693284650:get_sources
section_start:1693284650:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1693284651:cleanup_file_variables
ERROR: Job failed: exit code 1
build-containers:build-debian-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48129635):
time="2023-08-29T04:52:01Z" level=fatal msg="Error determining repository tags: Invalid status code returned when fetching tags list 503 (Service Unavailable)"
Building!
STEP 1: FROM debian:buster
Getting image source signatures
Copying blob sha256:d6b7393fb4f375905c31c483d81ce2a2905f88aba8cb198874da2b54035bc41d
Copying config sha256:de08540e8ff0e470ff7956df4bed403725a5f45c186e9bf495da5344ff8fbe84
Writing manifest to image destination
Storing signatures
STEP 2: RUN apt-get update
error running container: error creating container for [/bin/sh -c apt-get update]: time="2023-08-29T04:52:05Z" level=warning msg="signal: killed"
time="2023-08-29T04:52:05Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
: exit status 1
Error: error building at STEP "RUN apt-get update": error while running runtime: exit status 1
section_end:1693284726:step_script
section_start:1693284726:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1693284726:cleanup_file_variables
ERROR: Job failed: exit code 1
build-containers:build-fedora has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48129636):
time="2023-08-29T04:51:44Z" level=fatal msg="Error determining repository tags: Invalid status code returned when fetching tags list 503 (Service Unavailable)"
Building!
STEP 1: FROM fedora:31
Getting image source signatures
Copying blob sha256:854946d575a439a894349addd141568875d7c1e673d3286b08250f3dde002e6a
Copying config sha256:7e94ed77b448a8d2ff08b92d3ca743e4e862c744892d6886c73487581eb5863a
Writing manifest to image destination
Storing signatures
STEP 2: RUN dnf install -y gcc flex bison libatomic meson ninja-build xdotool 'pkgconfig(libdrm)' 'pkgconfig(pciaccess)' 'pkgconfig(libkmod)' 'pkgconfig(libprocps)' 'pkgconfig(libunwind)' 'pkgconfig(libdw)' 'pkgconfig(pixman-1)' 'pkgconfig(valgrind)' 'pkgconfig(cairo)' 'pkgconfig(libudev)' 'pkgconfig(glib-2.0)' 'pkgconfig(gsl)' 'pkgconfig(alsa)' 'pkgconfig(xmlrpc)' 'pkgconfig(xmlrpc_util)' 'pkgconfig(xmlrpc_client)' 'pkgconfig(json-c)' 'pkgconfig(gtk-doc)' 'pkgconfig(xv)' 'pkgconfig(xrandr)' python3-docutils
error running container: error creating container for [/bin/sh -c dnf install -y gcc flex bison libatomic meson ninja-build xdotool 'pkgconfig(libdrm)' 'pkgconfig(pciaccess)' 'pkgconfig(libkmod)' 'pkgconfig(libprocps)' 'pkgconfig(libunwind)' 'pkgconfig(libdw)' 'pkgconfig(pixman-1)' 'pkgconfig(valgrind)' 'pkgconfig(cairo)' 'pkgconfig(libudev)' 'pkgconfig(glib-2.0)' 'pkgconfig(gsl)' 'pkgconfig(alsa)' 'pkgconfig(xmlrpc)' 'pkgconfig(xmlrpc_util)' 'pkgconfig(xmlrpc_client)' 'pkgconfig(json-c)' 'pkgconfig(gtk-doc)' 'pkgconfig(xv)' 'pkgconfig(xrandr)' python3-docutils]: time="2023-08-29T04:51:50Z" level=warning msg="signal: killed"
time="2023-08-29T04:51:50Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
: exit status 1
Error: error building at STEP "RUN dnf install -y gcc flex bison libatomic meson ninja-build xdotool 'pkgconfig(libdrm)' 'pkgconfig(pciaccess)' 'pkgconfig(libkmod)' 'pkgconfig(libprocps)' 'pkgconfig(libunwind)' 'pkgconfig(libdw)' 'pkgconfig(pixman-1)' 'pkgconfig(valgrind)' 'pkgconfig(cairo)' 'pkgconfig(libudev)' 'pkgconfig(glib-2.0)' 'pkgconfig(gsl)' 'pkgconfig(alsa)' 'pkgconfig(xmlrpc)' 'pkgconfig(xmlrpc_util)' 'pkgconfig(xmlrpc_client)' 'pkgconfig(json-c)' 'pkgconfig(gtk-doc)' 'pkgconfig(xv)' 'pkgconfig(xrandr)' python3-docutils": error while running runtime: exit status 1
section_end:1693284711:step_script
section_start:1693284711:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1693284712:cleanup_file_variables
ERROR: Job failed: exit code 1
== Logs ==
For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/972106
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] ✓ CI.xeBAT: success for tests/amdgpu: add sync object tests (rev4)
2023-08-29 4:40 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
2023-08-29 4:54 ` [igt-dev] ✗ GitLab.Pipeline: warning for tests/amdgpu: add sync object tests (rev4) Patchwork
@ 2023-08-29 5:24 ` Patchwork
2023-08-29 5:28 ` [igt-dev] ✓ Fi.CI.BAT: " Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-08-29 5:24 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 3989 bytes --]
== Series Details ==
Series: tests/amdgpu: add sync object tests (rev4)
URL : https://patchwork.freedesktop.org/series/119304/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_7454_BAT -> XEIGTPW_9674_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (2 -> 4)
------------------------------
Additional (2): bat-pvc-2 bat-dg2-oem2
Known issues
------------
Here are the changes found in XEIGTPW_9674_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-oem2: NOTRUN -> [SKIP][1] ([i915#5274])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9674/bat-dg2-oem2/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12:
- bat-dg2-oem2: NOTRUN -> [FAIL][2] ([Intel XE#400]) +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9674/bat-dg2-oem2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12.html
* igt@kms_psr@primary_page_flip:
- bat-dg2-oem2: NOTRUN -> [SKIP][3] ([i915#1072]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9674/bat-dg2-oem2/igt@kms_psr@primary_page_flip.html
* igt@xe_compute@compute-square:
- bat-dg2-oem2: NOTRUN -> [SKIP][4] ([Intel XE#252])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9674/bat-dg2-oem2/igt@xe_compute@compute-square.html
* igt@xe_exec_fault_mode@many-basic:
- bat-dg2-oem2: NOTRUN -> [SKIP][5] ([Intel XE#288]) +17 similar issues
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9674/bat-dg2-oem2/igt@xe_exec_fault_mode@many-basic.html
* igt@xe_huc_copy@huc_copy:
- bat-dg2-oem2: NOTRUN -> [SKIP][6] ([Intel XE#255])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9674/bat-dg2-oem2/igt@xe_huc_copy@huc_copy.html
* igt@xe_live_ktest@bo:
- bat-dg2-oem2: NOTRUN -> [SKIP][7] ([Intel XE#483]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9674/bat-dg2-oem2/igt@xe_live_ktest@bo.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/252
[Intel XE#255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/255
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/389
[Intel XE#400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/400
[Intel XE#482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/482
[Intel XE#483]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/483
[Intel XE#526]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/526
[Intel XE#531]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/531
[Intel XE#532]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/532
[Intel XE#533]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/533
[Intel XE#535]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/535
[Intel XE#536]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/536
[Intel XE#537]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/537
[Intel XE#538]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/538
[Intel XE#539]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/539
[Intel XE#540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/540
[Intel XE#541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/541
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
Build changes
-------------
* IGT: IGT_7454 -> IGTPW_9674
IGTPW_9674: 9674
IGT_7454: 7454
xe-340-c77796cf84361b4716839141f2e48de2bf7f4bd5: c77796cf84361b4716839141f2e48de2bf7f4bd5
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^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for tests/amdgpu: add sync object tests (rev4)
2023-08-29 4:40 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
2023-08-29 4:54 ` [igt-dev] ✗ GitLab.Pipeline: warning for tests/amdgpu: add sync object tests (rev4) Patchwork
2023-08-29 5:24 ` [igt-dev] ✓ CI.xeBAT: success " Patchwork
@ 2023-08-29 5:28 ` Patchwork
2023-08-29 7:37 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-08-29 5:28 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 2818 bytes --]
== Series Details ==
Series: tests/amdgpu: add sync object tests (rev4)
URL : https://patchwork.freedesktop.org/series/119304/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13572 -> IGTPW_9674
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/index.html
Participating hosts (39 -> 28)
------------------------------
Missing (11): bat-adlp-11 fi-skl-guc bat-adlm-1 fi-ilk-650 fi-snb-2520m bat-adlp-6 fi-hsw-4770 bat-adln-1 fi-kbl-8809g bat-dg2-13 bat-rpls-2
Known issues
------------
Here are the changes found in IGTPW_9674 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#6645])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-edp-1:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-edp-1.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- bat-mtlp-8: [ABORT][3] ([i915#7982]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/bat-mtlp-8/igt@i915_selftest@live@requests.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/bat-mtlp-8/igt@i915_selftest@live@requests.html
#### Warnings ####
* igt@kms_psr@sprite_plane_onoff:
- bat-rplp-1: [SKIP][5] ([i915#1072]) -> [ABORT][6] ([i915#8442] / [i915#8668] / [i915#8712])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8712]: https://gitlab.freedesktop.org/drm/intel/issues/8712
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7454 -> IGTPW_9674
CI-20190529: 20190529
CI_DRM_13572: f2dfaec0582a995d5e74e5b1896dd6772f5ca9e6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9674: 9674
IGT_7454: 7454
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/index.html
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^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for tests/amdgpu: add sync object tests (rev4)
2023-08-29 4:40 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
` (2 preceding siblings ...)
2023-08-29 5:28 ` [igt-dev] ✓ Fi.CI.BAT: " Patchwork
@ 2023-08-29 7:37 ` Patchwork
2023-08-29 12:24 ` [igt-dev] [PATCH] tests/amdgpu: add sync object tests Kamil Konieczny
2023-08-29 17:18 ` Luben Tuikov
5 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-08-29 7:37 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 82590 bytes --]
== Series Details ==
Series: tests/amdgpu: add sync object tests (rev4)
URL : https://patchwork.freedesktop.org/series/119304/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13572_full -> IGTPW_9674_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/index.html
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in IGTPW_9674_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-dg2: NOTRUN -> [SKIP][1] ([i915#8411]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@api_intel_bb@blit-reloc-keep-cache.html
- shard-rkl: NOTRUN -> [SKIP][2] ([i915#8411])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@api_intel_bb@render-ccs:
- shard-dg2: NOTRUN -> [FAIL][3] ([i915#6122])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@api_intel_bb@render-ccs.html
* igt@drm_fdinfo@busy-idle@bcs0:
- shard-dg2: NOTRUN -> [SKIP][4] ([i915#8414]) +21 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@drm_fdinfo@busy-idle@bcs0.html
* igt@feature_discovery@chamelium:
- shard-tglu: NOTRUN -> [SKIP][5] ([fdo#111827])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-8/igt@feature_discovery@chamelium.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-dg2: NOTRUN -> [SKIP][6] ([i915#7697])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-dg2: NOTRUN -> [SKIP][7] ([i915#8555]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-5/igt@gem_ctx_persistence@heartbeat-stop.html
* igt@gem_ctx_persistence@processes:
- shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-snb6/igt@gem_ctx_persistence@processes.html
* igt@gem_ctx_sseu@mmap-args:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#280])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_exec_balancer@bonded-dual:
- shard-dg2: NOTRUN -> [SKIP][10] ([i915#4771])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@bonded-sync:
- shard-mtlp: NOTRUN -> [SKIP][11] ([i915#4771])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-5/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-rkl: NOTRUN -> [SKIP][12] ([i915#4525])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: [PASS][13] -> [FAIL][14] ([i915#2846])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-rkl-1/igt@gem_exec_fair@basic-deadline.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-throttle:
- shard-dg1: NOTRUN -> [SKIP][15] ([i915#3539])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-17/igt@gem_exec_fair@basic-throttle.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-rkl: NOTRUN -> [FAIL][16] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@gem_exec_fair@basic-throttle@rcs0.html
- shard-tglu: NOTRUN -> [FAIL][17] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-9/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_fence@submit3:
- shard-dg2: NOTRUN -> [SKIP][18] ([i915#4812]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@gem_exec_fence@submit3.html
* igt@gem_exec_flush@basic-batch-kernel-default-uc:
- shard-mtlp: [PASS][19] -> [DMESG-FAIL][20] ([i915#8962] / [i915#9121])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-5/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-4/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
* igt@gem_exec_flush@basic-wb-rw-default:
- shard-dg2: NOTRUN -> [SKIP][21] ([i915#3539] / [i915#4852]) +4 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@gem_exec_flush@basic-wb-rw-default.html
* igt@gem_exec_gttfill@multigpu-basic:
- shard-rkl: NOTRUN -> [SKIP][22] ([i915#7697])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@gem_exec_gttfill@multigpu-basic.html
- shard-dg1: NOTRUN -> [SKIP][23] ([i915#7697])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-14/igt@gem_exec_gttfill@multigpu-basic.html
- shard-tglu: NOTRUN -> [SKIP][24] ([i915#7697])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-8/igt@gem_exec_gttfill@multigpu-basic.html
* igt@gem_exec_params@secure-non-root:
- shard-rkl: NOTRUN -> [SKIP][25] ([fdo#112283])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-1/igt@gem_exec_params@secure-non-root.html
- shard-dg1: NOTRUN -> [SKIP][26] ([fdo#112283])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-14/igt@gem_exec_params@secure-non-root.html
- shard-tglu: NOTRUN -> [SKIP][27] ([fdo#112283])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-2/igt@gem_exec_params@secure-non-root.html
* igt@gem_exec_reloc@basic-cpu-noreloc:
- shard-rkl: NOTRUN -> [SKIP][28] ([i915#3281]) +3 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-noreloc.html
- shard-dg1: NOTRUN -> [SKIP][29] ([i915#3281]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-13/igt@gem_exec_reloc@basic-cpu-noreloc.html
* igt@gem_exec_reloc@basic-gtt-wc:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#3281]) +9 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-2/igt@gem_exec_reloc@basic-gtt-wc.html
* igt@gem_exec_reloc@basic-write-read-active:
- shard-mtlp: NOTRUN -> [SKIP][31] ([i915#3281]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-2/igt@gem_exec_reloc@basic-write-read-active.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#4537] / [i915#4812])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@gem_exec_schedule@preempt-queue-contexts-chain.html
* igt@gem_exec_schedule@preemptive-hang@vcs0:
- shard-mtlp: [PASS][33] -> [FAIL][34] ([i915#9051])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-6/igt@gem_exec_schedule@preemptive-hang@vcs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-5/igt@gem_exec_schedule@preemptive-hang@vcs0.html
* igt@gem_exec_suspend@basic-s0@lmem0:
- shard-dg2: [PASS][35] -> [INCOMPLETE][36] ([i915#6311])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-11/igt@gem_exec_suspend@basic-s0@lmem0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-5/igt@gem_exec_suspend@basic-s0@lmem0.html
* igt@gem_fenced_exec_thrash@too-many-fences:
- shard-dg2: NOTRUN -> [SKIP][37] ([i915#4860])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@gem_fenced_exec_thrash@too-many-fences.html
* igt@gem_lmem_swapping@random-engines:
- shard-rkl: NOTRUN -> [SKIP][38] ([i915#4613])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@gem_lmem_swapping@random-engines.html
- shard-tglu: NOTRUN -> [SKIP][39] ([i915#4613])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-6/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [PASS][40] -> [TIMEOUT][41] ([i915#5493])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-8/igt@gem_lmem_swapping@smem-oom@lmem0.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#4613]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-3/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_mmap@basic:
- shard-dg1: NOTRUN -> [SKIP][43] ([i915#4083])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-13/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@zero-extend:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#4077]) +11 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@gem_mmap_gtt@zero-extend.html
* igt@gem_mmap_wc@read:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#4083])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-3/igt@gem_mmap_wc@read.html
* igt@gem_mmap_wc@write-wc-read-gtt:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4083]) +4 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@gem_mmap_wc@write-wc-read-gtt.html
* igt@gem_partial_pwrite_pread@reads:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#3282]) +6 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_partial_pwrite_pread@write-uncached:
- shard-mtlp: NOTRUN -> [SKIP][48] ([i915#3282])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-1/igt@gem_partial_pwrite_pread@write-uncached.html
* igt@gem_pwrite@basic-random:
- shard-rkl: NOTRUN -> [SKIP][49] ([i915#3282]) +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@gem_pwrite@basic-random.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#4270]) +2 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-5/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-rkl: NOTRUN -> [SKIP][51] ([i915#4270]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
- shard-tglu: NOTRUN -> [SKIP][52] ([i915#4270])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-8/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#8428]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-2/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#4079]) +3 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_spin_batch@spin-all-new:
- shard-dg2: NOTRUN -> [FAIL][55] ([i915#5889])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@gem_spin_batch@spin-all-new.html
* igt@gem_unfence_active_buffers:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#4879])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg1: NOTRUN -> [SKIP][57] ([i915#3297] / [i915#4880])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-14/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#3297] / [i915#4880]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#3297])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-dg2: NOTRUN -> [SKIP][60] ([i915#3297]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gem_userptr_blits@vma-merge:
- shard-rkl: NOTRUN -> [FAIL][61] ([i915#3318])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-1/igt@gem_userptr_blits@vma-merge.html
- shard-dg1: NOTRUN -> [FAIL][62] ([i915#3318])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-14/igt@gem_userptr_blits@vma-merge.html
- shard-tglu: NOTRUN -> [FAIL][63] ([i915#3318])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-2/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_render_linear_blits:
- shard-rkl: NOTRUN -> [SKIP][64] ([fdo#109289]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-2/igt@gen3_render_linear_blits.html
- shard-dg1: NOTRUN -> [SKIP][65] ([fdo#109289]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-16/igt@gen3_render_linear_blits.html
- shard-tglu: NOTRUN -> [SKIP][66] ([fdo#109289]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-7/igt@gen3_render_linear_blits.html
* igt@gen7_exec_parse@basic-offset:
- shard-dg2: NOTRUN -> [SKIP][67] ([fdo#109289]) +4 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@allowed-all:
- shard-rkl: NOTRUN -> [SKIP][68] ([i915#2527]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-dg1: NOTRUN -> [SKIP][69] ([i915#2527])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-16/igt@gen9_exec_parse@bb-start-cmd.html
- shard-tglu: NOTRUN -> [SKIP][70] ([i915#2527] / [i915#2856])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-3/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@bb-start-far:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#2856]) +5 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-2/igt@gen9_exec_parse@bb-start-far.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-mtlp: NOTRUN -> [SKIP][72] ([i915#2856])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-8/igt@gen9_exec_parse@unaligned-jump.html
* igt@i915_pm_backlight@bad-brightness:
- shard-dg2: NOTRUN -> [SKIP][73] ([i915#5354] / [i915#7561])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@i915_pm_backlight@bad-brightness.html
* igt@i915_pm_dc@dc5-psr:
- shard-rkl: NOTRUN -> [SKIP][74] ([i915#658]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@i915_pm_dc@dc5-psr.html
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#658])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-16/igt@i915_pm_dc@dc5-psr.html
- shard-tglu: NOTRUN -> [SKIP][76] ([i915#658])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-8/igt@i915_pm_dc@dc5-psr.html
* igt@i915_pm_dc@dc9-dpms:
- shard-tglu: [PASS][77] -> [SKIP][78] ([i915#4281])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-tglu-2/igt@i915_pm_dc@dc9-dpms.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-6/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_freq_api@freq-reset-multiple:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#8399])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@i915_pm_freq_api@freq-reset-multiple.html
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- shard-dg1: [PASS][80] -> [FAIL][81] ([i915#3591])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-tglu: NOTRUN -> [SKIP][82] ([fdo#111644] / [i915#1397]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-8/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp:
- shard-dg2: [PASS][83] -> [SKIP][84] ([i915#1397])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-12/igt@i915_pm_rpm@modeset-lpsp.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-3/igt@i915_pm_rpm@modeset-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-rkl: [PASS][85] -> [SKIP][86] ([i915#1397])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#1397])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_pm_rps@basic-api:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#6621])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-mtlp: NOTRUN -> [SKIP][89] ([i915#6621])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-7/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#6188])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@i915_query@query-topology-unsupported:
- shard-dg2: NOTRUN -> [SKIP][91] ([fdo#109302])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@i915_query@query-topology-unsupported.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-mtlp: NOTRUN -> [SKIP][92] ([i915#4077]) +3 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-6/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_addfb_basic@clobberred-modifier:
- shard-dg2: NOTRUN -> [SKIP][93] ([i915#4212]) +2 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-2/igt@kms_addfb_basic@clobberred-modifier.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-dp-4-4-mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#8709]) +11 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-dp-4-4-mc_ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-y-rc_ccs:
- shard-dg1: NOTRUN -> [SKIP][95] ([i915#8502]) +7 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-19/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][96] ([i915#8247]) +3 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-17/igt@kms_async_flips@crc@pipe-d-hdmi-a-4.html
* igt@kms_async_flips@invalid-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][97] ([i915#6228])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-7/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_async_flips@test-cursor:
- shard-mtlp: NOTRUN -> [SKIP][98] ([i915#6229])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-3/igt@kms_async_flips@test-cursor.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#1769] / [i915#3555])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#5286]) +2 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-2/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-0:
- shard-mtlp: [PASS][101] -> [DMESG-WARN][102] ([i915#2017])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-5/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-2/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][103] ([i915#4538] / [i915#5286]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-17/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-mtlp: [PASS][104] -> [FAIL][105] ([i915#5138])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-tglu: NOTRUN -> [SKIP][106] ([fdo#111615] / [i915#5286]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@linear-64bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][107] ([fdo#111614] / [i915#3638])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-2/igt@kms_big_fb@linear-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-mtlp: NOTRUN -> [SKIP][108] ([fdo#111614]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-8/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][109] ([fdo#111614]) +2 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-mtlp: [PASS][110] -> [FAIL][111] ([i915#3743]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#5190]) +15 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-2/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][113] ([fdo#111615]) +3 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#4538] / [i915#5190]) +8 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-rkl: NOTRUN -> [SKIP][115] ([fdo#110723])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
- shard-dg1: NOTRUN -> [SKIP][116] ([i915#4538])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-16/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
- shard-tglu: NOTRUN -> [SKIP][117] ([fdo#111615])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-10/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_mtl_rc_ccs_cc:
- shard-rkl: NOTRUN -> [SKIP][118] ([i915#5354] / [i915#6095]) +6 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_mtl_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][119] ([i915#3734] / [i915#5354] / [i915#6095]) +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-1/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_ccs.html
- shard-dg1: NOTRUN -> [SKIP][120] ([i915#3689] / [i915#5354] / [i915#6095])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-16/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#5354]) +60 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc:
- shard-tglu: NOTRUN -> [SKIP][122] ([i915#5354] / [i915#6095]) +7 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-4/igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs_cc:
- shard-tglu: NOTRUN -> [SKIP][123] ([i915#3689] / [i915#5354] / [i915#6095]) +2 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-10/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#3689] / [i915#5354]) +19 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_ccs:
- shard-mtlp: NOTRUN -> [SKIP][125] ([i915#6095]) +12 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-3/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#3886] / [i915#5354] / [i915#6095]) +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-2/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][127] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-4/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#3689] / [i915#3886] / [i915#5354]) +12 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-3/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][129] ([fdo#109271]) +3 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-apl2/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_mtl_rc_ccs:
- shard-dg1: NOTRUN -> [SKIP][130] ([i915#5354] / [i915#6095]) +3 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-19/igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_mtl_rc_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][131] ([i915#5354]) +11 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_cdclk@mode-transition@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][132] ([i915#7213] / [i915#9010]) +3 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-1/igt@kms_cdclk@mode-transition@pipe-b-edp-1.html
* igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][133] ([i915#7213]) +3 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-2/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2.html
* igt@kms_chamelium_color@degamma:
- shard-dg2: NOTRUN -> [SKIP][134] ([fdo#111827]) +3 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@kms_chamelium_color@degamma.html
- shard-rkl: NOTRUN -> [SKIP][135] ([fdo#111827]) +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-rkl: NOTRUN -> [SKIP][136] ([i915#7828]) +2 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-2/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#7828]) +6 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-3/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_chamelium_hpd@dp-hpd:
- shard-dg1: NOTRUN -> [SKIP][138] ([i915#7828])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-14/igt@kms_chamelium_hpd@dp-hpd.html
- shard-tglu: NOTRUN -> [SKIP][139] ([i915#7828])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-10/igt@kms_chamelium_hpd@dp-hpd.html
* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-mtlp: NOTRUN -> [SKIP][140] ([i915#7828]) +4 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-1/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: NOTRUN -> [SKIP][141] ([i915#7118])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-5/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@srm@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][142] ([i915#7173])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@kms_content_protection@srm@pipe-a-dp-4.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][143] ([i915#1339])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-rkl: NOTRUN -> [SKIP][144] ([i915#3555]) +1 similar issue
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-2/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-rkl: NOTRUN -> [SKIP][145] ([fdo#109279] / [i915#3359])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html
- shard-tglu: NOTRUN -> [SKIP][146] ([fdo#109279] / [i915#3359])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-3/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-mtlp: NOTRUN -> [SKIP][147] ([i915#8814]) +1 similar issue
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-7/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-dg2: NOTRUN -> [SKIP][148] ([i915#3555]) +8 similar issues
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-2/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-rkl: NOTRUN -> [SKIP][149] ([i915#3359])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
- shard-dg1: NOTRUN -> [SKIP][150] ([i915#3359]) +1 similar issue
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-19/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
- shard-tglu: NOTRUN -> [SKIP][151] ([i915#3359])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-7/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-mtlp: NOTRUN -> [SKIP][152] ([i915#3359])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-7/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#3359])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_crc@cursor-suspend@pipe-b-vga-1:
- shard-snb: NOTRUN -> [DMESG-WARN][154] ([i915#8841]) +3 similar issues
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-snb6/igt@kms_cursor_crc@cursor-suspend@pipe-b-vga-1.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-snb: NOTRUN -> [SKIP][155] ([fdo#109271] / [fdo#111767]) +1 similar issue
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-snb2/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-dg2: NOTRUN -> [SKIP][156] ([i915#4103] / [i915#4213]) +1 similar issue
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-tglu: NOTRUN -> [SKIP][157] ([fdo#109274]) +1 similar issue
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-rkl: NOTRUN -> [SKIP][158] ([fdo#111767] / [fdo#111825])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
- shard-dg1: NOTRUN -> [SKIP][159] ([fdo#111767] / [fdo#111825])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-14/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
- shard-tglu: NOTRUN -> [SKIP][160] ([fdo#109274] / [fdo#111767])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
- shard-dg2: NOTRUN -> [SKIP][161] ([fdo#109274] / [i915#5354]) +2 similar issues
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-dg2: NOTRUN -> [SKIP][162] ([fdo#109274] / [fdo#111767] / [i915#5354])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][163] ([i915#3546]) +1 similar issue
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-6/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][164] -> [FAIL][165] ([i915#2346])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-rkl: NOTRUN -> [SKIP][166] ([i915#4103])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
- shard-tglu: NOTRUN -> [SKIP][167] ([i915#4103])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_display_modes@extended-mode-basic:
- shard-mtlp: NOTRUN -> [SKIP][168] ([i915#8827])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-8/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-dg2: NOTRUN -> [SKIP][169] ([i915#8588])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_draw_crc@draw-method-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][170] ([i915#8812])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_draw_crc@draw-method-mmap-wc.html
* igt@kms_dsc@dsc-basic:
- shard-dg2: NOTRUN -> [SKIP][171] ([i915#3555] / [i915#3840]) +1 similar issue
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@kms_dsc@dsc-basic.html
* igt@kms_fbcon_fbt@psr:
- shard-dg2: NOTRUN -> [SKIP][172] ([i915#3469])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglu: NOTRUN -> [SKIP][173] ([fdo#109274] / [i915#3637] / [i915#3966])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-7/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-dg2: NOTRUN -> [SKIP][174] ([fdo#109274]) +7 similar issues
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-dg2: NOTRUN -> [SKIP][175] ([fdo#109274] / [fdo#111767])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][176] ([i915#8381]) +1 similar issue
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-snb: NOTRUN -> [SKIP][177] ([fdo#109271]) +240 similar issues
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-snb2/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@2x-plain-flip:
- shard-rkl: NOTRUN -> [SKIP][178] ([fdo#111825]) +5 similar issues
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-1/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][179] ([i915#3637])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-7/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-tglu: NOTRUN -> [SKIP][180] ([fdo#109274] / [i915#3637]) +1 similar issue
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][181] ([i915#2672]) +2 similar issues
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#2587] / [i915#2672]) +1 similar issue
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
- shard-tglu: NOTRUN -> [SKIP][183] ([i915#2587] / [i915#2672]) +1 similar issue
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#2672]) +4 similar issues
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][185] ([i915#8810])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][186] ([i915#2672])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-dg2: [PASS][187] -> [FAIL][188] ([i915#6880])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#8708]) +19 similar issues
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite:
- shard-mtlp: NOTRUN -> [SKIP][190] ([i915#1825]) +9 similar issues
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][191] ([i915#8708]) +3 similar issues
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-19/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][192] ([fdo#111825]) +10 similar issues
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html
- shard-tglu: NOTRUN -> [SKIP][193] ([fdo#109280]) +7 similar issues
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][194] ([fdo#111825] / [i915#1825]) +14 similar issues
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][195] ([fdo#110189]) +5 similar issues
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-2/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#3458]) +17 similar issues
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][197] ([i915#8708]) +5 similar issues
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-rkl: NOTRUN -> [SKIP][198] ([i915#3023]) +9 similar issues
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@bpc-switch:
- shard-dg2: NOTRUN -> [SKIP][199] ([i915#3555] / [i915#8228]) +2 similar issues
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-5/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-dg1: NOTRUN -> [SKIP][200] ([i915#3555] / [i915#8228])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-19/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-rkl: NOTRUN -> [SKIP][201] ([i915#3555] / [i915#8228]) +1 similar issue
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@kms_hdr@invalid-metadata-sizes.html
- shard-tglu: NOTRUN -> [SKIP][202] ([i915#3555] / [i915#8228]) +1 similar issue
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-8/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#4816])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-dg2: [PASS][204] -> [INCOMPLETE][205] ([i915#7886])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-5/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][206] ([i915#8292])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][207] ([i915#8292])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][208] ([i915#8292])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-17/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][209] ([i915#5176]) +15 similar issues
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-13/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][210] ([i915#5176]) +11 similar issues
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][211] ([i915#5176]) +1 similar issue
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][212] ([i915#5176]) +3 similar issues
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-5/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-c-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][213] ([i915#5235]) +15 similar issues
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-2.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][214] ([i915#5235]) +1 similar issue
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][215] ([i915#5235]) +3 similar issues
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][216] ([i915#5235]) +19 similar issues
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-19/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1.html
* igt@kms_prime@d3hot:
- shard-dg2: NOTRUN -> [SKIP][217] ([i915#6524] / [i915#6805])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-1/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][218] ([fdo#111068] / [i915#658])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
- shard-dg1: NOTRUN -> [SKIP][219] ([fdo#111068] / [i915#658])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-16/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
- shard-tglu: NOTRUN -> [SKIP][220] ([fdo#111068] / [i915#658])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-10/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr@psr2_dpms:
- shard-dg2: NOTRUN -> [SKIP][221] ([i915#1072]) +10 similar issues
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_psr@psr2_dpms.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#5461] / [i915#658])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][223] ([i915#4235])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#4235] / [i915#5190]) +1 similar issue
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
- shard-rkl: NOTRUN -> [SKIP][225] ([fdo#111615] / [i915#5289])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-mtlp: NOTRUN -> [SKIP][226] ([i915#4235]) +1 similar issue
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-5/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-tglu: NOTRUN -> [SKIP][227] ([i915#3555])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-9/igt@kms_scaling_modes@scaling-mode-full-aspect.html
- shard-dg1: NOTRUN -> [SKIP][228] ([i915#3555])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-17/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_selftest@drm_format_helper:
- shard-snb: NOTRUN -> [SKIP][229] ([fdo#109271] / [i915#8661]) +2 similar issues
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-snb4/igt@kms_selftest@drm_format_helper.html
* igt@kms_setmode@basic@pipe-a-vga-1:
- shard-snb: NOTRUN -> [FAIL][230] ([i915#5465]) +1 similar issue
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-snb6/igt@kms_setmode@basic@pipe-a-vga-1.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: NOTRUN -> [FAIL][231] ([IGT#2])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2: NOTRUN -> [SKIP][232] ([i915#8623])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tv_load_detect@load-detect:
- shard-dg2: NOTRUN -> [SKIP][233] ([fdo#109309])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vblank@pipe-c-ts-continuation-idle:
- shard-rkl: NOTRUN -> [SKIP][234] ([i915#4070] / [i915#6768]) +1 similar issue
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@kms_vblank@pipe-c-ts-continuation-idle.html
* igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend:
- shard-dg2: [PASS][235] -> [FAIL][236] ([fdo#103375])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-2/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-5/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html
* igt@kms_vblank@pipe-d-ts-continuation-modeset:
- shard-rkl: NOTRUN -> [SKIP][237] ([i915#4070] / [i915#533] / [i915#6768]) +1 similar issue
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-1/igt@kms_vblank@pipe-d-ts-continuation-modeset.html
* igt@kms_writeback@writeback-fb-id:
- shard-dg2: NOTRUN -> [SKIP][238] ([i915#2437])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@kms_writeback@writeback-fb-id.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [PASS][239] -> [FAIL][240] ([i915#4349]) +3 similar issues
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@perf_pmu@busy-double-start@vecs1.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-dg2: NOTRUN -> [SKIP][241] ([i915#8516])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-5/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][242] ([i915#3291] / [i915#3708])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@fence-read-hang:
- shard-rkl: NOTRUN -> [SKIP][243] ([fdo#109295] / [i915#3708])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@prime_vgem@fence-read-hang.html
- shard-dg1: NOTRUN -> [SKIP][244] ([i915#3708])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-19/igt@prime_vgem@fence-read-hang.html
- shard-tglu: NOTRUN -> [SKIP][245] ([fdo#109295])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-6/igt@prime_vgem@fence-read-hang.html
* igt@prime_vgem@fence-write-hang:
- shard-dg2: NOTRUN -> [SKIP][246] ([i915#3708])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@prime_vgem@fence-write-hang.html
* igt@sysfs_timeslice_duration@timeout@vecs0:
- shard-mtlp: [PASS][247] -> [ABORT][248] ([i915#8521] / [i915#8865])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-7/igt@sysfs_timeslice_duration@timeout@vecs0.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-5/igt@sysfs_timeslice_duration@timeout@vecs0.html
* igt@v3d/v3d_perfmon@create-perfmon-0:
- shard-mtlp: NOTRUN -> [SKIP][249] ([i915#2575]) +7 similar issues
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-4/igt@v3d/v3d_perfmon@create-perfmon-0.html
* igt@v3d/v3d_submit_cl@bad-perfmon:
- shard-dg2: NOTRUN -> [SKIP][250] ([i915#2575]) +14 similar issues
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@v3d/v3d_submit_cl@bad-perfmon.html
* igt@v3d/v3d_submit_csd@bad-bo:
- shard-dg1: NOTRUN -> [SKIP][251] ([i915#2575])
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-13/igt@v3d/v3d_submit_csd@bad-bo.html
- shard-tglu: NOTRUN -> [SKIP][252] ([fdo#109315] / [i915#2575])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-2/igt@v3d/v3d_submit_csd@bad-bo.html
* igt@v3d/v3d_wait_bo@bad-pad:
- shard-rkl: NOTRUN -> [SKIP][253] ([fdo#109315]) +2 similar issues
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@v3d/v3d_wait_bo@bad-pad.html
* igt@vc4/vc4_perfmon@create-single-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][254] ([i915#7711]) +1 similar issue
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-8/igt@vc4/vc4_perfmon@create-single-perfmon.html
* igt@vc4/vc4_purgeable_bo@mark-purgeable:
- shard-dg1: NOTRUN -> [SKIP][255] ([i915#7711])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-17/igt@vc4/vc4_purgeable_bo@mark-purgeable.html
- shard-tglu: NOTRUN -> [SKIP][256] ([i915#2575])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-5/igt@vc4/vc4_purgeable_bo@mark-purgeable.html
* igt@vc4/vc4_tiling@set-get:
- shard-rkl: NOTRUN -> [SKIP][257] ([i915#7711]) +1 similar issue
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@vc4/vc4_tiling@set-get.html
* igt@vc4/vc4_wait_bo@unused-bo-0ns:
- shard-dg2: NOTRUN -> [SKIP][258] ([i915#7711]) +7 similar issues
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-11/igt@vc4/vc4_wait_bo@unused-bo-0ns.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][259] ([i915#7742]) -> [PASS][260]
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-rkl-6/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [ABORT][261] ([i915#7461]) -> [PASS][262]
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-5/igt@gem_create@create-ext-cpu-access-big.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_isolation@preservation-s3@vcs1:
- shard-dg2: [INCOMPLETE][263] -> [PASS][264]
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-5/igt@gem_ctx_isolation@preservation-s3@vcs1.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@gem_ctx_isolation@preservation-s3@vcs1.html
* igt@gem_eio@hibernate:
- shard-tglu: [ABORT][265] ([i915#7975] / [i915#8213] / [i915#8398]) -> [PASS][266]
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-tglu-10/igt@gem_eio@hibernate.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-7/igt@gem_eio@hibernate.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-mtlp: [ABORT][267] ([i915#8503]) -> [PASS][268] +1 similar issue
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-3/igt@gem_eio@in-flight-contexts-1us.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-5/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_eio@reset-stress:
- shard-dg1: [FAIL][269] ([i915#5784]) -> [PASS][270]
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg1-18/igt@gem_eio@reset-stress.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-16/igt@gem_eio@reset-stress.html
* igt@gem_exec_capture@pi@rcs0:
- shard-mtlp: [FAIL][271] ([i915#4475]) -> [PASS][272]
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-1/igt@gem_exec_capture@pi@rcs0.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-5/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: [FAIL][273] ([i915#2842]) -> [PASS][274] +1 similar issue
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-rkl-4/igt@gem_exec_fair@basic-none@bcs0.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-6/igt@gem_exec_fair@basic-none@bcs0.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-dg2: [SKIP][275] ([i915#1937]) -> [PASS][276]
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-5/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-10/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-mtlp: [SKIP][277] ([i915#8403]) -> [PASS][278]
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-6/igt@i915_pm_rc6_residency@rc6-accuracy.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-5/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-dg1: [FAIL][279] ([i915#3591]) -> [PASS][280] +1 similar issue
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-dg1: [SKIP][281] ([i915#1397]) -> [PASS][282] +2 similar issues
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg1-16/igt@i915_pm_rpm@dpms-lpsp.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-19/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg2: [SKIP][283] ([i915#1397]) -> [PASS][284]
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-12/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-dg2: [FAIL][285] ([fdo#103375]) -> [PASS][286] +2 similar issues
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg2-11/igt@i915_pm_rpm@system-suspend-modeset.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg2-8/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][287] ([i915#7790]) -> [PASS][288]
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-snb5/igt@i915_pm_rps@reset.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-snb4/igt@i915_pm_rps@reset.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-2:
- shard-glk: [FAIL][289] ([i915#2521]) -> [PASS][290]
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-glk4/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-2.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-glk7/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-2.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-mtlp: [FAIL][291] ([i915#3743]) -> [PASS][292] +1 similar issue
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][293] ([i915#2346]) -> [PASS][294]
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][295] ([i915#2346]) -> [PASS][296]
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-mtlp: [FAIL][297] ([i915#4767]) -> [PASS][298]
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-2/igt@kms_fbcon_fbt@psr-suspend.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-1/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@dpms-vs-vblank-race@b-hdmi-a1:
- shard-glk: [FAIL][299] ([i915#407]) -> [PASS][300]
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-glk3/igt@kms_flip@dpms-vs-vblank-race@b-hdmi-a1.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-glk4/igt@kms_flip@dpms-vs-vblank-race@b-hdmi-a1.html
* igt@kms_plane_cursor@viewport@pipe-d-edp-1-size-64:
- shard-mtlp: [DMESG-WARN][301] ([i915#1982]) -> [PASS][302]
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-7/igt@kms_plane_cursor@viewport@pipe-d-edp-1-size-64.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-4/igt@kms_plane_cursor@viewport@pipe-d-edp-1-size-64.html
* igt@kms_vblank@pipe-c-query-forked-busy-hang:
- shard-mtlp: [DMESG-WARN][303] -> [PASS][304]
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-3/igt@kms_vblank@pipe-c-query-forked-busy-hang.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-7/igt@kms_vblank@pipe-c-query-forked-busy-hang.html
* igt@perf_pmu@render-node-busy-idle@vcs1:
- shard-dg1: [FAIL][305] ([i915#4349]) -> [PASS][306] +1 similar issue
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-dg1-17/igt@perf_pmu@render-node-busy-idle@vcs1.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-dg1-14/igt@perf_pmu@render-node-busy-idle@vcs1.html
- shard-mtlp: [FAIL][307] ([i915#4349]) -> [PASS][308] +1 similar issue
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-6/igt@perf_pmu@render-node-busy-idle@vcs1.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-7/igt@perf_pmu@render-node-busy-idle@vcs1.html
* igt@sysfs_preempt_timeout@timeout@vecs0:
- shard-mtlp: [TIMEOUT][309] ([i915#8521]) -> [PASS][310]
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-mtlp-5/igt@sysfs_preempt_timeout@timeout@vecs0.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-mtlp-5/igt@sysfs_preempt_timeout@timeout@vecs0.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-tglu: [WARN][311] ([i915#2681]) -> [FAIL][312] ([i915#2681] / [i915#3591])
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-tglu-6/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-tglu-2/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@kms_fbcon_fbt@psr:
- shard-rkl: [SKIP][313] ([fdo#110189] / [i915#3955]) -> [SKIP][314] ([i915#3955])
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13572/shard-rkl-1/igt@kms_fbcon_fbt@psr.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/shard-rkl-4/igt@kms_fbcon_fbt@psr.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1339]: https://gitlab.freedesktop.org/drm/intel/issues/1339
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5889]: https://gitlab.freedesktop.org/drm/intel/issues/5889
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6122]: https://gitlab.freedesktop.org/drm/intel/issues/6122
[i915#6188]: https://gitlab.freedesktop.org/drm/intel/issues/6188
[i915#6228]: https://gitlab.freedesktop.org/drm/intel/issues/6228
[i915#6229]: https://gitlab.freedesktop.org/drm/intel/issues/6229
[i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7886]: https://gitlab.freedesktop.org/drm/intel/issues/7886
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
[i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
[i915#8403]: https://gitlab.freedesktop.org/drm/intel/issues/8403
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8503]: https://gitlab.freedesktop.org/drm/intel/issues/8503
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
[i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8827]: https://gitlab.freedesktop.org/drm/intel/issues/8827
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865
[i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
[i915#9010]: https://gitlab.freedesktop.org/drm/intel/issues/9010
[i915#9051]: https://gitlab.freedesktop.org/drm/intel/issues/9051
[i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7454 -> IGTPW_9674
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13572: f2dfaec0582a995d5e74e5b1896dd6772f5ca9e6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9674: 9674
IGT_7454: 7454
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9674/index.html
[-- Attachment #2: Type: text/html, Size: 101521 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-29 4:40 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
` (3 preceding siblings ...)
2023-08-29 7:37 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
@ 2023-08-29 12:24 ` Kamil Konieczny
2023-08-29 17:18 ` Luben Tuikov
5 siblings, 0 replies; 21+ messages in thread
From: Kamil Konieczny @ 2023-08-29 12:24 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
Hi Vitaly,
On 2023-08-29 at 00:40:06 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e83b5c5ad
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
Add Copyright here.
> +
> +#include <pthread.h>
------------ ^
Sort alphabetically (after amdgpu_drm.h)
Regards,
Kamil
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..1520c34bd 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, no amd_syncobj test')
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-29 4:40 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
` (4 preceding siblings ...)
2023-08-29 12:24 ` [igt-dev] [PATCH] tests/amdgpu: add sync object tests Kamil Konieczny
@ 2023-08-29 17:18 ` Luben Tuikov
5 siblings, 0 replies; 21+ messages in thread
From: Luben Tuikov @ 2023-08-29 17:18 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: Alex Deucher, Christian Koenig
Hi Vitaly,
Good work--thanks for working on this.
Inlined:
On 2023-08-29 00:40, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e83b5c5ad
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +
Should probably include the standard AMD copyright notice.
/* Copyright (C) 2023 Advanced Micro Devices Inc. */
> +#include <pthread.h>
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
In the function above, you don't need "ret"--the compiler optimizes it away
as follows:
static bool
syncobj_timeline_enable(int fd)
{
uint64_t cap = 0;
int r;
r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
return !(r || cap == 0);
}
Or you can use "!!!(r || cap == 0);" if the/a compiler complains.
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
Very nice. :-)
One question: Is it possible we hang indefinitely in
pthread_create()-->syncobj_signal/wait()-->amdgpu_cs_query_fence_status()?
If yes, is there a way to mitigate this and timeout the test, if run
from a nightly script for instance?
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..1520c34bd 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, no amd_syncobj test')
I'd probably print:
'libdrm <= 2.4.97 found, amd_syncobj test not applicable'
to clarify that for libdrm versions less than or equal to the one indicated,
the test while available is not applicable.
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
With these changes applied, this patch is,
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
--
Regards,
Luben
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-30 14:55 vitaly.prosyak
2023-08-30 15:06 ` Luben Tuikov
0 siblings, 1 reply; 21+ messages in thread
From: vitaly.prosyak @ 2023-08-30 14:55 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
v3 : Kamil suggested sort alphabetically includes.
Luben suggested code and meson script improvements.
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e1d80758e
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include <pthread.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+
+ return !(r || cap == 0);
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..ebf52bf38 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-30 14:55 vitaly.prosyak
@ 2023-08-30 15:06 ` Luben Tuikov
0 siblings, 0 replies; 21+ messages in thread
From: Luben Tuikov @ 2023-08-30 15:06 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: Alex Deucher, Christian Koenig
Looks great--thanks! :-)
Regards,
Luben
On 2023-08-30 10:55, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
> v3 : Kamil suggested sort alphabetically includes.
> Luben suggested code and meson script improvements.
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
> Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e1d80758e
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +#include <pthread.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> +
> + return !(r || cap == 0);
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..ebf52bf38 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
--
Regards,
Luben
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-31 0:24 vitaly.prosyak
0 siblings, 0 replies; 21+ messages in thread
From: vitaly.prosyak @ 2023-08-31 0:24 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
v3 : Kamil suggested sort alphabetically includes.
Luben suggested code and meson script improvements.
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e1d80758e
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include <pthread.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+
+ return !(r || cap == 0);
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..ebf52bf38 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-31 3:31 vitaly.prosyak
2023-08-31 13:07 ` Luben Tuikov
0 siblings, 1 reply; 21+ messages in thread
From: vitaly.prosyak @ 2023-08-31 3:31 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
v3 : Kamil suggested sort alphabetically includes.
Luben suggested code and meson script improvements.
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e1d80758e
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include <pthread.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+
+ return !(r || cap == 0);
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..ebf52bf38 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-31 3:31 vitaly.prosyak
@ 2023-08-31 13:07 ` Luben Tuikov
0 siblings, 0 replies; 21+ messages in thread
From: Luben Tuikov @ 2023-08-31 13:07 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: Alex Deucher, Christian Koenig
Looks good.
Regards,
Luben
On 2023-08-30 23:31, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
> v3 : Kamil suggested sort alphabetically includes.
> Luben suggested code and meson script improvements.
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
> Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e1d80758e
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +#include <pthread.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> +
> + return !(r || cap == 0);
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..ebf52bf38 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2023-08-31 13:07 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
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2023-08-29 4:40 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
2023-08-29 4:54 ` [igt-dev] ✗ GitLab.Pipeline: warning for tests/amdgpu: add sync object tests (rev4) Patchwork
2023-08-29 5:24 ` [igt-dev] ✓ CI.xeBAT: success " Patchwork
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2023-08-29 7:37 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2023-08-29 12:24 ` [igt-dev] [PATCH] tests/amdgpu: add sync object tests Kamil Konieczny
2023-08-29 17:18 ` Luben Tuikov
-- strict thread matches above, loose matches on Subject: below --
2023-08-31 3:31 vitaly.prosyak
2023-08-31 13:07 ` Luben Tuikov
2023-08-31 0:24 vitaly.prosyak
2023-08-30 14:55 vitaly.prosyak
2023-08-30 15:06 ` Luben Tuikov
2023-08-22 21:17 vitaly.prosyak
2023-08-23 16:34 ` Kamil Konieczny
2023-08-24 0:42 ` vitaly prosyak
2023-07-02 1:22 vitaly.prosyak
2023-07-03 7:39 ` Kamil Konieczny
2023-07-03 11:15 ` Prosyak, Vitaly
2023-06-13 22:06 vitaly.prosyak
2023-06-14 9:57 ` Christian König
2023-06-14 11:09 ` Kamil Konieczny
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