* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-06-13 22:06 vitaly.prosyak
2023-06-14 9:57 ` Christian König
2023-06-14 11:09 ` Kamil Konieczny
0 siblings, 2 replies; 21+ messages in thread
From: vitaly.prosyak @ 2023-06-13 22:06 UTC (permalink / raw)
To: igt-dev; +Cc: alexander.deucher, michael.strawbridge, christian.koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
tests/amdgpu/amd_syncobj.c | 293 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 294 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..d178c2600
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,293 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+
+#include "igt.h"
+#include "drmtest.h"
+#include "lib/amdgpu/amd_PM4.h" // GFX_COMPUTE_NOP
+#include "lib/amdgpu/amd_sdma.h" // SDMA_NOP
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include "lib/amdgpu/amd_memory.h"
+#include <pthread.h>
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static int
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal,
+ uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE,0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+
+ return r;
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+ int r;
+
+ r = syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+ igt_assert_eq(r, 0);
+
+ return (void *)(long)r;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+ int r;
+
+ r = syncobj_command_submission_helper(sp->device,sp->syncobj_handle, false,
+ sp->point);
+ igt_assert_eq(r, 0);
+
+ return (void *)(long)r;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 0x10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 7fff7602f..7342bb714 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -5,6 +5,7 @@ if libdrm_amdgpu.found()
amdgpu_progs += [ 'amd_abm',
'amd_assr',
'amd_basic',
+ 'amd_syncobj',
'amd_bypass',
'amd_deadlock',
'amd_pci_unplug',
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-06-13 22:06 vitaly.prosyak
@ 2023-06-14 9:57 ` Christian König
2023-06-14 11:09 ` Kamil Konieczny
1 sibling, 0 replies; 21+ messages in thread
From: Christian König @ 2023-06-14 9:57 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: alexander.deucher, michael.strawbridge
Am 14.06.23 um 00:06 schrieb vitaly.prosyak@amd.com:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 293 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 294 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..d178c2600
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,293 @@
> +/* SPDX-License-Identifier: MIT
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> +*/
> +
> +
> +#include "igt.h"
> +#include "drmtest.h"
> +#include "lib/amdgpu/amd_PM4.h" // GFX_COMPUTE_NOP
> +#include "lib/amdgpu/amd_sdma.h" // SDMA_NOP
A long long time ago in a different job comments on preprocessor lines
were extremely frowned on.
Could be that modern compilers doesn't have a problem with that any
more, but I wouldn't bet on it.
Apart from that looks good to me,
Christian.
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +#include "lib/amdgpu/amd_memory.h"
> +#include <pthread.h>
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static int
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal,
> + uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE,0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +
> + return r;
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device,sp->syncobj_handle, false,
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 0x10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 7fff7602f..7342bb714 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -5,6 +5,7 @@ if libdrm_amdgpu.found()
> amdgpu_progs += [ 'amd_abm',
> 'amd_assr',
> 'amd_basic',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_deadlock',
> 'amd_pci_unplug',
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-06-13 22:06 vitaly.prosyak
2023-06-14 9:57 ` Christian König
@ 2023-06-14 11:09 ` Kamil Konieczny
1 sibling, 0 replies; 21+ messages in thread
From: Kamil Konieczny @ 2023-06-14 11:09 UTC (permalink / raw)
To: igt-dev; +Cc: alexander.deucher, michael.strawbridge, christian.koenig
Hi Vitaly,
On 2023-06-13 at 18:06:36 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 293 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 294 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..d178c2600
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,293 @@
> +/* SPDX-License-Identifier: MIT
-- ^^
Should be '//'
See for example tests/device_reset.c
Please use checkpatch.pl from Linux kernel scripts for finding
some problems, you can ignore 'line too long'.
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
----- ^
Delete this, it is replaced by SPDX above and the reason for
using SPDX was to drop such full licence texts.
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
----- ^
> + *
> +*/
-- ^^
Add space before so as to keep '*' aligned.
> +
> +
> +#include "igt.h"
----------- ^
Move igt includes after system ones.
> +#include "drmtest.h"
------------ ^
Sort includes alpabetically (in their sections).
> +#include "lib/amdgpu/amd_PM4.h" // GFX_COMPUTE_NOP
---------------------------------- ^
Maybe better to add comments before ?
> +#include "lib/amdgpu/amd_sdma.h" // SDMA_NOP
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
Put system includes first.
> +#include "lib/amdgpu/amd_memory.h"
----------- ^^
Move to igt include section.
> +#include <pthread.h>
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static int
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
------------------------------------ ^
> + uint32_t syncobj_handle, bool wait_or_signal,
----------------------------------------------------------------- ^
Align it to above amdgpu_device
> + uint64_t point)
Same here, align.
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
-------------------------------------------------------- ^
Add space before ':'
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE,0, &expired);
----------------------------------------------- ^
Space after ","
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
--------------------- ^ ^
> +
> + return r;
Why do you need to return 0 ? imho better make this a void
function.
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> + int r;
> +
> + r = syncobj_command_submission_helper(sp->device,sp->syncobj_handle, false,
-------------------------------------------------------- ^
Space after ","
> + sp->point);
> + igt_assert_eq(r, 0);
> +
> + return (void *)(long)r;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
----------------------------- ^^^^^^^^^^^^^
> + timeout += 0x10000000000; //10s
------------------ ^^^
This is hex and above you use decimal ? Maybe use define or const.
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
------- ^
Add additional tab before, like
igt_subtest("amdgpu_syncobj_timeline")
amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
--------------- ^
drm_close_driver(fd);
Regards,
Kamil
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 7fff7602f..7342bb714 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -5,6 +5,7 @@ if libdrm_amdgpu.found()
> amdgpu_progs += [ 'amd_abm',
> 'amd_assr',
> 'amd_basic',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_deadlock',
> 'amd_pci_unplug',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-07-02 1:22 vitaly.prosyak
2023-07-03 7:39 ` Kamil Konieczny
0 siblings, 1 reply; 21+ messages in thread
From: vitaly.prosyak @ 2023-07-02 1:22 UTC (permalink / raw)
To: igt-dev; +Cc: Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v1->v2. Fixed style issues - Christian.
Fixed formatting issues - Kamil.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Acked-by: Christian Koenig <christian.koenig@amd.com>
Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 266 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..7cab093c9
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <pthread.h>
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 24843de73..02096934d 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
'amd_assr',
'amd_basic',
'amd_bo',
+ 'amd_syncobj',
'amd_bypass',
'amd_color',
'amd_cp_dma_misc',
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-07-02 1:22 vitaly.prosyak
@ 2023-07-03 7:39 ` Kamil Konieczny
2023-07-03 11:15 ` Prosyak, Vitaly
0 siblings, 1 reply; 21+ messages in thread
From: Kamil Konieczny @ 2023-07-03 7:39 UTC (permalink / raw)
To: igt-dev; +Cc: Christian Koenig
Hi Vitaly,
On 2023-07-01 at 21:22:30 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v1->v2. Fixed style issues - Christian.
> Fixed formatting issues - Kamil.
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Acked-by: Christian Koenig <christian.koenig@amd.com>
> Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Please do not merge this until you address GitLab compilation
issue.
Regards,
Kamil
> ---
> tests/amdgpu/amd_syncobj.c | 266 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..7cab093c9
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,266 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <pthread.h>
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 24843de73..02096934d 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
> 'amd_assr',
> 'amd_basic',
> 'amd_bo',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_color',
> 'amd_cp_dma_misc',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-07-03 7:39 ` Kamil Konieczny
@ 2023-07-03 11:15 ` Prosyak, Vitaly
0 siblings, 0 replies; 21+ messages in thread
From: Prosyak, Vitaly @ 2023-07-03 11:15 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev@lists.freedesktop.org; +Cc: Koenig, Christian
[-- Attachment #1: Type: text/plain, Size: 11622 bytes --]
[Public]
Hi Kamil,
Yes, sure,
I will work on this using your suggestion in the previous email.
Thanks, Vitaly
________________________________
From: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Sent: Monday, July 3, 2023 3:39 AM
To: igt-dev@lists.freedesktop.org <igt-dev@lists.freedesktop.org>
Cc: Prosyak, Vitaly <Vitaly.Prosyak@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>
Subject: Re: [PATCH] tests/amdgpu: add sync object tests
Hi Vitaly,
On 2023-07-01 at 21:22:30 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v1->v2. Fixed style issues - Christian.
> Fixed formatting issues - Kamil.
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Acked-by: Christian Koenig <christian.koenig@amd.com>
> Acked-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Please do not merge this until you address GitLab compilation
issue.
Regards,
Kamil
> ---
> tests/amdgpu/amd_syncobj.c | 266 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..7cab093c9
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,266 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <pthread.h>
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 24843de73..02096934d 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
> 'amd_assr',
> 'amd_basic',
> 'amd_bo',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_color',
> 'amd_cp_dma_misc',
> --
> 2.25.1
>
[-- Attachment #2: Type: text/html, Size: 23964 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-22 21:17 vitaly.prosyak
2023-08-23 16:34 ` Kamil Konieczny
0 siblings, 1 reply; 21+ messages in thread
From: vitaly.prosyak @ 2023-08-22 21:17 UTC (permalink / raw)
To: igt-dev
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 1 +
2 files changed, 263 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e83b5c5ad
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+
+#include <pthread.h>
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..1c4f5030b 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
'amd_assr',
'amd_basic',
'amd_bo',
+ 'amd_syncobj',
'amd_bypass',
'amd_color',
'amd_cp_dma_misc',
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-22 21:17 vitaly.prosyak
@ 2023-08-23 16:34 ` Kamil Konieczny
2023-08-24 0:42 ` vitaly prosyak
0 siblings, 1 reply; 21+ messages in thread
From: Kamil Konieczny @ 2023-08-23 16:34 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
Hi vitaly.prosyak,
On 2023-08-22 at 17:17:11 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
This is not building on some CI images, please fix this before merge.
Steps to reproduce:
on some images your test will not build,
to reproduce:
follow links from failed build to find out what container image was used,
for example here: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/47872456
click on failed run to show error log
install podman, enter to igt-tools source dir,
then run script:
POD_IGT=registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian:commit-1af4386ff3086df670e10af3a2bfd89993af3b0a
# search error log for line starting with:
# Using docker image sha256:... for registry.freedesktop.org/... with digest ...
# --------------------------------- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
# copy this string for POD_IGT above
mkdir -p /tmp/igt-build
cp -R * /tmp/igt-build/
sudo podman run -i -t -v /tmp/igt-build/:/opt/builds --privileged ${POD_IGT}
## end of script
now you will have root prompt '#' inside podman image (debian),
enter commands:
# cd /opt/builds
# meson build
# ninja -C build
and you can debug it yourself.
Regards,
Kamil
> tests/amdgpu/meson.build | 1 +
> 2 files changed, 263 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e83b5c5ad
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +
> +#include <pthread.h>
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..1c4f5030b 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
> 'amd_assr',
> 'amd_basic',
> 'amd_bo',
> + 'amd_syncobj',
> 'amd_bypass',
> 'amd_color',
> 'amd_cp_dma_misc',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-23 16:34 ` Kamil Konieczny
@ 2023-08-24 0:42 ` vitaly prosyak
0 siblings, 0 replies; 21+ messages in thread
From: vitaly prosyak @ 2023-08-24 0:42 UTC (permalink / raw)
To: Kamil Konieczny, vitaly.prosyak, igt-dev
Thanks a lot, Kamil for the explanation and useful commands.
I was delayed in dealing with this problem, now I have to finish .
Thanks, Vitaly
On 2023-08-23 12:34, Kamil Konieczny wrote:
> Hi vitaly.prosyak,
> On 2023-08-22 at 17:17:11 -0400, vitaly.prosyak@amd.com wrote:
>> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>>
>> Using worker thread to wait on point and then signal point on other thread.
>> Another test uses a worker thread to signal point and wait on the main
>> thread using amdgpu_cs_syncobj_timeline_wait.
>>
>> The command consists of two chunks :
>> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
>> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
>> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
>> point number .
>>
>> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
>> ---
>> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> This is not building on some CI images, please fix this before merge.
>
> Steps to reproduce:
>
> on some images your test will not build,
> to reproduce:
>
> follow links from failed build to find out what container image was used,
> for example here: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/47872456
> click on failed run to show error log
>
> install podman, enter to igt-tools source dir,
> then run script:
>
> POD_IGT=registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian:commit-1af4386ff3086df670e10af3a2bfd89993af3b0a
> # search error log for line starting with:
> # Using docker image sha256:... for registry.freedesktop.org/... with digest ...
> # --------------------------------- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> # copy this string for POD_IGT above
>
> mkdir -p /tmp/igt-build
> cp -R * /tmp/igt-build/
> sudo podman run -i -t -v /tmp/igt-build/:/opt/builds --privileged ${POD_IGT}
>
> ## end of script
>
> now you will have root prompt '#' inside podman image (debian),
> enter commands:
>
> # cd /opt/builds
> # meson build
> # ninja -C build
>
> and you can debug it yourself.
>
> Regards,
> Kamil
>
>> tests/amdgpu/meson.build | 1 +
>> 2 files changed, 263 insertions(+)
>> create mode 100644 tests/amdgpu/amd_syncobj.c
>>
>> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
>> new file mode 100644
>> index 000000000..e83b5c5ad
>> --- /dev/null
>> +++ b/tests/amdgpu/amd_syncobj.c
>> @@ -0,0 +1,262 @@
>> +// SPDX-License-Identifier: MIT
>> +
>> +#include <pthread.h>
>> +#include <amdgpu.h>
>> +#include <amdgpu_drm.h>
>> +
>> +#include "igt.h"
>> +#include "lib/amdgpu/amd_PM4.h"
>> +#include "lib/amdgpu/amd_sdma.h"
>> +#include "lib/amdgpu/amd_memory.h"
>> +
>> +struct syncobj_point {
>> + amdgpu_device_handle device;
>> + uint32_t syncobj_handle;
>> + uint64_t point;
>> +};
>> +
>> +
>> +static bool
>> +syncobj_timeline_enable(int fd)
>> +{
>> + int r;
>> + bool ret = false;
>> + uint64_t cap = 0;
>> +
>> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
>> + if (r || cap == 0)
>> + return ret;
>> + ret = true;
>> +
>> + return ret;
>> +}
>> +
>> +static void
>> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
>> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
>> +{
>> + amdgpu_context_handle context_handle;
>> + amdgpu_bo_handle ib_result_handle;
>> + void *ib_result_cpu;
>> + uint64_t ib_result_mc_address;
>> + struct drm_amdgpu_cs_chunk chunks[2];
>> + struct drm_amdgpu_cs_chunk_data chunk_data;
>> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
>> + struct amdgpu_cs_fence fence_status;
>> + amdgpu_bo_list_handle bo_list;
>> + amdgpu_va_handle va_handle;
>> + uint32_t expired;
>> + int i, r;
>> + uint64_t seq_no;
>> + uint32_t *ptr;
>> +
>> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
>> + AMDGPU_GEM_DOMAIN_GTT, 0,
>> + &ib_result_handle, &ib_result_cpu,
>> + &ib_result_mc_address, &va_handle);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
>> + igt_assert_eq(r, 0);
>> +
>> + ptr = ib_result_cpu;
>> +
>> + for (i = 0; i < 16; ++i)
>> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
>> +
>> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
>> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
>> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
>> + chunk_data.ib_data._pad = 0;
>> + chunk_data.ib_data.va_start = ib_result_mc_address;
>> + chunk_data.ib_data.ib_bytes = 16 * 4;
>> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
>> + chunk_data.ib_data.ip_instance = 0;
>> + chunk_data.ib_data.ring = 0;
>> + chunk_data.ib_data.flags = 0;
>> +
>> + chunks[1].chunk_id = wait_or_signal ?
>> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
>> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
>> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
>> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
>> + syncobj_data.handle = syncobj_handle;
>> + syncobj_data.point = point;
>> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
>> +
>> + r = amdgpu_cs_submit_raw(device_handle,
>> + context_handle,
>> + bo_list,
>> + 2,
>> + chunks,
>> + &seq_no);
>> + igt_assert_eq(r, 0);
>> +
>> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
>> + fence_status.context = context_handle;
>> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
>> + fence_status.ip_instance = 0;
>> + fence_status.ring = 0;
>> + fence_status.fence = seq_no;
>> +
>> + r = amdgpu_cs_query_fence_status(&fence_status,
>> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
>> + igt_assert_eq(r, 0);
>> +
>> + r = amdgpu_bo_list_destroy(bo_list);
>> + igt_assert_eq(r, 0);
>> +
>> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
>> + ib_result_mc_address, 4096);
>> +
>> + r = amdgpu_cs_ctx_free(context_handle);
>> + igt_assert_eq(r, 0);
>> +}
>> +
>> +static void *
>> +syncobj_wait(void *data)
>> +{
>> + struct syncobj_point *sp = (struct syncobj_point *)data;
>> +
>> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
>> + sp->point);
>> +
>> + return (void *)0;
>> +}
>> +
>> +static void *
>> +syncobj_signal(void *data)
>> +{
>> + struct syncobj_point *sp = (struct syncobj_point *)data;
>> +
>> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
>> + sp->point);
>> +
>> + return (void *)0;
>> +}
>> +
>> +static void
>> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
>> +{
>> + static pthread_t wait_thread;
>> + static pthread_t signal_thread;
>> + static pthread_t c_thread;
>> + struct syncobj_point sp1, sp2, sp3;
>> + uint32_t syncobj_handle;
>> + uint64_t payload;
>> + uint64_t wait_point, signal_point;
>> + uint64_t timeout;
>> + struct timespec tp;
>> + int r, sync_fd;
>> + void *tmp, *tmp2;
>> +
>> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
>> + igt_assert_eq(r, 0);
>> +
>> + // wait on point 5
>> + sp1.syncobj_handle = syncobj_handle;
>> + sp1.device = device_handle;
>> + sp1.point = 5;
>> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
>> + igt_assert_eq(r, 0);
>> +
>> + // signal on point 10
>> + sp2.syncobj_handle = syncobj_handle;
>> + sp2.device = device_handle;
>> + sp2.point = 10;
>> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
>> + igt_assert_eq(r, 0);
>> +
>> + r = pthread_join(signal_thread, &tmp);
>> + igt_assert_eq(r, 0);
>> +
>> + r = pthread_join(wait_thread, &tmp2);
>> + igt_assert_eq(r, 0);
>> +
>> + //query timeline payload
>> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> + &payload, 1);
>> + igt_assert_eq(r, 0);
>> + igt_assert_eq(payload, 10);
>> +
>> + //signal on point 16
>> + sp3.syncobj_handle = syncobj_handle;
>> + sp3.device = device_handle;
>> + sp3.point = 16;
>> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
>> + igt_assert_eq(r, 0);
>> +
>> + //CPU wait on point 16
>> + wait_point = 16;
>> + timeout = 0;
>> + clock_gettime(CLOCK_MONOTONIC, &tp);
>> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
>> + timeout += 10000000000; //10s
>> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
>> + &wait_point, 1, timeout,
>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>> + NULL);
>> +
>> + igt_assert_eq(r, 0);
>> + r = pthread_join(c_thread, &tmp);
>> + igt_assert_eq(r, 0);
>> +
>> + // export point 16 and import to point 18
>> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
>> + 16,
>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>> + &sync_fd);
>> + igt_assert_eq(r, 0);
>> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
>> + 18, sync_fd);
>> + igt_assert_eq(r, 0);
>> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> + &payload, 1);
>> + igt_assert_eq(r, 0);
>> + igt_assert_eq(payload, 18);
>> +
>> + // CPU signal on point 20
>> + signal_point = 20;
>> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
>> + &signal_point, 1);
>> + igt_assert_eq(r, 0);
>> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> + &payload, 1);
>> + igt_assert_eq(r, 0);
>> + igt_assert_eq(payload, 20);
>> +
>> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
>> + igt_assert_eq(r, 0);
>> +
>> +}
>> +
>> +igt_main
>> +{
>> + amdgpu_device_handle device;
>> + int fd = -1;
>> +
>> + igt_fixture {
>> + uint32_t major, minor;
>> + int err;
>> +
>> + fd = drm_open_driver(DRIVER_AMDGPU);
>> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
>> + igt_require(err == 0);
>> + igt_require(syncobj_timeline_enable(fd));
>> + igt_info("Initialized amdgpu, driver version %d.%d\n",
>> + major, minor);
>> +
>> + }
>> +
>> + igt_subtest("amdgpu_syncobj_timeline")
>> + amdgpu_syncobj_timeline(device);
>> +
>> + igt_fixture {
>> + amdgpu_device_deinitialize(device);
>> + close(fd);
>> + }
>> +}
>> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
>> index 6032a38e8..1c4f5030b 100644
>> --- a/tests/amdgpu/meson.build
>> +++ b/tests/amdgpu/meson.build
>> @@ -6,6 +6,7 @@ if libdrm_amdgpu.found()
>> 'amd_assr',
>> 'amd_basic',
>> 'amd_bo',
>> + 'amd_syncobj',
>> 'amd_bypass',
>> 'amd_color',
>> 'amd_cp_dma_misc',
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-29 4:40 vitaly.prosyak
2023-08-29 12:24 ` Kamil Konieczny
2023-08-29 17:18 ` Luben Tuikov
0 siblings, 2 replies; 21+ messages in thread
From: vitaly.prosyak @ 2023-08-29 4:40 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e83b5c5ad
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+
+#include <pthread.h>
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ bool ret = false;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+ if (r || cap == 0)
+ return ret;
+ ret = true;
+
+ return ret;
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..1520c34bd 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, no amd_syncobj test')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-29 4:40 vitaly.prosyak
@ 2023-08-29 12:24 ` Kamil Konieczny
2023-08-29 17:18 ` Luben Tuikov
1 sibling, 0 replies; 21+ messages in thread
From: Kamil Konieczny @ 2023-08-29 12:24 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
Hi Vitaly,
On 2023-08-29 at 00:40:06 -0400, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e83b5c5ad
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
Add Copyright here.
> +
> +#include <pthread.h>
------------ ^
Sort alphabetically (after amdgpu_drm.h)
Regards,
Kamil
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..1520c34bd 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, no amd_syncobj test')
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-29 4:40 vitaly.prosyak
2023-08-29 12:24 ` Kamil Konieczny
@ 2023-08-29 17:18 ` Luben Tuikov
1 sibling, 0 replies; 21+ messages in thread
From: Luben Tuikov @ 2023-08-29 17:18 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: Alex Deucher, Christian Koenig
Hi Vitaly,
Good work--thanks for working on this.
Inlined:
On 2023-08-29 00:40, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e83b5c5ad
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +
Should probably include the standard AMD copyright notice.
/* Copyright (C) 2023 Advanced Micro Devices Inc. */
> +#include <pthread.h>
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + bool ret = false;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> + if (r || cap == 0)
> + return ret;
> + ret = true;
> +
> + return ret;
> +}
In the function above, you don't need "ret"--the compiler optimizes it away
as follows:
static bool
syncobj_timeline_enable(int fd)
{
uint64_t cap = 0;
int r;
r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
return !(r || cap == 0);
}
Or you can use "!!!(r || cap == 0);" if the/a compiler complains.
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
Very nice. :-)
One question: Is it possible we hang indefinitely in
pthread_create()-->syncobj_signal/wait()-->amdgpu_cs_query_fence_status()?
If yes, is there a way to mitigate this and timeout the test, if run
from a nightly script for instance?
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..1520c34bd 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, no amd_syncobj test')
I'd probably print:
'libdrm <= 2.4.97 found, amd_syncobj test not applicable'
to clarify that for libdrm versions less than or equal to the one indicated,
the test while available is not applicable.
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
With these changes applied, this patch is,
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
--
Regards,
Luben
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-30 14:55 vitaly.prosyak
2023-08-30 15:06 ` Luben Tuikov
` (4 more replies)
0 siblings, 5 replies; 21+ messages in thread
From: vitaly.prosyak @ 2023-08-30 14:55 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
v3 : Kamil suggested sort alphabetically includes.
Luben suggested code and meson script improvements.
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e1d80758e
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include <pthread.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+
+ return !(r || cap == 0);
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..ebf52bf38 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-30 14:55 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
@ 2023-08-30 15:06 ` Luben Tuikov
2023-08-30 16:15 ` [igt-dev] ✗ GitLab.Pipeline: warning for tests/amdgpu: add sync object tests (rev5) Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 21+ messages in thread
From: Luben Tuikov @ 2023-08-30 15:06 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: Alex Deucher, Christian Koenig
Looks great--thanks! :-)
Regards,
Luben
On 2023-08-30 10:55, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
> v3 : Kamil suggested sort alphabetically includes.
> Luben suggested code and meson script improvements.
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
> Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e1d80758e
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +#include <pthread.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> +
> + return !(r || cap == 0);
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..ebf52bf38 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
--
Regards,
Luben
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: warning for tests/amdgpu: add sync object tests (rev5)
2023-08-30 14:55 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
2023-08-30 15:06 ` Luben Tuikov
@ 2023-08-30 16:15 ` Patchwork
2023-08-30 16:47 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-08-30 16:15 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
== Series Details ==
Series: tests/amdgpu: add sync object tests (rev5)
URL : https://patchwork.freedesktop.org/series/119304/
State : warning
== Summary ==
Pipeline status: FAILED.
see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/973642 for the overview.
build-containers:build-debian-arm64 has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48246328):
time="2023-08-30T16:09:25Z" level=fatal msg="Get https://registry.freedesktop.org/v2/gfx-ci/igt-ci-tags/build-debian-arm64/blobs/sha256:7360075a71dacfc66f0b49b3271b9a459904dbe51c5760efac48fe52da27946c: dial tcp 147.75.198.156:443: i/o timeout"
Building!
STEP 1: FROM debian:buster
Getting image source signatures
Copying blob sha256:d6b7393fb4f375905c31c483d81ce2a2905f88aba8cb198874da2b54035bc41d
Copying config sha256:de08540e8ff0e470ff7956df4bed403725a5f45c186e9bf495da5344ff8fbe84
Writing manifest to image destination
Storing signatures
STEP 2: RUN apt-get update
error running container: error creating container for [/bin/sh -c apt-get update]: time="2023-08-30T16:09:30Z" level=warning msg="signal: killed"
time="2023-08-30T16:09:30Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
: exit status 1
Error: error building at STEP "RUN apt-get update": error while running runtime: exit status 1
section_end:1693411770:step_script
section_start:1693411770:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1693411771:cleanup_file_variables
ERROR: Job failed: exit code 1
== Logs ==
For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/973642
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for tests/amdgpu: add sync object tests (rev5)
2023-08-30 14:55 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
2023-08-30 15:06 ` Luben Tuikov
2023-08-30 16:15 ` [igt-dev] ✗ GitLab.Pipeline: warning for tests/amdgpu: add sync object tests (rev5) Patchwork
@ 2023-08-30 16:47 ` Patchwork
2023-08-30 17:02 ` [igt-dev] ✓ CI.xeBAT: " Patchwork
2023-08-31 1:05 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-08-30 16:47 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 4525 bytes --]
== Series Details ==
Series: tests/amdgpu: add sync object tests (rev5)
URL : https://patchwork.freedesktop.org/series/119304/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13577 -> IGTPW_9682
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/index.html
Participating hosts (39 -> 37)
------------------------------
Missing (2): fi-kbl-soraka fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_9682 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5:
- bat-adlp-11: NOTRUN -> [ABORT][1] ([i915#8668])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-1:
- fi-rkl-11600: [PASS][2] -> [FAIL][3] ([fdo#103375])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-1.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-1.html
* igt@kms_psr@cursor_plane_move:
- bat-rplp-1: NOTRUN -> [ABORT][4] ([i915#8469] / [i915#8668] / [i915#9243])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/bat-rplp-1/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_page_flip:
- bat-rplp-1: NOTRUN -> [SKIP][5] ([i915#1072])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/bat-rplp-1/igt@kms_psr@primary_page_flip.html
#### Possible fixes ####
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-a-dp-5:
- bat-adlp-11: [DMESG-FAIL][6] ([i915#6868]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/bat-adlp-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-a-dp-5.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/bat-adlp-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-a-dp-5.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-5:
- bat-adlp-11: [FAIL][8] ([i915#9047]) -> [PASS][9] +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/bat-adlp-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-5.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/bat-adlp-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-5.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [ABORT][10] ([i915#8442] / [i915#8668]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#485]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/485
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8469]: https://gitlab.freedesktop.org/drm/intel/issues/8469
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#9047]: https://gitlab.freedesktop.org/drm/intel/issues/9047
[i915#9243]: https://gitlab.freedesktop.org/drm/intel/issues/9243
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7459 -> IGTPW_9682
CI-20190529: 20190529
CI_DRM_13577: bb585492db95d4cc7fe3797523ed2bbf5c621d37 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9682: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/index.html
IGT_7459: 7459
Testlist changes
----------------
-igt@xe_exec_invalid_va@invalid-va
-igt@xe_exec_invalid_va@invalid-va-fault
-igt@xe_exec_invalid_va@invalid-va-fault-scratch
-igt@xe_exec_invalid_va@invalid-va-scratch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/index.html
[-- Attachment #2: Type: text/html, Size: 5301 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] ✓ CI.xeBAT: success for tests/amdgpu: add sync object tests (rev5)
2023-08-30 14:55 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
` (2 preceding siblings ...)
2023-08-30 16:47 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-08-30 17:02 ` Patchwork
2023-08-31 1:05 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-08-30 17:02 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 2947 bytes --]
== Series Details ==
Series: tests/amdgpu: add sync object tests (rev5)
URL : https://patchwork.freedesktop.org/series/119304/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_7459_BAT -> XEIGTPW_9682_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in XEIGTPW_9682_BAT that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- bat-adlp-7: [FAIL][1] ([Intel XE#480]) -> [PASS][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7459/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9682/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
* igt@xe_exec_reset@cm-close-fd-no-exec:
- {bat-pvc-2}: [DMESG-WARN][3] ([Intel XE#526]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7459/bat-pvc-2/igt@xe_exec_reset@cm-close-fd-no-exec.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9682/bat-pvc-2/igt@xe_exec_reset@cm-close-fd-no-exec.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/255
[Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480
[Intel XE#483]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/483
[Intel XE#526]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/526
[Intel XE#531]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/531
[Intel XE#532]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/532
[Intel XE#533]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/533
[Intel XE#535]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/535
[Intel XE#536]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/536
[Intel XE#537]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/537
[Intel XE#538]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/538
[Intel XE#539]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/539
[Intel XE#540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/540
[Intel XE#541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/541
Build changes
-------------
* IGT: IGT_7459 -> IGTPW_9682
* Linux: xe-340-c77796cf84361b4716839141f2e48de2bf7f4bd5 -> xe-346-2c728d192daf742a57749f4fdfee53d8d7b75817
IGTPW_9682: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/index.html
IGT_7459: 7459
xe-340-c77796cf84361b4716839141f2e48de2bf7f4bd5: c77796cf84361b4716839141f2e48de2bf7f4bd5
xe-346-2c728d192daf742a57749f4fdfee53d8d7b75817: 2c728d192daf742a57749f4fdfee53d8d7b75817
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^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-31 0:24 vitaly.prosyak
0 siblings, 0 replies; 21+ messages in thread
From: vitaly.prosyak @ 2023-08-31 0:24 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
v3 : Kamil suggested sort alphabetically includes.
Luben suggested code and meson script improvements.
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e1d80758e
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include <pthread.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+
+ return !(r || cap == 0);
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..ebf52bf38 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for tests/amdgpu: add sync object tests (rev5)
2023-08-30 14:55 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
` (3 preceding siblings ...)
2023-08-30 17:02 ` [igt-dev] ✓ CI.xeBAT: " Patchwork
@ 2023-08-31 1:05 ` Patchwork
4 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-08-31 1:05 UTC (permalink / raw)
To: vitaly.prosyak; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 75766 bytes --]
== Series Details ==
Series: tests/amdgpu: add sync object tests (rev5)
URL : https://patchwork.freedesktop.org/series/119304/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13577_full -> IGTPW_9682_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_9682_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_9682_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/index.html
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_9682_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_cursor@overlay@pipe-b-edp-1-size-256:
- shard-mtlp: [PASS][1] -> [FAIL][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-2/igt@kms_plane_cursor@overlay@pipe-b-edp-1-size-256.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-8/igt@kms_plane_cursor@overlay@pipe-b-edp-1-size-256.html
Known issues
------------
Here are the changes found in IGTPW_9682_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8411]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-5/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg1: NOTRUN -> [SKIP][4] ([i915#8411])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-12/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@drm_fdinfo@busy-idle@bcs0:
- shard-dg2: NOTRUN -> [SKIP][5] ([i915#8414]) +9 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@drm_fdinfo@busy-idle@bcs0.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][6] ([i915#8414]) +4 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-17/igt@drm_fdinfo@most-busy-check-all@bcs0.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [PASS][7] -> [FAIL][8] ([i915#7742])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@feature_discovery@display-4x:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#1839])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-8/igt@feature_discovery@display-4x.html
* igt@gem_ccs@block-multicopy-inplace:
- shard-dg1: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#5325])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-14/igt@gem_ccs@block-multicopy-inplace.html
* igt@gem_ctx_persistence@hang:
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#8555])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-3/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-dg1: NOTRUN -> [SKIP][12] ([i915#8555])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-15/igt@gem_ctx_persistence@heartbeat-stop.html
* igt@gem_ctx_persistence@legacy-engines-cleanup:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-snb4/igt@gem_ctx_persistence@legacy-engines-cleanup.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#5882]) +9 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg1: NOTRUN -> [SKIP][15] ([i915#280])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-12/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglu: NOTRUN -> [SKIP][16] ([i915#280])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-7/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][17] ([i915#8898])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-snb2/igt@gem_eio@unwedge-stress.html
- shard-dg1: [PASS][18] -> [FAIL][19] ([i915#5784])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg1-19/igt@gem_eio@unwedge-stress.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-18/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@hog:
- shard-mtlp: NOTRUN -> [SKIP][20] ([i915#4812])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-6/igt@gem_exec_balancer@hog.html
* igt@gem_exec_capture@capture-invisible@lmem0:
- shard-dg2: NOTRUN -> [SKIP][21] ([i915#6334]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-6/igt@gem_exec_capture@capture-invisible@lmem0.html
* igt@gem_exec_fair@basic-none-vip:
- shard-dg1: NOTRUN -> [SKIP][22] ([i915#3539] / [i915#4852])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-16/igt@gem_exec_fair@basic-none-vip.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-rkl: NOTRUN -> [FAIL][23] ([i915#2842])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-7/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][24] -> [FAIL][25] ([i915#2842]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-rkl: [PASS][26] -> [FAIL][27] ([i915#2842])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-rkl-7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglu: [PASS][28] -> [FAIL][29] ([i915#2842])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fence@submit67:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#4812])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-12/igt@gem_exec_fence@submit67.html
* igt@gem_exec_flush@basic-uc-ro-default:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#3539] / [i915#4852]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-11/igt@gem_exec_flush@basic-uc-ro-default.html
* igt@gem_exec_reloc@basic-scanout:
- shard-mtlp: NOTRUN -> [SKIP][32] ([i915#3281]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-5/igt@gem_exec_reloc@basic-scanout.html
* igt@gem_exec_reloc@basic-wc-gtt-noreloc:
- shard-dg1: NOTRUN -> [SKIP][33] ([i915#3281]) +5 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-19/igt@gem_exec_reloc@basic-wc-gtt-noreloc.html
* igt@gem_exec_schedule@preempt-queue-contexts:
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#4812])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-14/igt@gem_exec_schedule@preempt-queue-contexts.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg1: [PASS][35] -> [ABORT][36] ([i915#7975] / [i915#8213])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg1-13/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@gem_fence_thrash@bo-write-verify-none:
- shard-dg1: NOTRUN -> [SKIP][37] ([i915#4860])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-14/igt@gem_fence_thrash@bo-write-verify-none.html
* igt@gem_fence_thrash@bo-write-verify-x:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#4860])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@gem_fence_thrash@bo-write-verify-x.html
* igt@gem_media_vme:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#284])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-1/igt@gem_media_vme.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-mtlp: NOTRUN -> [SKIP][40] ([i915#4077])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-4/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_mmap_wc@bad-object:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#4083]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-3/igt@gem_mmap_wc@bad-object.html
* igt@gem_mmap_wc@copy:
- shard-dg1: NOTRUN -> [SKIP][42] ([i915#4083]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-14/igt@gem_mmap_wc@copy.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#3282])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-1/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gem_partial_pwrite_pread@write-snoop:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#3282])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-5/igt@gem_partial_pwrite_pread@write-snoop.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- shard-dg1: NOTRUN -> [SKIP][45] ([i915#3282]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-18/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gem_pxp@display-protected-crc:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4270]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-2/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-dg1: NOTRUN -> [SKIP][47] ([i915#4270])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-15/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@gem_render_copy@yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#5190]) +4 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-5/igt@gem_render_copy@yf-tiled.html
* igt@gem_set_tiling_vs_gtt:
- shard-mtlp: NOTRUN -> [SKIP][49] ([i915#4079]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-3/igt@gem_set_tiling_vs_gtt.html
* igt@gem_set_tiling_vs_pwrite:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#4079])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-11/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_tiled_swapping@non-threaded:
- shard-dg1: NOTRUN -> [SKIP][51] ([i915#4077]) +5 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-12/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#3297]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-1/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@mmap-offset-banned@gtt:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#3297]) +3 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-3/igt@gem_userptr_blits@mmap-offset-banned@gtt.html
* igt@gem_userptr_blits@nohangcheck:
- shard-mtlp: [PASS][54] -> [FAIL][55] ([i915#6268])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-8/igt@gem_userptr_blits@nohangcheck.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-6/igt@gem_userptr_blits@nohangcheck.html
* igt@gem_userptr_blits@relocations:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#3281]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-12/igt@gem_userptr_blits@relocations.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#3297])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-4/igt@gem_userptr_blits@unsync-overlap.html
- shard-dg1: NOTRUN -> [SKIP][58] ([i915#3297])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-17/igt@gem_userptr_blits@unsync-overlap.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][59] ([i915#2724])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-snb1/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_render_linear_blits:
- shard-dg2: NOTRUN -> [SKIP][60] ([fdo#109289]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@gen3_render_linear_blits.html
* igt@gen7_exec_parse@basic-rejected:
- shard-dg1: NOTRUN -> [SKIP][61] ([fdo#109289]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-13/igt@gen7_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-snb: NOTRUN -> [SKIP][62] ([fdo#109271]) +257 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-snb6/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@bb-chained:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#2856])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-3/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@bb-start-out:
- shard-dg1: NOTRUN -> [SKIP][64] ([i915#2527]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-17/igt@gen9_exec_parse@bb-start-out.html
* igt@i915_fb_tiling:
- shard-mtlp: NOTRUN -> [SKIP][65] ([i915#4881])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-7/igt@i915_fb_tiling.html
* igt@i915_module_load@load:
- shard-dg1: NOTRUN -> [SKIP][66] ([i915#6227])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-16/igt@i915_module_load@load.html
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#6227])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-apl2/igt@i915_module_load@load.html
* igt@i915_pm_backlight@fade-with-suspend:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#5354] / [i915#7561])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-1/igt@i915_pm_backlight@fade-with-suspend.html
* igt@i915_pm_lpsp@screens-disabled:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#8430])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-8/igt@i915_pm_lpsp@screens-disabled.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-dg1: NOTRUN -> [FAIL][70] ([i915#3591])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@fences-dpms:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#4077]) +6 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-12/igt@i915_pm_rpm@fences-dpms.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#1397])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-5/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [PASS][73] -> [SKIP][74] ([i915#1397]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-11/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rps@thresholds@gt0:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#8925]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-6/igt@i915_pm_rps@thresholds@gt0.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-4-mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#8502] / [i915#8709]) +11 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-4-mc_ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#8502]) +3 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [FAIL][78] ([i915#8247]) +3 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-1/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html
* igt@kms_async_flips@crc@pipe-b-hdmi-a-3:
- shard-dg1: NOTRUN -> [FAIL][79] ([i915#8247]) +3 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-13/igt@kms_async_flips@crc@pipe-b-hdmi-a-3.html
* igt@kms_async_flips@invalid-async-flip:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#6228])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg1: NOTRUN -> [SKIP][81] ([i915#1769] / [i915#3555])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-15/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][82] ([fdo#111614]) +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-1/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-dg1: NOTRUN -> [SKIP][83] ([i915#4538] / [i915#5286]) +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-17/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][84] ([i915#3638]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-17/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][85] ([fdo#111614])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-2/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-mtlp: [PASS][86] -> [FAIL][87] ([i915#3743])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-mtlp: NOTRUN -> [FAIL][88] ([i915#3743])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#4538] / [i915#5190]) +4 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-6/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-dg1: NOTRUN -> [SKIP][90] ([fdo#111615])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-19/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-rkl: NOTRUN -> [SKIP][91] ([fdo#110723])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
- shard-dg1: NOTRUN -> [SKIP][92] ([i915#4538])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-16/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_joiner@2x-modeset:
- shard-dg1: NOTRUN -> [SKIP][93] ([i915#2705])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-16/igt@kms_big_joiner@2x-modeset.html
* igt@kms_ccs@pipe-a-bad-aux-stride-4_tiled_mtl_rc_ccs:
- shard-apl: NOTRUN -> [SKIP][94] ([fdo#109271]) +8 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-apl2/igt@kms_ccs@pipe-a-bad-aux-stride-4_tiled_mtl_rc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-dg1: NOTRUN -> [SKIP][95] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095]) +3 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-16/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#3886])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-apl4/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs:
- shard-dg1: NOTRUN -> [SKIP][97] ([i915#3689] / [i915#5354] / [i915#6095]) +8 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-18/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_mc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][98] ([i915#6095]) +3 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-1/igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][99] ([i915#3689] / [i915#5354] / [i915#6095])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-3/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_mtl_rc_ccs_cc:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#5354]) +3 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-7/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_mtl_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#3689] / [i915#3886] / [i915#5354]) +3 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-dg2: NOTRUN -> [SKIP][102] ([i915#3689] / [i915#5354]) +14 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-12/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc:
- shard-tglu: NOTRUN -> [SKIP][103] ([i915#5354] / [i915#6095])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-4/igt@kms_ccs@pipe-d-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_mtl_mc_ccs:
- shard-dg1: NOTRUN -> [SKIP][104] ([i915#5354] / [i915#6095]) +9 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-18/igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_mtl_mc_ccs.html
* igt@kms_cdclk@mode-transition@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [SKIP][105] ([i915#4087] / [i915#7213]) +3 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-12/igt@kms_cdclk@mode-transition@pipe-a-dp-2.html
* igt@kms_chamelium_color@ctm-0-50:
- shard-mtlp: NOTRUN -> [SKIP][106] ([fdo#111827])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-3/igt@kms_chamelium_color@ctm-0-50.html
* igt@kms_chamelium_color@ctm-green-to-red:
- shard-dg2: NOTRUN -> [SKIP][107] ([fdo#111827]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-6/igt@kms_chamelium_color@ctm-green-to-red.html
* igt@kms_chamelium_color@ctm-limited-range:
- shard-dg1: NOTRUN -> [SKIP][108] ([fdo#111827])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-15/igt@kms_chamelium_color@ctm-limited-range.html
* igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#7828]) +5 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-11/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-tglu: NOTRUN -> [SKIP][110] ([i915#7828]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-6/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
- shard-dg1: NOTRUN -> [SKIP][111] ([i915#7828]) +5 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-14/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
* igt@kms_color@deep-color:
- shard-rkl: NOTRUN -> [SKIP][112] ([i915#3555])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-1/igt@kms_color@deep-color.html
- shard-tglu: NOTRUN -> [SKIP][113] ([i915#3555])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-2/igt@kms_color@deep-color.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#7118]) +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-2/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#3299])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-5/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@legacy:
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#7118])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-1/igt@kms_content_protection@legacy.html
- shard-dg1: NOTRUN -> [SKIP][117] ([i915#7116])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-19/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@srm@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [TIMEOUT][118] ([i915#7173])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-12/igt@kms_content_protection@srm@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-rkl: NOTRUN -> [SKIP][119] ([fdo#109279] / [i915#3359])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-4/igt@kms_cursor_crc@cursor-offscreen-512x170.html
- shard-dg1: NOTRUN -> [SKIP][120] ([i915#3359]) +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-17/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-mtlp: NOTRUN -> [SKIP][121] ([i915#3359])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-5/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#3359]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-3/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-dg1: NOTRUN -> [SKIP][123] ([i915#3555]) +3 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-12/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#3555]) +4 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-8/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-rkl: NOTRUN -> [SKIP][125] ([fdo#111825])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
- shard-tglu: NOTRUN -> [SKIP][126] ([fdo#109274])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-mtlp: [PASS][127] -> [FAIL][128] ([i915#8248])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
- shard-dg2: NOTRUN -> [SKIP][129] ([fdo#109274] / [i915#5354]) +3 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-1/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-dg1: NOTRUN -> [SKIP][130] ([fdo#111767] / [fdo#111825])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-16/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][131] -> [FAIL][132] ([i915#2346])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-tglu: [PASS][133] -> [FAIL][134] ([i915#2346])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-tglu-8/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#4103] / [i915#4213])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
- shard-dg1: NOTRUN -> [SKIP][136] ([i915#4103] / [i915#4213])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-13/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][137] ([i915#9226]) +1 similar issue
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-6/igt@kms_dirtyfb@dirtyfb-ioctl@drrs-hdmi-a-2.html
* igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][138] ([i915#9227])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-1.html
* igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][139] ([i915#9227])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-6/igt@kms_dirtyfb@dirtyfb-ioctl@fbc-hdmi-a-2.html
* igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#9226]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-1.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-dg2: NOTRUN -> [SKIP][141] ([i915#8588])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-1/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_draw_crc@draw-method-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#8812])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-2/igt@kms_draw_crc@draw-method-mmap-wc.html
- shard-dg1: NOTRUN -> [SKIP][143] ([i915#8812])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-13/igt@kms_draw_crc@draw-method-mmap-wc.html
* igt@kms_dsc@dsc-basic:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#3555] / [i915#3840])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-5/igt@kms_dsc@dsc-basic.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-dg2: NOTRUN -> [SKIP][145] ([fdo#109274]) +2 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-12/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-snb: NOTRUN -> [SKIP][146] ([fdo#109271] / [fdo#111767])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-snb4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-tglu: NOTRUN -> [SKIP][147] ([fdo#109274] / [i915#3637])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-8/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1:
- shard-mtlp: [PASS][148] -> [DMESG-WARN][149] ([i915#1982])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-4/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-4/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@a-hdmi-a3:
- shard-dg2: [PASS][150] -> [FAIL][151] ([fdo#103375]) +2 similar issues
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg2-1/igt@kms_flip@flip-vs-suspend@a-hdmi-a3.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-5/igt@kms_flip@flip-vs-suspend@a-hdmi-a3.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][152] ([i915#2587] / [i915#2672]) +2 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-13/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#2672]) +3 similar issues
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#5354]) +30 similar issues
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][155] ([i915#8708]) +8 similar issues
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][156] ([i915#8708]) +13 similar issues
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-dg1: NOTRUN -> [SKIP][157] ([i915#5439])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][158] ([i915#3458]) +14 similar issues
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
- shard-dg1: NOTRUN -> [SKIP][159] ([i915#3458]) +11 similar issues
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-pwrite:
- shard-tglu: NOTRUN -> [SKIP][160] ([fdo#109280]) +3 similar issues
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][161] ([fdo#111825] / [i915#1825]) +5 similar issues
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
- shard-mtlp: NOTRUN -> [SKIP][162] ([i915#1825]) +6 similar issues
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
- shard-dg1: NOTRUN -> [SKIP][163] ([fdo#111825]) +21 similar issues
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-19/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-dg1: NOTRUN -> [SKIP][164] ([i915#3555] / [i915#8228])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-12/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-toggle:
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#3555] / [i915#8228]) +2 similar issues
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-5/igt@kms_hdr@static-toggle.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-dg2: NOTRUN -> [SKIP][166] ([i915#4816])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
- shard-mtlp: NOTRUN -> [SKIP][167] ([fdo#109289]) +1 similar issue
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-1/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][168] ([i915#8292])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][169] ([i915#8292])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-4/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][170] ([i915#8292])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-18/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][171] ([i915#5176]) +3 similar issues
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-1/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][172] ([i915#5176]) +3 similar issues
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-c-edp-1.html
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][173] ([i915#5176]) +11 similar issues
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-16/igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-d-hdmi-a-4.html
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][174] ([i915#5176]) +3 similar issues
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-4/igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#5235]) +19 similar issues
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-11/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][176] ([i915#5235]) +7 similar issues
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][177] ([i915#5235]) +19 similar issues
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-19/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#6524] / [i915#6805])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-12/igt@kms_prime@basic-crc-hybrid.html
- shard-dg1: NOTRUN -> [SKIP][179] ([i915#6524])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-12/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][180] ([i915#658]) +1 similar issue
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][181] ([fdo#111068] / [i915#658])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-18/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr@primary_render:
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#1072]) +2 similar issues
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-17/igt@kms_psr@primary_render.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#1072]) +5 similar issues
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-1/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-rkl: NOTRUN -> [SKIP][184] ([fdo#111615] / [i915#5289])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
- shard-tglu: NOTRUN -> [SKIP][185] ([fdo#111615] / [i915#5289])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_selftest@drm_damage:
- shard-dg2: NOTRUN -> [SKIP][186] ([i915#8661]) +1 similar issue
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-11/igt@kms_selftest@drm_damage.html
- shard-dg1: NOTRUN -> [SKIP][187] ([i915#8661]) +1 similar issue
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-18/igt@kms_selftest@drm_damage.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#3555] / [i915#4098])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-7/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_vblank@pipe-a-query-busy-hang:
- shard-apl: [PASS][189] -> [SKIP][190] ([fdo#109271])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-apl3/igt@kms_vblank@pipe-a-query-busy-hang.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-apl3/igt@kms_vblank@pipe-a-query-busy-hang.html
- shard-glk: [PASS][191] -> [SKIP][192] ([fdo#109271])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-glk2/igt@kms_vblank@pipe-a-query-busy-hang.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-glk2/igt@kms_vblank@pipe-a-query-busy-hang.html
* igt@kms_vblank@pipe-a-query-idle-hang:
- shard-snb: [PASS][193] -> [ABORT][194] ([i915#8865])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-snb6/igt@kms_vblank@pipe-a-query-idle-hang.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-snb7/igt@kms_vblank@pipe-a-query-idle-hang.html
* igt@kms_writeback@writeback-check-output:
- shard-dg1: NOTRUN -> [SKIP][195] ([i915#2437])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-15/igt@kms_writeback@writeback-check-output.html
* igt@perf@global-sseu-config:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#7387])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@perf@global-sseu-config.html
* igt@perf@mi-rpc:
- shard-dg1: NOTRUN -> [SKIP][197] ([i915#2434])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-19/igt@perf@mi-rpc.html
* igt@perf@per-context-mode-unprivileged:
- shard-rkl: NOTRUN -> [SKIP][198] ([i915#2435])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-1/igt@perf@per-context-mode-unprivileged.html
- shard-dg1: NOTRUN -> [SKIP][199] ([fdo#109289] / [i915#2433])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-14/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@all-busy-idle-check-all:
- shard-dg2: [PASS][200] -> [FAIL][201] ([i915#5234])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg2-8/igt@perf_pmu@all-busy-idle-check-all.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-12/igt@perf_pmu@all-busy-idle-check-all.html
- shard-dg1: [PASS][202] -> [FAIL][203] ([i915#5234])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg1-13/igt@perf_pmu@all-busy-idle-check-all.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-14/igt@perf_pmu@all-busy-idle-check-all.html
- shard-mtlp: [PASS][204] -> [FAIL][205] ([i915#5234])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-5/igt@perf_pmu@all-busy-idle-check-all.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-2/igt@perf_pmu@all-busy-idle-check-all.html
* igt@perf_pmu@busy-idle@vcs0:
- shard-dg2: [PASS][206] -> [FAIL][207] ([i915#4349]) +10 similar issues
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg2-2/igt@perf_pmu@busy-idle@vcs0.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-5/igt@perf_pmu@busy-idle@vcs0.html
- shard-dg1: [PASS][208] -> [FAIL][209] ([i915#4349]) +5 similar issues
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg1-13/igt@perf_pmu@busy-idle@vcs0.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-16/igt@perf_pmu@busy-idle@vcs0.html
- shard-mtlp: [PASS][210] -> [FAIL][211] ([i915#4349]) +3 similar issues
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-6/igt@perf_pmu@busy-idle@vcs0.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-3/igt@perf_pmu@busy-idle@vcs0.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg1: NOTRUN -> [SKIP][212] ([i915#8516])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-19/igt@perf_pmu@rc6-all-gts.html
* igt@perf_pmu@rc6-suspend:
- shard-snb: NOTRUN -> [DMESG-WARN][213] ([i915#8841]) +1 similar issue
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-snb1/igt@perf_pmu@rc6-suspend.html
* igt@prime_vgem@basic-write:
- shard-mtlp: NOTRUN -> [SKIP][214] ([i915#3708])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-5/igt@prime_vgem@basic-write.html
* igt@sysfs_heartbeat_interval@mixed@ccs0:
- shard-mtlp: [PASS][215] -> [ABORT][216] ([i915#8552])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-1/igt@sysfs_heartbeat_interval@mixed@ccs0.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-3/igt@sysfs_heartbeat_interval@mixed@ccs0.html
* igt@sysfs_heartbeat_interval@mixed@vecs0:
- shard-mtlp: [PASS][217] -> [FAIL][218] ([i915#1731])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-1/igt@sysfs_heartbeat_interval@mixed@vecs0.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-3/igt@sysfs_heartbeat_interval@mixed@vecs0.html
* igt@v3d/v3d_perfmon@get-values-invalid-perfmon:
- shard-dg1: NOTRUN -> [SKIP][219] ([i915#2575]) +6 similar issues
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-17/igt@v3d/v3d_perfmon@get-values-invalid-perfmon.html
* igt@v3d/v3d_submit_cl@bad-multisync-out-sync:
- shard-dg2: NOTRUN -> [SKIP][220] ([i915#2575]) +6 similar issues
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-2/igt@v3d/v3d_submit_cl@bad-multisync-out-sync.html
* igt@v3d/v3d_submit_cl@valid-multisync-submission:
- shard-rkl: NOTRUN -> [SKIP][221] ([fdo#109315])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-4/igt@v3d/v3d_submit_cl@valid-multisync-submission.html
* igt@v3d/v3d_submit_csd@bad-in-sync:
- shard-tglu: NOTRUN -> [SKIP][222] ([fdo#109315] / [i915#2575])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-9/igt@v3d/v3d_submit_csd@bad-in-sync.html
* igt@v3d/v3d_wait_bo@map-bo-0ns:
- shard-mtlp: NOTRUN -> [SKIP][223] ([i915#2575]) +2 similar issues
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-5/igt@v3d/v3d_wait_bo@map-bo-0ns.html
* igt@vc4/vc4_label_bo@set-kernel-name:
- shard-dg1: NOTRUN -> [SKIP][224] ([i915#7711]) +4 similar issues
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-16/igt@vc4/vc4_label_bo@set-kernel-name.html
* igt@vc4/vc4_wait_seqno@bad-seqno-1ns:
- shard-dg2: NOTRUN -> [SKIP][225] ([i915#7711]) +6 similar issues
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-11/igt@vc4/vc4_wait_seqno@bad-seqno-1ns.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][226] ([i915#7742]) -> [PASS][227]
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [FAIL][228] ([i915#6268]) -> [PASS][229]
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-rkl-7/igt@gem_ctx_exec@basic-nohangcheck.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@engines-hostile@vcs0:
- shard-mtlp: [FAIL][230] ([i915#2410]) -> [PASS][231] +2 similar issues
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-3/igt@gem_ctx_persistence@engines-hostile@vcs0.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-2/igt@gem_ctx_persistence@engines-hostile@vcs0.html
* igt@gem_exec_capture@pi@rcs0:
- shard-rkl: [TIMEOUT][232] -> [PASS][233]
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-rkl-4/igt@gem_exec_capture@pi@rcs0.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-4/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_capture@pi@vcs1:
- shard-mtlp: [FAIL][234] ([i915#4475] / [i915#7765]) -> [PASS][235] +1 similar issue
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-7/igt@gem_exec_capture@pi@vcs1.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-4/igt@gem_exec_capture@pi@vcs1.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-rkl: [FAIL][236] ([i915#2842]) -> [PASS][237]
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-rkl-7/igt@gem_exec_fair@basic-none-share@rcs0.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-1/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [FAIL][238] ([i915#2842]) -> [PASS][239]
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-glk3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-glk9/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_whisper@basic-fds-priority-all:
- shard-tglu: [INCOMPLETE][240] ([i915#6755] / [i915#7392]) -> [PASS][241]
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-tglu-7/igt@gem_exec_whisper@basic-fds-priority-all.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-9/igt@gem_exec_whisper@basic-fds-priority-all.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [DMESG-WARN][242] ([i915#4936] / [i915#5493]) -> [PASS][243]
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg2-12/igt@gem_lmem_swapping@smem-oom@lmem0.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-5/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_hangman@engine-engine-error@vcs0:
- shard-mtlp: [FAIL][244] ([i915#7069]) -> [PASS][245]
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-4/igt@i915_hangman@engine-engine-error@vcs0.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-7/igt@i915_hangman@engine-engine-error@vcs0.html
* igt@i915_pm_dc@dc9-dpms:
- shard-tglu: [SKIP][246] ([i915#4281]) -> [PASS][247]
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-tglu-7/igt@i915_pm_dc@dc9-dpms.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-9/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-dg1: [SKIP][248] ([i915#1937]) -> [PASS][249]
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg1-13/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-19/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-rkl: [SKIP][250] ([i915#1397]) -> [PASS][251] +4 similar issues
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-6/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-mtlp: [FAIL][252] ([i915#3743]) -> [PASS][253] +1 similar issue
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0:
- shard-mtlp: [FAIL][254] ([i915#5138]) -> [PASS][255] +1 similar issue
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-1/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-7/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][256] ([i915#2346]) -> [PASS][257]
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size:
- shard-apl: [INCOMPLETE][258] ([i915#2295]) -> [PASS][259]
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-apl7/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-apl6/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
- shard-glk: [FAIL][260] ([i915#79]) -> [PASS][261]
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-dg2: [FAIL][262] ([i915#6880]) -> [PASS][263]
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@perf_pmu@busy-double-start@ccs2:
- shard-dg2: [FAIL][264] ([i915#4349]) -> [PASS][265]
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg2-12/igt@perf_pmu@busy-double-start@ccs2.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-11/igt@perf_pmu@busy-double-start@ccs2.html
* igt@perf_pmu@busy-double-start@vcs1:
- shard-mtlp: [FAIL][266] ([i915#4349]) -> [PASS][267] +2 similar issues
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-1/igt@perf_pmu@busy-double-start@vcs1.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-3/igt@perf_pmu@busy-double-start@vcs1.html
* igt@sysfs_heartbeat_interval@nopreempt@vcs0:
- shard-mtlp: [FAIL][268] ([i915#6015]) -> [PASS][269] +2 similar issues
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-5/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-8/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
* igt@sysfs_heartbeat_interval@precise@vecs0:
- shard-mtlp: [FAIL][270] ([i915#8332]) -> [PASS][271]
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-1/igt@sysfs_heartbeat_interval@precise@vecs0.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-7/igt@sysfs_heartbeat_interval@precise@vecs0.html
* igt@sysfs_preempt_timeout@timeout@vecs0:
- shard-mtlp: [TIMEOUT][272] ([i915#8521]) -> [PASS][273]
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-3/igt@sysfs_preempt_timeout@timeout@vecs0.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-3/igt@sysfs_preempt_timeout@timeout@vecs0.html
#### Warnings ####
* igt@kms_async_flips@crc@pipe-a-edp-1:
- shard-mtlp: [DMESG-FAIL][274] ([i915#1982] / [i915#8561]) -> [DMESG-FAIL][275] ([i915#8561])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-2/igt@kms_async_flips@crc@pipe-a-edp-1.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-7/igt@kms_async_flips@crc@pipe-a-edp-1.html
* igt@kms_content_protection@mei_interface:
- shard-rkl: [SKIP][276] ([fdo#109300]) -> [SKIP][277] ([i915#7118])
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-rkl-7/igt@kms_content_protection@mei_interface.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-4/igt@kms_content_protection@mei_interface.html
- shard-dg1: [SKIP][278] ([fdo#109300]) -> [SKIP][279] ([i915#7116])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg1-18/igt@kms_content_protection@mei_interface.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-15/igt@kms_content_protection@mei_interface.html
- shard-tglu: [SKIP][280] ([fdo#109300]) -> [SKIP][281] ([i915#6944] / [i915#7116] / [i915#7118])
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-tglu-10/igt@kms_content_protection@mei_interface.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-tglu-9/igt@kms_content_protection@mei_interface.html
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][282] ([i915#7118] / [i915#7162]) -> [SKIP][283] ([i915#7118]) +1 similar issue
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg2-12/igt@kms_content_protection@type1.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg2-10/igt@kms_content_protection@type1.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-mtlp: [FAIL][284] ([i915#2346]) -> [DMESG-FAIL][285] ([i915#1982] / [i915#2017] / [i915#5954])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-mtlp-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-mtlp-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][286] ([i915#3955]) -> [SKIP][287] ([fdo#110189] / [i915#3955])
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-rkl-4/igt@kms_fbcon_fbt@psr-suspend.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-rkl: [SKIP][288] ([fdo#109285]) -> [SKIP][289] ([fdo#109285] / [i915#4098])
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-rkl-6/igt@kms_force_connector_basic@force-load-detect.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-1/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][290] ([i915#4816]) -> [SKIP][291] ([i915#4070] / [i915#4816])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_psr@cursor_plane_move:
- shard-dg1: [SKIP][292] ([i915#1072] / [i915#4078]) -> [SKIP][293] ([i915#1072]) +1 similar issue
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13577/shard-dg1-18/igt@kms_psr@cursor_plane_move.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/shard-dg1-19/igt@kms_psr@cursor_plane_move.html
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882
[i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
[i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6228]: https://gitlab.freedesktop.org/drm/intel/issues/6228
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7765]: https://gitlab.freedesktop.org/drm/intel/issues/7765
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8332]: https://gitlab.freedesktop.org/drm/intel/issues/8332
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8430]: https://gitlab.freedesktop.org/drm/intel/issues/8430
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
[i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521
[i915#8552]: https://gitlab.freedesktop.org/drm/intel/issues/8552
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865
[i915#8898]: https://gitlab.freedesktop.org/drm/intel/issues/8898
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#9226]: https://gitlab.freedesktop.org/drm/intel/issues/9226
[i915#9227]: https://gitlab.freedesktop.org/drm/intel/issues/9227
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7459 -> IGTPW_9682
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13577: bb585492db95d4cc7fe3797523ed2bbf5c621d37 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9682: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/index.html
IGT_7459: 7459
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9682/index.html
[-- Attachment #2: Type: text/html, Size: 91780 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH] tests/amdgpu: add sync object tests
@ 2023-08-31 3:31 vitaly.prosyak
2023-08-31 13:07 ` Luben Tuikov
0 siblings, 1 reply; 21+ messages in thread
From: vitaly.prosyak @ 2023-08-31 3:31 UTC (permalink / raw)
To: igt-dev; +Cc: Alex Deucher, Luben Tuikov, Christian Koenig
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Using worker thread to wait on point and then signal point on other thread.
Another test uses a worker thread to signal point and wait on the main
thread using amdgpu_cs_syncobj_timeline_wait.
The command consists of two chunks :
1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
point number .
v2 : Kamil helped with podman script to fix the build
failure when drmlib version < 2.4.97
v3 : Kamil suggested sort alphabetically includes.
Luben suggested code and meson script improvements.
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
tests/amdgpu/meson.build | 5 +
2 files changed, 267 insertions(+)
create mode 100644 tests/amdgpu/amd_syncobj.c
diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
new file mode 100644
index 000000000..e1d80758e
--- /dev/null
+++ b/tests/amdgpu/amd_syncobj.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include <pthread.h>
+
+#include "igt.h"
+#include "lib/amdgpu/amd_PM4.h"
+#include "lib/amdgpu/amd_sdma.h"
+#include "lib/amdgpu/amd_memory.h"
+
+struct syncobj_point {
+ amdgpu_device_handle device;
+ uint32_t syncobj_handle;
+ uint64_t point;
+};
+
+
+static bool
+syncobj_timeline_enable(int fd)
+{
+ int r;
+ uint64_t cap = 0;
+
+ r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
+
+ return !(r || cap == 0);
+}
+
+static void
+syncobj_command_submission_helper(amdgpu_device_handle device_handle,
+ uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
+{
+ amdgpu_context_handle context_handle;
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ struct drm_amdgpu_cs_chunk chunks[2];
+ struct drm_amdgpu_cs_chunk_data chunk_data;
+ struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+ struct amdgpu_cs_fence fence_status;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ uint32_t expired;
+ int i, r;
+ uint64_t seq_no;
+ uint32_t *ptr;
+
+ r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ &ib_result_handle, &ib_result_cpu,
+ &ib_result_mc_address, &va_handle);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
+ igt_assert_eq(r, 0);
+
+ ptr = ib_result_cpu;
+
+ for (i = 0; i < 16; ++i)
+ ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
+
+ chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+ chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+ chunk_data.ib_data._pad = 0;
+ chunk_data.ib_data.va_start = ib_result_mc_address;
+ chunk_data.ib_data.ib_bytes = 16 * 4;
+ chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ chunk_data.ib_data.ip_instance = 0;
+ chunk_data.ib_data.ring = 0;
+ chunk_data.ib_data.flags = 0;
+
+ chunks[1].chunk_id = wait_or_signal ?
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+ chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+ syncobj_data.handle = syncobj_handle;
+ syncobj_data.point = point;
+ syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+ r = amdgpu_cs_submit_raw(device_handle,
+ context_handle,
+ bo_list,
+ 2,
+ chunks,
+ &seq_no);
+ igt_assert_eq(r, 0);
+
+ memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+ fence_status.context = context_handle;
+ fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
+ fence_status.ip_instance = 0;
+ fence_status.ring = 0;
+ fence_status.fence = seq_no;
+
+ r = amdgpu_cs_query_fence_status(&fence_status,
+ AMDGPU_TIMEOUT_INFINITE, 0, &expired);
+ igt_assert_eq(r, 0);
+
+ r = amdgpu_bo_list_destroy(bo_list);
+ igt_assert_eq(r, 0);
+
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ ib_result_mc_address, 4096);
+
+ r = amdgpu_cs_ctx_free(context_handle);
+ igt_assert_eq(r, 0);
+}
+
+static void *
+syncobj_wait(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void *
+syncobj_signal(void *data)
+{
+ struct syncobj_point *sp = (struct syncobj_point *)data;
+
+ syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
+ sp->point);
+
+ return (void *)0;
+}
+
+static void
+amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
+{
+ static pthread_t wait_thread;
+ static pthread_t signal_thread;
+ static pthread_t c_thread;
+ struct syncobj_point sp1, sp2, sp3;
+ uint32_t syncobj_handle;
+ uint64_t payload;
+ uint64_t wait_point, signal_point;
+ uint64_t timeout;
+ struct timespec tp;
+ int r, sync_fd;
+ void *tmp, *tmp2;
+
+ r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+ igt_assert_eq(r, 0);
+
+ // wait on point 5
+ sp1.syncobj_handle = syncobj_handle;
+ sp1.device = device_handle;
+ sp1.point = 5;
+ r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+ igt_assert_eq(r, 0);
+
+ // signal on point 10
+ sp2.syncobj_handle = syncobj_handle;
+ sp2.device = device_handle;
+ sp2.point = 10;
+ r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(signal_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ r = pthread_join(wait_thread, &tmp2);
+ igt_assert_eq(r, 0);
+
+ //query timeline payload
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 10);
+
+ //signal on point 16
+ sp3.syncobj_handle = syncobj_handle;
+ sp3.device = device_handle;
+ sp3.point = 16;
+ r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+ igt_assert_eq(r, 0);
+
+ //CPU wait on point 16
+ wait_point = 16;
+ timeout = 0;
+ clock_gettime(CLOCK_MONOTONIC, &tp);
+ timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+ timeout += 10000000000; //10s
+ r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+ &wait_point, 1, timeout,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ NULL);
+
+ igt_assert_eq(r, 0);
+ r = pthread_join(c_thread, &tmp);
+ igt_assert_eq(r, 0);
+
+ // export point 16 and import to point 18
+ r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+ 16,
+ DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+ &sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+ 18, sync_fd);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 18);
+
+ // CPU signal on point 20
+ signal_point = 20;
+ r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+ &signal_point, 1);
+ igt_assert_eq(r, 0);
+ r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+ &payload, 1);
+ igt_assert_eq(r, 0);
+ igt_assert_eq(payload, 20);
+
+ r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+ igt_assert_eq(r, 0);
+
+}
+
+igt_main
+{
+ amdgpu_device_handle device;
+ int fd = -1;
+
+ igt_fixture {
+ uint32_t major, minor;
+ int err;
+
+ fd = drm_open_driver(DRIVER_AMDGPU);
+ err = amdgpu_device_initialize(fd, &major, &minor, &device);
+ igt_require(err == 0);
+ igt_require(syncobj_timeline_enable(fd));
+ igt_info("Initialized amdgpu, driver version %d.%d\n",
+ major, minor);
+
+ }
+
+ igt_subtest("amdgpu_syncobj_timeline")
+ amdgpu_syncobj_timeline(device);
+
+ igt_fixture {
+ amdgpu_device_deinitialize(device);
+ close(fd);
+ }
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 6032a38e8..ebf52bf38 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
'amd_mall',
'amd_odm',
]
+ if libdrm_amdgpu.version().version_compare('> 2.4.97')
+ amdgpu_progs +=[ 'amd_syncobj', ]
+ else
+ warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
+ endif
amdgpu_deps += libdrm_amdgpu
endif
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH] tests/amdgpu: add sync object tests
2023-08-31 3:31 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
@ 2023-08-31 13:07 ` Luben Tuikov
0 siblings, 0 replies; 21+ messages in thread
From: Luben Tuikov @ 2023-08-31 13:07 UTC (permalink / raw)
To: vitaly.prosyak, igt-dev; +Cc: Alex Deucher, Christian Koenig
Looks good.
Regards,
Luben
On 2023-08-30 23:31, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> Using worker thread to wait on point and then signal point on other thread.
> Another test uses a worker thread to signal point and wait on the main
> thread using amdgpu_cs_syncobj_timeline_wait.
>
> The command consists of two chunks :
> 1. AMDGPU_CHUNK_ID_IB uses GFX_COMPUTE_NOP or SDMA_NOP.
> 2. The second chunk is AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
> or AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL which has the
> point number .
>
> v2 : Kamil helped with podman script to fix the build
> failure when drmlib version < 2.4.97
> v3 : Kamil suggested sort alphabetically includes.
> Luben suggested code and meson script improvements.
>
> Cc: Luben Tuikov <luben.tuikov@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
> Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
> tests/amdgpu/amd_syncobj.c | 262 +++++++++++++++++++++++++++++++++++++
> tests/amdgpu/meson.build | 5 +
> 2 files changed, 267 insertions(+)
> create mode 100644 tests/amdgpu/amd_syncobj.c
>
> diff --git a/tests/amdgpu/amd_syncobj.c b/tests/amdgpu/amd_syncobj.c
> new file mode 100644
> index 000000000..e1d80758e
> --- /dev/null
> +++ b/tests/amdgpu/amd_syncobj.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + */
> +
> +#include <amdgpu.h>
> +#include <amdgpu_drm.h>
> +#include <pthread.h>
> +
> +#include "igt.h"
> +#include "lib/amdgpu/amd_PM4.h"
> +#include "lib/amdgpu/amd_sdma.h"
> +#include "lib/amdgpu/amd_memory.h"
> +
> +struct syncobj_point {
> + amdgpu_device_handle device;
> + uint32_t syncobj_handle;
> + uint64_t point;
> +};
> +
> +
> +static bool
> +syncobj_timeline_enable(int fd)
> +{
> + int r;
> + uint64_t cap = 0;
> +
> + r = drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &cap);
> +
> + return !(r || cap == 0);
> +}
> +
> +static void
> +syncobj_command_submission_helper(amdgpu_device_handle device_handle,
> + uint32_t syncobj_handle, bool wait_or_signal, uint64_t point)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct drm_amdgpu_cs_chunk chunks[2];
> + struct drm_amdgpu_cs_chunk_data chunk_data;
> + struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> + struct amdgpu_cs_fence fence_status;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + uint32_t expired;
> + int i, r;
> + uint64_t seq_no;
> + uint32_t *ptr;
> +
> + r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0,
> + &ib_result_handle, &ib_result_cpu,
> + &ib_result_mc_address, &va_handle);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, &bo_list);
> + igt_assert_eq(r, 0);
> +
> + ptr = ib_result_cpu;
> +
> + for (i = 0; i < 16; ++i)
> + ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP : SDMA_NOP;
> +
> + chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> + chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> + chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> + chunk_data.ib_data._pad = 0;
> + chunk_data.ib_data.va_start = ib_result_mc_address;
> + chunk_data.ib_data.ib_bytes = 16 * 4;
> + chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + chunk_data.ib_data.ip_instance = 0;
> + chunk_data.ib_data.ring = 0;
> + chunk_data.ib_data.flags = 0;
> +
> + chunks[1].chunk_id = wait_or_signal ?
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> + chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> + chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> + syncobj_data.handle = syncobj_handle;
> + syncobj_data.point = point;
> + syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> + r = amdgpu_cs_submit_raw(device_handle,
> + context_handle,
> + bo_list,
> + 2,
> + chunks,
> + &seq_no);
> + igt_assert_eq(r, 0);
> +
> + memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> + fence_status.context = context_handle;
> + fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : AMDGPU_HW_IP_DMA;
> + fence_status.ip_instance = 0;
> + fence_status.ring = 0;
> + fence_status.fence = seq_no;
> +
> + r = amdgpu_cs_query_fence_status(&fence_status,
> + AMDGPU_TIMEOUT_INFINITE, 0, &expired);
> + igt_assert_eq(r, 0);
> +
> + r = amdgpu_bo_list_destroy(bo_list);
> + igt_assert_eq(r, 0);
> +
> + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> + ib_result_mc_address, 4096);
> +
> + r = amdgpu_cs_ctx_free(context_handle);
> + igt_assert_eq(r, 0);
> +}
> +
> +static void *
> +syncobj_wait(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, true,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void *
> +syncobj_signal(void *data)
> +{
> + struct syncobj_point *sp = (struct syncobj_point *)data;
> +
> + syncobj_command_submission_helper(sp->device, sp->syncobj_handle, false,
> + sp->point);
> +
> + return (void *)0;
> +}
> +
> +static void
> +amdgpu_syncobj_timeline(amdgpu_device_handle device_handle)
> +{
> + static pthread_t wait_thread;
> + static pthread_t signal_thread;
> + static pthread_t c_thread;
> + struct syncobj_point sp1, sp2, sp3;
> + uint32_t syncobj_handle;
> + uint64_t payload;
> + uint64_t wait_point, signal_point;
> + uint64_t timeout;
> + struct timespec tp;
> + int r, sync_fd;
> + void *tmp, *tmp2;
> +
> + r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> + // wait on point 5
> + sp1.syncobj_handle = syncobj_handle;
> + sp1.device = device_handle;
> + sp1.point = 5;
> + r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> + igt_assert_eq(r, 0);
> +
> + // signal on point 10
> + sp2.syncobj_handle = syncobj_handle;
> + sp2.device = device_handle;
> + sp2.point = 10;
> + r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(signal_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + r = pthread_join(wait_thread, &tmp2);
> + igt_assert_eq(r, 0);
> +
> + //query timeline payload
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 10);
> +
> + //signal on point 16
> + sp3.syncobj_handle = syncobj_handle;
> + sp3.device = device_handle;
> + sp3.point = 16;
> + r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> + igt_assert_eq(r, 0);
> +
> + //CPU wait on point 16
> + wait_point = 16;
> + timeout = 0;
> + clock_gettime(CLOCK_MONOTONIC, &tp);
> + timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> + timeout += 10000000000; //10s
> + r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> + &wait_point, 1, timeout,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + NULL);
> +
> + igt_assert_eq(r, 0);
> + r = pthread_join(c_thread, &tmp);
> + igt_assert_eq(r, 0);
> +
> + // export point 16 and import to point 18
> + r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> + 16,
> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> + &sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> + 18, sync_fd);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 18);
> +
> + // CPU signal on point 20
> + signal_point = 20;
> + r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> + &signal_point, 1);
> + igt_assert_eq(r, 0);
> + r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> + &payload, 1);
> + igt_assert_eq(r, 0);
> + igt_assert_eq(payload, 20);
> +
> + r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> + igt_assert_eq(r, 0);
> +
> +}
> +
> +igt_main
> +{
> + amdgpu_device_handle device;
> + int fd = -1;
> +
> + igt_fixture {
> + uint32_t major, minor;
> + int err;
> +
> + fd = drm_open_driver(DRIVER_AMDGPU);
> + err = amdgpu_device_initialize(fd, &major, &minor, &device);
> + igt_require(err == 0);
> + igt_require(syncobj_timeline_enable(fd));
> + igt_info("Initialized amdgpu, driver version %d.%d\n",
> + major, minor);
> +
> + }
> +
> + igt_subtest("amdgpu_syncobj_timeline")
> + amdgpu_syncobj_timeline(device);
> +
> + igt_fixture {
> + amdgpu_device_deinitialize(device);
> + close(fd);
> + }
> +}
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 6032a38e8..ebf52bf38 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -37,6 +37,11 @@ if libdrm_amdgpu.found()
> 'amd_mall',
> 'amd_odm',
> ]
> + if libdrm_amdgpu.version().version_compare('> 2.4.97')
> + amdgpu_progs +=[ 'amd_syncobj', ]
> + else
> + warning('libdrm <= 2.4.97 found, amd_syncobj test not applicable')
> + endif
> amdgpu_deps += libdrm_amdgpu
> endif
>
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2023-08-31 13:07 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
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2023-08-30 14:55 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
2023-08-30 15:06 ` Luben Tuikov
2023-08-30 16:15 ` [igt-dev] ✗ GitLab.Pipeline: warning for tests/amdgpu: add sync object tests (rev5) Patchwork
2023-08-30 16:47 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
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2023-08-31 3:31 [igt-dev] [PATCH] tests/amdgpu: add sync object tests vitaly.prosyak
2023-08-31 13:07 ` Luben Tuikov
2023-08-31 0:24 vitaly.prosyak
2023-08-29 4:40 vitaly.prosyak
2023-08-29 12:24 ` Kamil Konieczny
2023-08-29 17:18 ` Luben Tuikov
2023-08-22 21:17 vitaly.prosyak
2023-08-23 16:34 ` Kamil Konieczny
2023-08-24 0:42 ` vitaly prosyak
2023-07-02 1:22 vitaly.prosyak
2023-07-03 7:39 ` Kamil Konieczny
2023-07-03 11:15 ` Prosyak, Vitaly
2023-06-13 22:06 vitaly.prosyak
2023-06-14 9:57 ` Christian König
2023-06-14 11:09 ` Kamil Konieczny
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