From: "Hajda, Andrzej" <andrzej.hajda@intel.com>
To: "Grzegorzek, Dominik" <dominik.grzegorzek@intel.com>,
"igt-dev@lists.freedesktop.org" <igt-dev@lists.freedesktop.org>
Cc: "Kempczynski, Zbigniew" <zbigniew.kempczynski@intel.com>,
"Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com>,
"Manszewski, Christoph" <christoph.manszewski@intel.com>,
"kamil.konieczny@linux.intel.com"
<kamil.konieczny@linux.intel.com>
Subject: Re: [PATCH v3 4/4] lib/gpgpu_shader: add support for Xe3 platforms
Date: Fri, 22 Nov 2024 15:24:19 +0100 [thread overview]
Message-ID: <85949d12-d5bc-431e-a972-9fa9977444e9@intel.com> (raw)
In-Reply-To: <f52bb270341789ee54eee040c7783719d7990ed8.camel@intel.com>
W dniu 22.11.2024 o 15:11, Grzegorzek, Dominik pisze:
> On Thu, 2024-11-21 at 18:12 +0100, Andrzej Hajda wrote:
>> Xe3 platforms disallow indirect load/store addressing. Surface descriptor
>> must be passed in 2DBlock payload. Use for it inline data passed from
>> thread dispatcher.
>>
>> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
>> ---
>> lib/gpgpu_shader.c | 20 +++++++++++++-------
>> lib/iga64_generated_codes.c | 13 ++++++++-----
>> lib/iga64_macros.h | 37 +++++++++++++++++++++++++++++++++----
>> 3 files changed, 54 insertions(+), 16 deletions(-)
>>
>> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
>> index 518423158880..27e8be6b37e2 100644
>> --- a/lib/gpgpu_shader.c
>> +++ b/lib/gpgpu_shader.c
>> @@ -210,6 +210,17 @@ __xehp_gpgpu_execfunc(struct intel_bb *ibb,
>> engine | I915_EXEC_NO_RELOC, false);
>> }
>>
>> +static void gpgpu_alloc_gpu_addr(int fd, struct intel_buf *target)
>> +{
>> + uint64_t ahnd;
>> +
>> + ahnd = intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
>> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
>> + target->addr.offset = intel_allocator_alloc(ahnd, target->handle,
>> + target->surface[0].size, 0);
>> + intel_allocator_close(ahnd);
>> +}
>> +
>> /**
>> * gpgpu_shader_exec:
>> * @ibb: pointer to initialized intel_bb
>> @@ -231,17 +242,12 @@ void gpgpu_shader_exec(struct intel_bb *ibb,
>> struct gpgpu_shader *sip,
>> uint64_t ring, bool explicit_engine)
>> {
>> - uint64_t ahnd;
>> -
>> igt_require(shdr->gen_ver >= SUPPORTED_GEN_VER);
>> igt_assert(ibb->size >= PAGE_SIZE);
>> igt_assert(ibb->ptr == ibb->batch);
>>
>> - ahnd = intel_allocator_open_full(ibb->fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
>> - ALLOC_STRATEGY_LOW_TO_HIGH, 0);
>> - target->addr.offset = intel_allocator_alloc(ahnd, target->handle,
>> - target->surface[0].size, 0);
>> - intel_allocator_close(ahnd);
>> + if (target->addr.offset == INTEL_BUF_INVALID_ADDRESS)
>> + gpgpu_alloc_gpu_addr(ibb->fd, target);
> You could define gpgpu_alloc_gpu_addr in a previous patch.
Ups, I apparently messed it up when I was merging the late fixup, will
move it to prev patch.
Regards
Andrzej
>>
>> if (shdr->gen_ver >= 1250)
>> __xehp_gpgpu_execfunc(ibb, target, x_dim, y_dim, shdr, sip,
>> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
>> index 04015b0b6d29..a12135e7dbfd 100644
>> --- a/lib/iga64_generated_codes.c
>> +++ b/lib/iga64_generated_codes.c
>> @@ -3,7 +3,7 @@
>>
>> #include "gpgpu_shader.h"
>>
>> -#define MD5_SUM_IGA64_ASMS da66be3cf9bec819a61429de75943011
>> +#define MD5_SUM_IGA64_ASMS 7b1db60d1de46cf35666f2a7f51e8fc2
>>
>> struct iga64_template const iga64_code_gpgpu_fill[] = {
>> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> @@ -80,10 +80,11 @@ struct iga64_template const iga64_code_gpgpu_fill[] = {
>> };
>>
>> struct iga64_template const iga64_code_end_system_routine_step_if_eq[] = {
>> - { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> + { .gen_ver = 2000, .size = 48, .code = (const uint32_t []) {
>> 0x80000966, 0x80018220, 0x02008000, 0x00008000,
>> 0x80000965, 0x80118220, 0x02008010, 0xc0ded000,
>> 0x800c0961, 0x1e054220, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e554220, 0x00000000, 0x00000000,
>> 0x80000061, 0x1e654220, 0x00000000, 0xc0ded000,
>> 0x80000061, 0x1e754220, 0x00000000, 0x00000003,
>> 0x80032031, 0x1f0c0000, 0xd0061e8c, 0x04000000,
>> @@ -484,13 +485,14 @@ struct iga64_template const iga64_code_media_block_write_aip[] = {
>> };
>>
>> struct iga64_template const iga64_code_common_target_write[] = {
>> - { .gen_ver = 2000, .size = 48, .code = (const uint32_t []) {
>> + { .gen_ver = 2000, .size = 52, .code = (const uint32_t []) {
>> 0x80100061, 0x1f054220, 0x00000000, 0x00000000,
>> 0x80000061, 0x1f054220, 0x00000000, 0xc0ded001,
>> 0x80000061, 0x1f154220, 0x00000000, 0xc0ded002,
>> 0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
>> 0x80000061, 0x1f354220, 0x00000000, 0xc0ded004,
>> 0x800c0061, 0x1e054220, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e554220, 0x00000000, 0x00000000,
>> 0x80000061, 0x1e654220, 0x00000000, 0xc0ded000,
>> 0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
>> 0x80032031, 0x00000000, 0xd00e1e94, 0x04000000,
>> @@ -612,14 +614,15 @@ struct iga64_template const iga64_code_clear_r40[] = {
>> };
>>
>> struct iga64_template const iga64_code_jump_dw_neq[] = {
>> - { .gen_ver = 2000, .size = 32, .code = (const uint32_t []) {
>> + { .gen_ver = 2000, .size = 36, .code = (const uint32_t []) {
>> 0x800c0061, 0x1e054220, 0x00000000, 0x00000000,
>> + 0x80000061, 0x1e554220, 0x00000000, 0x00000000,
>> 0x80000061, 0x1e654220, 0x00000000, 0xc0ded000,
>> 0x80000061, 0x1e754220, 0x00000000, 0x00000003,
>> 0x80032031, 0x1f0c0000, 0xd0061e8c, 0x04000000,
>> 0x80000061, 0x30014220, 0x00000000, 0x00000000,
>> 0x80008070, 0x00018220, 0x22001f04, 0xc0ded001,
>> - 0x84000020, 0x00004000, 0x00000000, 0xffffffa0,
>> + 0x84000020, 0x00004000, 0x00000000, 0xffffff90,
>> 0x80000901, 0x00010000, 0x00000000, 0x00000000,
>> }},
>> { .gen_ver = 1270, .size = 40, .code = (const uint32_t []) {
>> diff --git a/lib/iga64_macros.h b/lib/iga64_macros.h
>> index 40b6338928e1..f82785610207 100644
>> --- a/lib/iga64_macros.h
>> +++ b/lib/iga64_macros.h
>> @@ -21,6 +21,13 @@
>> #define R0_TGIDY r0.6<0;1,0>:ud
>> #define R0_FFTID r0.5<0;1,0>:ud
>>
>> +/* Inline data from COMPUTE_WALKER*, Bspec: 47203, 73584
>> + * Filled by __xe*_gpgpu_execfunc.
>> + */
>> +#define R1_TGT_ADDRESS r1.0<0;1,0>:uq
>> +#define R1_TGT_WIDTH r1.2<0;1,0>:ud
>> +#define R1_TGT_HEIGHT r1.3<0;1,0>:ud
>> +
>> #define SET_SHARED_MEDIA_BLOCK_MSG_HDR(dst, y, width) \
>> (W) mov (8) dst.0<1>:ud 0x0:ud ;\
>> (W) mov (1) dst.1<1>:ud y ;\
>> @@ -35,28 +42,50 @@
>> (W) mov (1) dst.2<1>:ud (width - 1):ud ;\
>> (W) mov (1) dst.4<1>:ud R0_FFTID
>>
>> +#if GEN_VER < 3000
>> +#define SET_SURFACE_DESC(dst) \
>> +(W) mov (8) dst.0<1>:ud 0x0:ud
>> +#else
>> +#define SET_SURFACE_DESC(dst) \
>> +(W) mov (1) dst.0<1>:uq R1_TGT_ADDRESS ;\
>> +(W) add (1) dst.2<1>:ud R1_TGT_WIDTH -1:d ;\
>> +(W) add (1) dst.3<1>:ud R1_TGT_HEIGHT -1:d ;\
>> +(W) add (1) dst.4<1>:ud R1_TGT_WIDTH -1:d
>> +#endif
>> +
>> #define SET_SHARED_MEDIA_A2DBLOCK_PAYLOAD(dst, y, width) \
>> -(W) mov (8) dst.0<1>:ud 0x0:ud ;\
>> -(W) mov (1) dst.6<1>:ud y ;\
>> + SET_SURFACE_DESC(dst) ;\
>> +(W) mov (1) dst.5<1>:ud 0x0:ud ;\
>> +(W) mov (1) dst.6<1>:ud y ;\
>> (W) mov (1) dst.7<1>:ud (width - 1):ud
>>
>> -#define SET_THREAD_MEDIA_A2DBLOCK_PAYLOAD(dst, x, y, width) \
>> -(W) mov (8) dst.0<1>:ud 0x0:ud ;\
>> +#define SET_THREAD_MEDIA_A2DBLOCK_PAYLOAD(dst, x, y, width) \
>> + SET_SURFACE_DESC(dst) ;\
>> (W) shl (1) dst.5<1>:ud R0_TGIDX 0x2:ud ;\
>> (W) add (1) dst.5<1>:ud dst.5<0;1,0>:ud x:ud ;\
>> (W) add (1) dst.6<1>:ud R0_TGIDY y ;\
>> (W) mov (1) dst.7<1>:ud (width - 1):ud ;\
>>
>> #if GEN_VER < 2000
>> +
>> #define SET_SHARED_SPACE_ADDR(dst, y, width) SET_SHARED_MEDIA_BLOCK_MSG_HDR(dst, y, width)
>> #define SET_THREAD_SPACE_ADDR(dst, x, y, width) SET_THREAD_MEDIA_BLOCK_MSG_HDR(dst, x, y, width)
>> #define LOAD_SPACE_DW(dst, src) send.dc1 (1) dst src src1_null 0x0 0x2190000
>> #define STORE_SPACE_DW(dst, src) send.dc1 (1) null dst null 0x0 0x40A8000
>> +
>> #else
>> +
>> #define SET_SHARED_SPACE_ADDR(dst, y, width) SET_SHARED_MEDIA_A2DBLOCK_PAYLOAD(dst, y, width)
>> #define SET_THREAD_SPACE_ADDR(dst, x, y, width) SET_THREAD_MEDIA_A2DBLOCK_PAYLOAD(dst, x, y, width)
>> +
>> +#if GEN_VER < 3000
>> #define LOAD_SPACE_DW(dst, src) send.tgm (1) dst src null:0 0x0 0x62100003
>> #define STORE_SPACE_DW(dst, src) send.tgm (1) null dst null:0 0x0 0x64000007
>> +#else
>> +#define LOAD_SPACE_DW(dst, src) send.ugm (1) dst src null:0 0x0 0x2120003
>> +#define STORE_SPACE_DW(dst, src) send.ugm (1) null dst src:1 0x0 0x2020007
>> +#endif
>> +
>> #endif
>>
>> #endif
>>
next prev parent reply other threads:[~2024-11-22 14:24 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-21 17:12 [PATCH v3 0/4] lib/gpgpu_shader: simplify load/store shaders and add Xe3 support Andrzej Hajda
2024-11-21 17:12 ` [PATCH v3 1/4] scripts/generate_iga64_codes: add iga64_macros.h to checksum calculation Andrzej Hajda
2024-11-21 17:12 ` [PATCH v3 2/4] lib/gpgpu_shader: simplify load/store shaders Andrzej Hajda
2024-11-22 14:05 ` Grzegorzek, Dominik
2024-11-22 14:22 ` Hajda, Andrzej
2024-11-22 14:28 ` Grzegorzek, Dominik
2024-11-21 17:12 ` [PATCH v3 3/4] lib/gpgpu_shader: pass surface desription to shaders via inline data Andrzej Hajda
2024-11-22 14:27 ` Grzegorzek, Dominik
2024-11-21 17:12 ` [PATCH v3 4/4] lib/gpgpu_shader: add support for Xe3 platforms Andrzej Hajda
2024-11-22 14:11 ` Grzegorzek, Dominik
2024-11-22 14:24 ` Hajda, Andrzej [this message]
2024-11-21 22:40 ` ✓ Xe.CI.BAT: success for lib/gpgpu_shader: simplify load/store shaders and add Xe3 support Patchwork
2024-11-21 22:46 ` ✓ i915.CI.BAT: " Patchwork
2024-11-22 12:34 ` ✗ Xe.CI.Full: failure " Patchwork
2024-11-24 13:14 ` ✗ i915.CI.Full: " Patchwork
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