[PATCH i-g-t v2 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests

[PATCH i-g-t v2 0/4] tests/intel/xe_eudebug_online: Introduce read/write pagefault tests

[Gwan-gyeong Mun]

Add a pagefault read/write test case so that the xe_eudebug_online test can
validate the invalid access pagefault scenario that the eu thread can cause.

For these tests, use the newly introduced DRM_XE_EUDEBUG_EVENT_PAGEFAULT 
event and struct drm_xe_eudebug_event_pagefault.

The added test cases are shown below.
	xe_eudebug_online@pagefault-read
	xe_eudebug_online@pagefault-write

changes in v2:
    Fix the function name to be more clear. (Andrzej, Christoph)
    Refactor of output attention bits on pagefault event handling (Andrzej)
    Remove / update redudant code (Andrzej, Christoph)
    Use igt_container_of() macro (Andrzej, Christoph)

Gwan-gyeong Mun (2):
  lib/gppgu_shader: Add read D32 from ppgtt virtual address
  tests/intel/xe_eudebug_online: Add read/write pagefault online tests

Jonathan Cavitt (2):
  lib/gppgu_shader: Add write D32 to ppgtt virtual address
  eudebug: Add eudebug pagefault event declarations

 .../drm-uapi-experimental/xe_drm_eudebug.h    |  13 ++
 lib/gpgpu_shader.c                            | 188 ++++++++++++++++++
 lib/gpgpu_shader.h                            |   3 +
 lib/iga64_generated_codes.c                   |  42 +++-
 lib/xe/xe_eudebug.c                           |  11 +
 tests/intel/xe_eudebug_online.c               | 178 ++++++++++++++++-
 6 files changed, 429 insertions(+), 6 deletions(-)

-- 
2.46.1

[PATCH i-g-t v2 1/4] lib/gppgu_shader: Add write D32 to ppgtt virtual address

[Gwan-gyeong Mun]

From: Jonathan Cavitt <jonathan.cavitt@intel.com>

Create a function that adds the capabilty to write an dword size at a given
ppgtt address with a dword value. Use an Untyped 2D Block Array Store
DataPort functionality of XE2+ with A64 flat addressing to direct accessing
an entire ppgtt address space.

For the write to succeed, the given ppgtt virtual address has to be bound.
Otherwise a store page fault will be triggered.

v2: Fix the function name to be more clear. (Andrzej)
    Use lower_32_bits() / upper_32_bits() macro (Andrzej)
    Drop unused code

Suggested-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
 lib/gpgpu_shader.c          | 94 +++++++++++++++++++++++++++++++++++++
 lib/gpgpu_shader.h          |  2 +
 lib/iga64_generated_codes.c | 23 ++++++++-
 3 files changed, 118 insertions(+), 1 deletion(-)

diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
index 4e1b8d5e9..d9da35895 100644
--- a/lib/gpgpu_shader.c
+++ b/lib/gpgpu_shader.c
@@ -803,3 +803,97 @@ void gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
 	", 0x807fffff, /* leave breakpoint exception */
 	y_offset, value, 0x7fffff /* clear all exceptions */ );
 }
+
+/**
+ * gpgpu_shader__write_a64_dword:
+ * @shdr: shader to be modified
+ * @ppgtt_addr: write target ppgtt virtual address
+ * @value: dword to be written
+ *
+ * Write one D32 data (DW; DoubleWord) directly to the target ppgtt virtual
+ * address (A64 Flat Address model).
+ *
+ * Note: for the write to succeed, the address specified by @ppgtt_addr has
+ * to be bound. Otherwise a store page fault will be triggered.
+ */
+void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_addr,
+				   uint32_t value)
+{
+	uint64_t addr = CANONICAL(ppgtt_addr);
+	igt_assert_f((addr & 0x3) == 0, "address must be aligned to DWord!\n");
+
+	emit_iga64_code(shdr, write_a64_dword, "				\n\
+#if GEN_VER >= 2000								\n\
+// Unyped 2D Block Store							\n\
+// Instruction_Store2DBlock							\n\
+// bspec: 63981									\n\
+// src0 address payload (Untyped2DBLOCKAddressPayload) specifies both		\n\
+//	the block parameters and the 2D Surface parameters.			\n\
+// src1 data payload format is selected by Data Size.				\n\
+// Untyped2DBLOCKAddressPayload							\n\
+// bspec: 63986									\n\
+// [243:240] Array Length: 0 (length is 1)					\n\
+// [239:232] Block Height: 0 (height is 1)					\n\
+// [231:224] Block Width: 0xf (width is 16)					\n\
+// [223:192] Block Start Y: 0							\n\
+// [191:160] Block Start X: 0							\n\
+// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 bytes)			\n\
+// [127:96] Untyped 2D Surface Height: 0 (height is 1)				\n\
+// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 bytes)			\n\
+// [63:0] Untyped 2D Surface Base Address					\n\
+// initialize register								\n\
+(W)	mov (8)			r30.0<1>:uq	0x0:uq				\n\
+// [0:31] Untyped 2D Surface Base Address low					\n\
+(W)	mov (1)			r30.0<1>:ud	ARG(0):ud			\n\
+// [32:63] Untyped 2D Surface Base Address high					\n\
+(W)	mov (1)			r30.1<1>:ud ARG(1):ud				\n\
+// [95:64] Untyped 2D Surface Width: 0x3f					\n\
+//	   (Width minus 1 (in bytes) of the 2D surface, it represents 64)	\n\
+(W)	mov (1) 		r30.2<1>:ud	0x3f:ud				\n\
+// [127:96] Untyped 2D Surface Height: 0x0					\n\
+//	    (Height minus 1 (in number of data elements) of			\n\
+//	    the Untyped 2D surface, it represents 1)				\n\
+(W)	mov (1) 		r30.3<1>:ud	0x0:ud				\n\
+// [159:128] Untyped 2D Surface Pitch: 0x3f					\n\
+//	     (Pitch minus 1 (in bytes) of the 2D surface, it represents 64)	\n\
+(W)	mov (1)			r30.4<1>:ud	0x3f:ud				\n\
+// [231:224] Block Width: 0xf (15)						\n\
+//	     (Specifies the width minus 1 (in number of data elements) for this	\n\
+//	     rectangular region, it represents 16)				\n\
+// Block width (encoded_value + 1) must be a multiple of DW (4 bytes).		\n\
+// [239:232] Block Height: 0							\n\
+//	     (Specifies the height minus 1 (in number of data elements) for	\n\
+//	     this rectangular region, it represents 1)				\n\
+// [243:240] Array Length: 0							\n\
+//	     (Specifies Array Length minus 1 for Load2DBlockArray messages,	\n\
+//	     must be zero for 2D Block Store messages, it represents 1)		\n\
+(W)	mov (1)			r30.7<1>:ud	0xf:ud				\n\
+// src1 data payload size							\n\
+// Block Height x Block Width x Data size / GRF Register size			\n\
+//	=> 1 x 16 x 32bit / 512bit = 1						\n\
+// data payload size is 1							\n\
+(W)	mov (8)			r31.0<1>:uq	0x0:uq				\n\
+(W)	mov (1|M0)		r31.0<1>:ud 	ARG(2):ud			\n\
+// send.ugm Untyped 2D Block Array Store					\n\
+// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc				\n\
+// Execution Mask restriction: SIMT1						\n\
+//										\n\
+// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D Block)	\n\
+// bspec: 67780									\n\
+// 0x0 =>									\n\
+// [32:22] Global Y_offset: 0							\n\
+// [21:12] Global X_offset: 0							\n\
+//										\n\
+// Message Descriptor								\n\
+// bspec: 63981									\n\
+// 0x2020407 =>									\n\
+// [30:29] Address Type: 0 (FLAT)						\n\
+// [28:25] Src0 Length: 1							\n\
+// [24:20] Dest Length: 0							\n\
+// [19:16] Cache : 2 (L1UC_L3UC)						\n\
+// [11:9] Data Size: 2 (D32)							\n\
+// [5:0] Store Operation: 7							\n\
+(W)	send.ugm (1)		null	r30	r31:1	0x0	0x2020407	\n\
+#endif										\n\
+	", lower_32_bits(addr), upper_32_bits(addr), value);
+}
diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
index c7c21c115..18a4c9725 100644
--- a/lib/gpgpu_shader.h
+++ b/lib/gpgpu_shader.h
@@ -85,6 +85,8 @@ void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
 			       uint32_t y_offset);
 void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, uint32_t x_offset,
 				      uint32_t y_offset, uint32_t mask, uint32_t value);
+void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_addr,
+				   uint32_t value);
 void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
 void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
 void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
index 6638be07b..e97bcf042 100644
--- a/lib/iga64_generated_codes.c
+++ b/lib/iga64_generated_codes.c
@@ -3,7 +3,7 @@
 
 #include "gpgpu_shader.h"
 
-#define MD5_SUM_IGA64_ASMS ec9d477415eebb7d6983395f1bcde78f
+#define MD5_SUM_IGA64_ASMS a1ee0173014ab4cda3090faeca1cbae1
 
 struct iga64_template const iga64_code_gpgpu_fill[] = {
 	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
@@ -79,6 +79,27 @@ struct iga64_template const iga64_code_gpgpu_fill[] = {
 	}}
 };
 
+struct iga64_template const iga64_code_write_a64_dword[] = {
+	{ .gen_ver = 2000, .size = 52, .code = (const uint32_t []) {
+		0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
+		0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
+		0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
+		0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
+		0x80000061, 0x1e354220, 0x00000000, 0x00000000,
+		0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
+		0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
+		0x800c0061, 0x1f054330, 0x00000000, 0x00000000,
+		0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
+		0x80032031, 0x00000000, 0xf80e1e0c, 0x00801f0c,
+		0x80000001, 0x00010000, 0x20000000, 0x00000000,
+		0x80000001, 0x00010000, 0x30000000, 0x00000000,
+		0x80000901, 0x00010000, 0x00000000, 0x00000000,
+	}},
+	{ .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
+
+	}}
+};
+
 struct iga64_template const iga64_code_end_system_routine_step_if_eq[] = {
 	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
 		0x80000966, 0x80018220, 0x02008000, 0x00008000,
-- 
2.46.1

[PATCH i-g-t v2 2/4] lib/gppgu_shader: Add read D32 from ppgtt virtual address

[Gwan-gyeong Mun]

Create a function that adds the capabilty to read an dword size from a
given ppgtt address. Use an Untyped 2D Block Array Load DataPort
functionality of XE2+ with A64 flat addressing to direct accessing an
entire ppgtt address space.

For the read to succeed, the given ppgtt virtual address has to be bound.
Otherwise a load page fault will be triggered.

v2: Fix the function name to be more clear. (Christoph)

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 lib/gpgpu_shader.c          | 94 +++++++++++++++++++++++++++++++++++++
 lib/gpgpu_shader.h          |  1 +
 lib/iga64_generated_codes.c | 21 ++++++++-
 3 files changed, 115 insertions(+), 1 deletion(-)

diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
index d9da35895..147df3a3d 100644
--- a/lib/gpgpu_shader.c
+++ b/lib/gpgpu_shader.c
@@ -897,3 +897,97 @@ void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_add
 #endif										\n\
 	", lower_32_bits(addr), upper_32_bits(addr), value);
 }
+
+/**
+ * gpgpu_shader__read_a64_dword:
+ * @shdr: shader to be modified
+ * @ppgtt_addr: read target ppgtt virtual address
+ *
+ * Read one D32 data (DW; DoubleWord) directly from the target ppgtt virtual
+ * address (A64 Flat Address model).
+ *
+ * Note: for the read to succeed, the address specified by @ppgtt_addr has
+ * to be bound. Otherwise a load page fault will be triggered.
+ */
+void gpgpu_shader__read_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_addr)
+{
+	uint64_t addr = CANONICAL(ppgtt_addr);
+
+	igt_assert_f((addr & 0x3) == 0, "address must be aligned to DWord!\n");
+
+	emit_iga64_code(shdr, read_a64_dword, "					\n\
+#if GEN_VER >= 2000								\n\
+// Unyped 2D Block Array Load 							\n\
+// Instruction_Load2DBlockArray							\n\
+// bspec: 63972									\n\
+// src0 address payload (Untyped2DBLOCKAddressPayload) specifies both		\n\
+//	the block parameters and the 2D Surface parameters.			\n\
+// Untyped2DBLOCKAddressPayload							\n\
+// bspec: 63986									\n\
+// [243:240] Array Length: 0 (length is 1)					\n\
+// [239:232] Block Height: 0 (height is 1)					\n\
+// [231:224] Block Width: 0xf (width is 16)					\n\
+// [223:192] Block Start Y: 0							\n\
+// [191:160] Block Start X: 0							\n\
+// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 bytes)			\n\
+// [127:96] Untyped 2D Surface Height: 0 (height is 1)				\n\
+// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 bytes)			\n\
+// [63:0] Untyped 2D Surface Base Address					\n\
+// initialize register								\n\
+(W)	mov (8)			r30.0<1>:uq	0x0:uq				\n\
+// [0:31] Untyped 2D Surface Base Address low					\n\
+(W)	mov (1)			r30.0<1>:ud	ARG(0):ud			\n\
+// [32:63] Untyped 2D Surface Base Address high					\n\
+(W)	mov (1)			r30.1<1>:ud ARG(1):ud				\n\
+// [95:64] Untyped 2D Surface Width: 0x3f					\n\
+//	   (Width minus 1 (in bytes) of the 2D surface, it represents 64)	\n\
+(W)	mov (1) 		r30.2<1>:ud	0x3f:ud				\n\
+// [127:96] Untyped 2D Surface Height: 0x0					\n\
+//	    (Height minus 1 (in number of data elements) of			\n\
+//	    the Untyped 2D surface, it represents 1)				\n\
+(W)	mov (1) 		r30.3<1>:ud	0x0:ud				\n\
+// [159:128] Untyped 2D Surface Pitch: 0x3f					\n\
+//	     (Pitch minus 1 (in bytes) of the 2D surface, it represents 64)	\n\
+(W)	mov (1)			r30.4<1>:ud	0x3f:ud				\n\
+// [231:224] Block Width: 0xf (15)						\n\
+//	     (Specifies the width minus 1 (in number of data elements) for this	\n\
+//	     rectangular region, it represents 16)				\n\
+// Block width (encoded_value + 1) must be a multiple of DW (4 bytes).		\n\
+// [239:232] Block Height: 0							\n\
+//	     (Specifies the height minus 1 (in number of data elements) for	\n\
+//	     this rectangular region, it represents 1)				\n\
+// [243:240] Array Length: 0							\n\
+//	     (Specifies Array Length minus 1 for Load2DBlockArray messages,	\n\
+//	     must be zero for 2D Block Store messages, it represents 1)		\n\
+(W)	mov (1)			r30.7<1>:ud	0xf:ud				\n\
+//										\n\
+// dest data payload format is selected by Data Size.				\n\
+// Block Height x Block Width x Data size / GRF Register size			\n\
+//	=> 1 x 16 x 32bit / 512bit = 1						\n\
+// data payload format size is 1 GRF Register.					\n\
+//										\n\
+// send.ugm Untyped 2D Block Array Load						\n\
+// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc				\n\
+// Execution Mask restriction: SIMT1						\n\
+//										\n\
+// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D Block)	\n\
+// bspec: 67780									\n\
+// 0x0 =>									\n\
+// [32:22] Global Y_offset: 0							\n\
+// [21:12] Global X_offset: 0							\n\
+//										\n\
+// Message Descriptor								\n\
+// bspec: 63972									\n\
+// 0x2128403 =>									\n\
+// [30:29] Address Type: 0 (FLAT)						\n\
+// [28:25] Src0 Length: 1							\n\
+// [24:20] Dest Length: 1							\n\
+// [19:16] Cache : 2 (L1UC_L3UC) 10						\n\
+// [15] Transpose Block: 1							\n\
+// [11:9] Data Size: 2 (D32) 10							\n\
+// [7] VNNI Transform: 0							\n\
+// [5:0] Load Operation: 3 (Load 2D Block) 11					\n\
+(W)	send.ugm (1)		r31	r30	null	0x0	0x2128403	\n\
+#endif										\n\
+	", lower_32_bits(addr), upper_32_bits(addr));
+}
diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
index 18a4c9725..07ed0fe1b 100644
--- a/lib/gpgpu_shader.h
+++ b/lib/gpgpu_shader.h
@@ -87,6 +87,7 @@ void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, ui
 				      uint32_t y_offset, uint32_t mask, uint32_t value);
 void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_addr,
 				   uint32_t value);
+void gpgpu_shader__read_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_addr);
 void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
 void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
 void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
index e97bcf042..721ac267f 100644
--- a/lib/iga64_generated_codes.c
+++ b/lib/iga64_generated_codes.c
@@ -3,7 +3,7 @@
 
 #include "gpgpu_shader.h"
 
-#define MD5_SUM_IGA64_ASMS a1ee0173014ab4cda3090faeca1cbae1
+#define MD5_SUM_IGA64_ASMS bdc80eeb9a11b97ff51422a39f4623f5
 
 struct iga64_template const iga64_code_gpgpu_fill[] = {
 	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
@@ -79,6 +79,25 @@ struct iga64_template const iga64_code_gpgpu_fill[] = {
 	}}
 };
 
+struct iga64_template const iga64_code_read_a64_dword[] = {
+	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
+		0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
+		0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
+		0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
+		0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
+		0x80000061, 0x1e354220, 0x00000000, 0x00000000,
+		0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
+		0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
+		0x80032031, 0x1f0c0000, 0xf8061e0c, 0x00a00000,
+		0x80000001, 0x00010000, 0x20000000, 0x00000000,
+		0x80000001, 0x00010000, 0x30000000, 0x00000000,
+		0x80000901, 0x00010000, 0x00000000, 0x00000000,
+	}},
+	{ .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
+
+	}}
+};
+
 struct iga64_template const iga64_code_write_a64_dword[] = {
 	{ .gen_ver = 2000, .size = 52, .code = (const uint32_t []) {
 		0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
-- 
2.46.1

[PATCH i-g-t v2 3/4] eudebug: Add eudebug pagefault event declarations

[Gwan-gyeong Mun]

From: Jonathan Cavitt <jonathan.cavitt@intel.com>

Update the xe_eudebug drm to include pagefault events.

v2: use igt_container_of() macro (Andrzej)

Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Acked-by: Christoph Manszewski <christoph.manszewski@intel.com>
---
 include/drm-uapi-experimental/xe_drm_eudebug.h | 13 +++++++++++++
 lib/xe/xe_eudebug.c                            | 11 +++++++++++
 2 files changed, 24 insertions(+)

diff --git a/include/drm-uapi-experimental/xe_drm_eudebug.h b/include/drm-uapi-experimental/xe_drm_eudebug.h
index f50051e9a..ed2e728c2 100644
--- a/include/drm-uapi-experimental/xe_drm_eudebug.h
+++ b/include/drm-uapi-experimental/xe_drm_eudebug.h
@@ -154,6 +154,7 @@ struct drm_xe_eudebug_event {
 #define DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE	9
 #define DRM_XE_EUDEBUG_EVENT_METADATA		10
 #define DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_METADATA 11
+#define DRM_XE_EUDEBUG_EVENT_PAGEFAULT		12
 
 	__u16 flags;
 #define DRM_XE_EUDEBUG_EVENT_CREATE		(1 << 0)
@@ -352,6 +353,18 @@ struct drm_xe_eudebug_event_vm_bind_op_metadata {
 	__u64 metadata_cookie;
 };
 
+struct drm_xe_eudebug_event_pagefault {
+	struct drm_xe_eudebug_event base;
+
+	__u64 client_handle;
+	__u64 exec_queue_handle;
+	__u64 lrc_handle;
+	__u32 flags;
+	__u32 bitmask_size;
+	__u64 pagefault_address;
+	__u8 bitmask[];
+};
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/lib/xe/xe_eudebug.c b/lib/xe/xe_eudebug.c
index c5814421b..8f3bb2f1e 100644
--- a/lib/xe/xe_eudebug.c
+++ b/lib/xe/xe_eudebug.c
@@ -91,6 +91,8 @@ static const char *type_to_str(unsigned int type)
 		return "metadata";
 	case DRM_XE_EUDEBUG_EVENT_VM_BIND_OP_METADATA:
 		return "vm_bind_op_metadata";
+	case DRM_XE_EUDEBUG_EVENT_PAGEFAULT:
+		return "pagefault";
 	}
 
 	return "UNKNOWN";
@@ -222,6 +224,15 @@ static const char *event_members_to_str(struct drm_xe_eudebug_event *e, char *bu
 			op->vm_bind_op_ref_seqno, op->metadata_handle, op->metadata_cookie);
 		break;
 	}
+	case DRM_XE_EUDEBUG_EVENT_PAGEFAULT: {
+		struct drm_xe_eudebug_event_pagefault *pf = igt_container_of(e, pf, base);
+
+		sprintf(buf, "client_handle=%llu, exec_queue_handle=%llu, "
+			"lrc_handle=%llu, bitmask_size=%d, pagefault_address=0x%llx",
+			pf->client_handle, pf->exec_queue_handle, pf->lrc_handle,
+			pf->bitmask_size, pf->pagefault_address);
+		break;
+	}
 	default:
 		strcpy(buf, "<...>");
 	}
-- 
2.46.1

[PATCH i-g-t v2 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests

[Gwan-gyeong Mun]

Add read and write pagefault tests to xe_eudebug_online that checks if a
pagefault event is submitted by the KMD debugger when a pagefault occurs.

Test that read (load instruction) and write(store instruction) attempt to
load or store access to unallocated memory, causing a pagefault.
Examine the address causing the page fault and the number of eu threads
causing the pagefault.

v2: Refactor of output attention bits on pagefault event handling (Andrzej)
    remove / update redudant code (Andrzej, Christoph)
    use igt_container_of() macro (Christoph)

Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 tests/intel/xe_eudebug_online.c | 178 +++++++++++++++++++++++++++++++-
 1 file changed, 173 insertions(+), 5 deletions(-)

diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/xe_eudebug_online.c
index 0ef0d8093..a70d18ee4 100644
--- a/tests/intel/xe_eudebug_online.c
+++ b/tests/intel/xe_eudebug_online.c
@@ -36,6 +36,8 @@
 #define BB_IN_VRAM			(1 << 11)
 #define TARGET_IN_SRAM			(1 << 12)
 #define TARGET_IN_VRAM			(1 << 13)
+#define SHADER_PAGEFAULT_READ		(1 << 14)
+#define SHADER_PAGEFAULT_WRITE		(1 << 15)
 #define TRIGGER_UFENCE_SET_BREAKPOINT	(1 << 24)
 #define TRIGGER_RESUME_SINGLE_WALK	(1 << 25)
 #define TRIGGER_RESUME_PARALLEL_WALK	(1 << 26)
@@ -45,6 +47,7 @@
 #define TRIGGER_RESUME_DSS		(1 << 30)
 #define TRIGGER_RESUME_ONE		(1 << 31)
 
+#define SHADER_PAGEFAULT	(SHADER_PAGEFAULT_READ | SHADER_PAGEFAULT_WRITE)
 #define BB_REGION_BITMASK	(BB_IN_SRAM | BB_IN_VRAM)
 #define TARGET_REGION_BITMASK	(TARGET_IN_SRAM | TARGET_IN_VRAM)
 
@@ -61,6 +64,8 @@
 #define CACHING_VALUE(n)	(CACHING_INIT_VALUE + (n))
 
 #define SHADER_CANARY 0x01010101
+#define BAD_CANARY 0xf1f1f1f
+#define BAD_OFFSET (0x12345678ull << 12)
 
 #define WALKER_X_DIM		4
 #define WALKER_ALIGNMENT	16
@@ -120,7 +125,7 @@ static struct intel_buf *create_uc_buf(int fd, int width, int height, uint64_t r
 
 static int get_number_of_threads(uint64_t flags)
 {
-	if (flags & SHADER_MIN_THREADS)
+	if (flags & (SHADER_MIN_THREADS | SHADER_PAGEFAULT))
 		return 16;
 
 	if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
@@ -179,6 +184,16 @@ static struct gpgpu_shader *get_shader(int fd, const unsigned int flags)
 			gpgpu_shader__common_target_write_u32(shader, s_dim.y + i, CACHING_VALUE(i));
 		gpgpu_shader__nop(shader);
 		gpgpu_shader__breakpoint(shader);
+	} else if (flags & SHADER_PAGEFAULT) {
+		if (flags & SHADER_PAGEFAULT_READ)
+			gpgpu_shader__read_a64_dword(shader, BAD_OFFSET);
+		else
+			gpgpu_shader__write_a64_dword(shader, BAD_OFFSET, BAD_CANARY);
+
+		gpgpu_shader__label(shader, 0);
+		gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
+		gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
+		gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
 	}
 
 	gpgpu_shader__eot(shader);
@@ -217,6 +232,16 @@ static int count_set_bits(void *ptr, size_t size)
 	return count;
 }
 
+static int eu_attentions_xor_count(const uint32_t *a, const uint32_t *b, uint32_t size)
+{
+	int count = 0;
+
+	for (int i = 0; i < size / 4 ; i++)
+		count += igt_hweight(a[i] ^ b[i]);
+
+	return count;
+}
+
 static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim, uint32_t value)
 {
 	int count = 0;
@@ -636,7 +661,7 @@ static void eu_attention_resume_trigger(struct xe_eudebug_debugger *d,
 		}
 	}
 
-	if (d->flags & SHADER_LOOP) {
+	if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
 		uint32_t threads = get_number_of_threads(d->flags);
 		uint32_t val = STEERING_END_LOOP;
 
@@ -746,6 +771,44 @@ static void eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
 			data->single_step_bitmask[i] &= ~att->bitmask[i];
 }
 
+static void eu_attention_resume_pagefault_trigger(struct xe_eudebug_debugger *d,
+						  struct drm_xe_eudebug_event *e)
+{
+	struct drm_xe_eudebug_event_eu_attention *att = igt_container_of(e, att, base);
+	struct online_debug_data *data = d->ptr;
+	uint32_t bitmask_size = att->bitmask_size;
+	uint8_t *bitmask;
+
+	if (data->last_eu_control_seqno > att->base.seqno)
+		return;
+
+	bitmask = calloc(1, att->bitmask_size);
+	igt_assert(bitmask);
+
+	eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
+		       att->lrc_handle, bitmask, &bitmask_size);
+	igt_assert(bitmask_size == att->bitmask_size);
+
+	pthread_mutex_lock(&data->mutex);
+
+	if (d->flags & SHADER_PAGEFAULT) {
+		uint32_t threads = get_number_of_threads(d->flags);
+		uint32_t val = STEERING_END_LOOP;
+
+		igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
+				     data->target_offset + steering_offset(threads)),
+			      sizeof(uint32_t));
+		fsync(data->vm_fd);
+	}
+	pthread_mutex_unlock(&data->mutex);
+
+	data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, att->client_handle,
+						    att->exec_queue_handle, att->lrc_handle,
+						    bitmask, att->bitmask_size);
+
+	free(bitmask);
+}
+
 static void open_trigger(struct xe_eudebug_debugger *d,
 			 struct drm_xe_eudebug_event *e)
 {
@@ -1015,7 +1078,7 @@ static void run_online_client(struct xe_eudebug_client *c)
 	struct intel_bb *ibb;
 	struct intel_buf *buf;
 	uint32_t *ptr;
-	int fd;
+	int fd, vm_flags;
 
 	metadata[0] = calloc(2, sizeof(*metadata));
 	metadata[1] = calloc(2, sizeof(*metadata));
@@ -1025,7 +1088,7 @@ static void run_online_client(struct xe_eudebug_client *c)
 	fd = xe_eudebug_client_open_driver(c);
 
 	/* Additional memory for steering control */
-	if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
+	if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || c->flags & SHADER_PAGEFAULT)
 		s_dim.y++;
 	/* Additional memory for caching check */
 	if ((c->flags & SHADER_CACHING_SRAM) || (c->flags & SHADER_CACHING_VRAM))
@@ -1045,7 +1108,11 @@ static void run_online_client(struct xe_eudebug_client *c)
 							   DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
 							   2 * sizeof(*metadata), metadata[1]);
 
-	create.vm_id = xe_eudebug_client_vm_create(c, fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
+	vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
+	vm_flags |= c->flags & SHADER_PAGEFAULT ? DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
+
+	create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
+
 	xe_eudebug_client_exec_queue_create(c, fd, &create);
 
 	ibb = xe_bb_create_on_offset(fd, create.exec_queue_id, create.vm_id, bb_offset, bb_size,
@@ -1245,11 +1312,13 @@ match_attention_with_exec_queue(struct xe_eudebug_event_log *log,
 static void online_session_check(struct xe_eudebug_session *s, int flags)
 {
 	struct drm_xe_eudebug_event_eu_attention *ea = NULL;
+	struct drm_xe_eudebug_event_pagefault *pf = NULL;
 	struct drm_xe_eudebug_event *event = NULL;
 	struct online_debug_data *data = s->client->ptr;
 	bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
 	int sum = 0;
 	int bitmask_size;
+	int pagefault_threads = 0;
 
 	xe_eudebug_session_check(s, true, XE_EUDEBUG_FILTER_EVENT_VM_BIND |
 					  XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
@@ -1265,6 +1334,17 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
 			igt_assert_eq(ea->bitmask_size, bitmask_size);
 			sum += count_set_bits(ea->bitmask, bitmask_size);
 			igt_assert(match_attention_with_exec_queue(s->debugger->log, ea));
+		} else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
+			uint32_t after_offset = bitmask_size / sizeof(uint32_t);
+			uint32_t resolved_offset = bitmask_size / sizeof(uint32_t) * 2;
+			uint32_t *ptr = NULL;
+
+			pf = igt_container_of(event, pf, base);
+			ptr = (uint32_t *) pf->bitmask;
+			igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
+			pagefault_threads += eu_attentions_xor_count(ptr + after_offset,
+								     ptr + resolved_offset,
+								     bitmask_size);
 		}
 	}
 
@@ -1279,6 +1359,9 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
 		igt_assert(sum > 0);
 	else
 		igt_assert(sum == 0);
+
+	if (flags & SHADER_PAGEFAULT)
+		igt_assert(pagefault_threads > 0);
 }
 
 static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
@@ -1302,6 +1385,43 @@ static void ufence_ack_set_bp_trigger(struct xe_eudebug_debugger *d,
 	}
 }
 
+static void pagefault_trigger(struct xe_eudebug_debugger *d,
+			      struct drm_xe_eudebug_event *e)
+{
+	struct drm_xe_eudebug_event_pagefault *pf = igt_container_of(e, pf, base);
+	uint32_t attn_size = pf->bitmask_size / 3;
+	int attn_size_as_u32 = attn_size / sizeof(uint32_t);
+	uint32_t *ptr = (uint32_t *) pf->bitmask;
+	uint32_t *ptrs[3] = {ptr, ptr + attn_size_as_u32, ptr + 2 * attn_size_as_u32};
+	const char * const name[3] = {"before", "after", "resolved"};
+	int threads[3], pagefault_threads, idx;
+
+	for (idx = 0; idx < 3; idx++)
+		threads[idx] = count_set_bits(ptrs[idx], attn_size);
+
+	pagefault_threads = eu_attentions_xor_count(ptrs[1], ptrs[2], attn_size);
+
+	igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
+		  "resolved=%d, pagefault=%d] "
+		  "client[%llu], exec_queue[%llu], lrc[%llu], bitmask_size[%d], "
+		  "pagefault_address[0x%llx]\n",
+		  pf->base.seqno, threads[0], threads[1], threads[2],
+		  pagefault_threads, pf->client_handle, pf->exec_queue_handle,
+		  pf->lrc_handle, pf->bitmask_size,
+		  pf->pagefault_address);
+
+	for (idx = 0; idx < 3; idx++) {
+		igt_debug("=== Attentions %s ===\n", name[idx]);
+
+		for (uint32_t i = 0; i < attn_size_as_u32; i += 2)
+			igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
+				  ptrs[idx][i], ptrs[idx][i + 1]);
+	}
+
+	igt_assert(pagefault_threads > 0);
+	igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
+}
+
 /**
  * SUBTEST: basic-breakpoint
  * Description:
@@ -1383,6 +1503,49 @@ static void test_set_breakpoint_online(int fd, struct drm_xe_engine_class_instan
 	online_debug_data_destroy(data);
 }
 
+/**
+ * SUBTEST: pagefault-read
+ * Description:
+ *     Check whether KMD sends pagefault event for workload in debug mode that
+ *     triggers a read pagefault.
+ *
+ * SUBTEST: pagefault-write
+ * Description:
+ *     Check whether KMD sends pagefault event for workload in debug mode that
+ *     triggers a write pagefault.
+ */
+static void test_pagefault_online(int fd, struct drm_xe_engine_class_instance *hwe,
+				  int flags)
+{
+	struct xe_eudebug_session *s;
+	struct online_debug_data *data;
+
+	data = online_debug_data_create(hwe);
+	s = xe_eudebug_session_create(fd, run_online_client, flags, data);
+
+	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_OPEN,
+					open_trigger);
+	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
+					exec_queue_trigger);
+	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
+					eu_attention_debug_trigger);
+	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
+					eu_attention_resume_pagefault_trigger);
+	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
+	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_METADATA,
+					create_metadata_trigger);
+	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
+					ufence_ack_trigger);
+	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
+					pagefault_trigger);
+
+	xe_eudebug_session_run(s);
+	online_session_check(s, s->flags);
+
+	xe_eudebug_session_destroy(s);
+	online_debug_data_destroy(data);
+}
+
 /**
  * SUBTEST: preempt-breakpoint
  * Description:
@@ -2344,6 +2507,11 @@ igt_main
 	igt_subtest("breakpoint-many-sessions-tiles")
 		test_many_sessions_on_tiles(fd, true);
 
+	test_gt_render_or_compute("pagefault-read", fd, hwe)
+		test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
+	test_gt_render_or_compute("pagefault-write", fd, hwe)
+		test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
+
 	igt_fixture {
 		xe_eudebug_enable(fd, was_enabled);
 
-- 
2.46.1

✓ Xe.CI.BAT: success for tests/intel/xe_eudebug_online: Introduce read/write pagefault tests (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 12320 bytes --]

== Series Details ==

Series: tests/intel/xe_eudebug_online: Introduce read/write pagefault tests (rev2)
URL   : https://patchwork.freedesktop.org/series/141401/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8118_BAT -> XEIGTPW_12158_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_12158_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-adlp-7:         [PASS][1] -> [DMESG-WARN][2] ([Intel XE#3517]) +2 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@core_hotunplug@unbind-rebind.html

  * igt@kms_psr@psr-cursor-plane-move:
    - bat-adlp-7:         [PASS][3] -> [SKIP][4] ([Intel XE#455]) +3 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@kms_psr@psr-cursor-plane-move.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@kms_psr@psr-cursor-plane-move.html

  * igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit:
    - bat-lnl-2:          NOTRUN -> [SKIP][5] ([Intel XE#2229]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-lnl-2/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html

  * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
    - bat-lnl-1:          NOTRUN -> [SKIP][6] ([Intel XE#2229]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-lnl-1/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html

  
#### Possible fixes ####

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-prefetch:
    - bat-lnl-1:          [DMESG-FAIL][7] ([Intel XE#3466]) -> [PASS][8] +33 other tests pass
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-lnl-1/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-prefetch.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-lnl-1/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-prefetch.html

  * igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch:
    - bat-lnl-2:          [DMESG-FAIL][9] ([Intel XE#3466]) -> [PASS][10] +33 other tests pass
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-lnl-2/igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-lnl-2/igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch.html

  * igt@xe_exec_threads@threads-basic:
    - bat-lnl-1:          [DMESG-WARN][11] ([Intel XE#3466]) -> [PASS][12] +3 other tests pass
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-lnl-1/igt@xe_exec_threads@threads-basic.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-lnl-1/igt@xe_exec_threads@threads-basic.html

  * igt@xe_exec_threads@threads-mixed-basic:
    - bat-lnl-2:          [DMESG-WARN][13] ([Intel XE#3466]) -> [PASS][14] +3 other tests pass
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-lnl-2/igt@xe_exec_threads@threads-mixed-basic.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-lnl-2/igt@xe_exec_threads@threads-mixed-basic.html

  * igt@xe_live_ktest@xe_migrate:
    - bat-lnl-2:          [SKIP][15] ([Intel XE#1192]) -> [PASS][16] +1 other test pass
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-lnl-2/igt@xe_live_ktest@xe_migrate.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-lnl-2/igt@xe_live_ktest@xe_migrate.html
    - bat-lnl-1:          [SKIP][17] ([Intel XE#1192]) -> [PASS][18] +1 other test pass
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-lnl-1/igt@xe_live_ktest@xe_migrate.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-lnl-1/igt@xe_live_ktest@xe_migrate.html

  
#### Warnings ####

  * igt@kms_dsc@dsc-basic:
    - bat-adlp-7:         [SKIP][19] ([Intel XE#3443] / [Intel XE#455]) -> [SKIP][20] ([Intel XE#455])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@kms_dsc@dsc-basic.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@kms_dsc@dsc-basic.html

  * igt@xe_evict@evict-beng-small:
    - bat-adlp-7:         [SKIP][21] ([Intel XE#261] / [Intel XE#3443] / [Intel XE#688]) -> [SKIP][22] ([Intel XE#261] / [Intel XE#688]) +15 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@xe_evict@evict-beng-small.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@xe_evict@evict-beng-small.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd:
    - bat-adlp-7:         [SKIP][23] ([Intel XE#3443] / [Intel XE#688]) -> [SKIP][24] ([Intel XE#688]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd.html

  * igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch:
    - bat-adlp-7:         [SKIP][25] ([Intel XE#288] / [Intel XE#3443]) -> [SKIP][26] ([Intel XE#288]) +32 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@xe_exec_fault_mode@twice-userptr-invalidate-prefetch.html

  * igt@xe_live_ktest@xe_bo:
    - bat-lnl-1:          [SKIP][27] ([Intel XE#1192]) -> [SKIP][28] ([Intel XE#2229])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-lnl-1/igt@xe_live_ktest@xe_bo.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-lnl-1/igt@xe_live_ktest@xe_bo.html
    - bat-lnl-2:          [SKIP][29] ([Intel XE#1192]) -> [SKIP][30] ([Intel XE#2229])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-lnl-2/igt@xe_live_ktest@xe_bo.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-lnl-2/igt@xe_live_ktest@xe_bo.html

  * igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit:
    - bat-adlp-7:         [SKIP][31] ([Intel XE#2229] / [Intel XE#3443] / [Intel XE#455]) -> [SKIP][32] ([Intel XE#2229] / [Intel XE#455]) +2 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html

  * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
    - bat-adlp-7:         [SKIP][33] ([Intel XE#2229] / [Intel XE#3443]) -> [SKIP][34] ([Intel XE#2229])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html

  * igt@xe_mmap@vram:
    - bat-adlp-7:         [SKIP][35] ([Intel XE#1008] / [Intel XE#3443]) -> [SKIP][36] ([Intel XE#1008])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@xe_mmap@vram.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@xe_mmap@vram.html

  * igt@xe_pat@pat-index-xe2:
    - bat-atsm-2:         [SKIP][37] ([Intel XE#2839] / [Intel XE#977]) -> [SKIP][38] ([Intel XE#977])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-atsm-2/igt@xe_pat@pat-index-xe2.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-atsm-2/igt@xe_pat@pat-index-xe2.html
    - bat-adlp-vf:        [SKIP][39] ([Intel XE#2839] / [Intel XE#977]) -> [SKIP][40] ([Intel XE#977])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-vf/igt@xe_pat@pat-index-xe2.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-vf/igt@xe_pat@pat-index-xe2.html
    - bat-adlp-7:         [SKIP][41] ([Intel XE#2839] / [Intel XE#3443] / [Intel XE#977]) -> [SKIP][42] ([Intel XE#977])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@xe_pat@pat-index-xe2.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@xe_pat@pat-index-xe2.html
    - bat-dg2-oem2:       [SKIP][43] ([Intel XE#2839] / [Intel XE#977]) -> [SKIP][44] ([Intel XE#977])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-dg2-oem2/igt@xe_pat@pat-index-xe2.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-dg2-oem2/igt@xe_pat@pat-index-xe2.html

  * igt@xe_pat@pat-index-xehpc:
    - bat-adlp-7:         [SKIP][45] ([Intel XE#2838] / [Intel XE#3443] / [Intel XE#979]) -> [SKIP][46] ([Intel XE#2838] / [Intel XE#979])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@xe_pat@pat-index-xehpc.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pat@pat-index-xelp:
    - bat-bmg-2:          [SKIP][47] ([Intel XE#2237] / [Intel XE#2245]) -> [SKIP][48] ([Intel XE#2245])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-bmg-2/igt@xe_pat@pat-index-xelp.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-bmg-2/igt@xe_pat@pat-index-xelp.html
    - bat-bmg-1:          [SKIP][49] ([Intel XE#2237] / [Intel XE#2245]) -> [SKIP][50] ([Intel XE#2245])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-bmg-1/igt@xe_pat@pat-index-xelp.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-bmg-1/igt@xe_pat@pat-index-xelp.html
    - bat-lnl-2:          [SKIP][51] ([Intel XE#2237] / [Intel XE#977]) -> [SKIP][52] ([Intel XE#977])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-lnl-2/igt@xe_pat@pat-index-xelp.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-lnl-2/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pat@pat-index-xelpg:
    - bat-adlp-7:         [SKIP][53] ([Intel XE#3443] / [Intel XE#979]) -> [SKIP][54] ([Intel XE#979])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/bat-adlp-7/igt@xe_pat@pat-index-xelpg.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/bat-adlp-7/igt@xe_pat@pat-index-xelpg.html

  
  [Intel XE#1008]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1008
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2237]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2237
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
  [Intel XE#2839]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2839
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#3443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3443
  [Intel XE#3466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3466
  [Intel XE#3517]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3517
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * IGT: IGT_8118 -> IGTPW_12158
  * Linux: xe-2252-f8f85a38f6c75e091805f01ceff4041ac2fdf3fd -> xe-2257-e46649e7764a9f6868ccbcba7b8b23b413303380

  IGTPW_12158: 12158
  IGT_8118: 17707095f1e5d3c30f463b43022f01c0160579b6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-2252-f8f85a38f6c75e091805f01ceff4041ac2fdf3fd: f8f85a38f6c75e091805f01ceff4041ac2fdf3fd
  xe-2257-e46649e7764a9f6868ccbcba7b8b23b413303380: e46649e7764a9f6868ccbcba7b8b23b413303380

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/index.html

[-- Attachment #2: Type: text/html, Size: 17058 bytes --]

✗ i915.CI.BAT: failure for tests/intel/xe_eudebug_online: Introduce read/write pagefault tests (rev2)

[Patchwork]

== Series Details ==

Series: tests/intel/xe_eudebug_online: Introduce read/write pagefault tests (rev2)
URL   : https://patchwork.freedesktop.org/series/141401/
State : failure

== Summary ==

CI Bug Log - changes from IGT_8118 -> IGTPW_12158
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_12158 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_12158, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/index.html

Participating hosts (46 -> 45)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_12158:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live:
    - bat-mtlp-6:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-mtlp-6/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-mtlp-6/igt@i915_selftest@live.html

  * igt@i915_selftest@live@objects:
    - fi-skl-6600u:       [PASS][3] -> [INCOMPLETE][4] +1 other test incomplete
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/fi-skl-6600u/igt@i915_selftest@live@objects.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/fi-skl-6600u/igt@i915_selftest@live@objects.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [ABORT][5] ([i915#12829]) -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-mtlp-8/igt@i915_selftest@live.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-mtlp-8/igt@i915_selftest@live.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live:
    - {bat-mtlp-9}:       NOTRUN -> [ABORT][7]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-mtlp-9/igt@i915_selftest@live.html

  
Known issues
------------

  Here are the changes found in IGTPW_12158 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@dmabuf@all-tests@dma_fence_chain:
    - fi-bsw-nick:        [PASS][8] -> [INCOMPLETE][9] ([i915#12904]) +1 other test incomplete
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html

  * igt@fbdev@info:
    - fi-kbl-8809g:       [PASS][10] -> [SKIP][11] ([i915#1849])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/fi-kbl-8809g/igt@fbdev@info.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/fi-kbl-8809g/igt@fbdev@info.html

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-6:         [PASS][12] -> [ABORT][13] ([i915#12915])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-mtlp-6/igt@i915_selftest@live@workarounds.html

  * igt@kms_flip@basic-plain-flip:
    - fi-kbl-8809g:       [PASS][14] -> [SKIP][15] +6 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/fi-kbl-8809g/igt@kms_flip@basic-plain-flip.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/fi-kbl-8809g/igt@kms_flip@basic-plain-flip.html

  
#### Possible fixes ####

  * igt@i915_module_load@load:
    - bat-twl-2:          [DMESG-WARN][16] ([i915#1982]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-twl-2/igt@i915_module_load@load.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-twl-2/igt@i915_module_load@load.html

  * igt@i915_pm_rpm@module-reload:
    - bat-adls-6:         [FAIL][18] ([i915#12903]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-adls-6/igt@i915_pm_rpm@module-reload.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-adls-6/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@gt_mocs:
    - bat-twl-2:          [ABORT][20] ([i915#12919]) -> [PASS][21] +1 other test pass
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-twl-2/igt@i915_selftest@live@gt_mocs.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-twl-2/igt@i915_selftest@live@gt_mocs.html

  * igt@kms_addfb_basic@too-high:
    - fi-kbl-8809g:       [FAIL][22] ([i915#12900]) -> [PASS][23] +37 other tests pass
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - fi-kbl-8809g:       [SKIP][24] -> [PASS][25] +4 other tests pass
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/fi-kbl-8809g/igt@kms_force_connector_basic@prune-stale-modes.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/fi-kbl-8809g/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-apl-1:          [DMESG-WARN][26] ([i915#12918]) -> [PASS][27] +2 other tests pass
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-apl-1/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-apl-1/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Warnings ####

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-dg2-9:          [SKIP][28] ([i915#4212] / [i915#5190]) -> [SKIP][29] ([i915#5190])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-mtlp-6:         [SKIP][30] ([i915#4212] / [i915#5190] / [i915#9792]) -> [SKIP][31] ([i915#5190] / [i915#9792])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-dg2-11:         [SKIP][32] ([i915#4212] / [i915#5190]) -> [SKIP][33] ([i915#5190])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-dg2-14:         [SKIP][34] ([i915#4212] / [i915#5190]) -> [SKIP][35] ([i915#5190])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-dg2-14/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-dg2-14/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-mtlp-8:         [SKIP][36] ([i915#4212] / [i915#5190]) -> [SKIP][37] ([i915#5190])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
    - bat-dg2-8:          [SKIP][38] ([i915#4212] / [i915#5190]) -> [SKIP][39] ([i915#5190])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg2-8:          [SKIP][40] ([i915#4212] / [i915#4215] / [i915#5190]) -> [SKIP][41] ([i915#4215] / [i915#5190])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg1-7:          [SKIP][42] ([i915#4212] / [i915#4215]) -> [SKIP][43] ([i915#4215])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-dg1-7/igt@kms_addfb_basic@basic-y-tiled-legacy.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-dg1-7/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg2-9:          [SKIP][44] ([i915#4212] / [i915#4215] / [i915#5190]) -> [SKIP][45] ([i915#4215] / [i915#5190])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg1-6:          [SKIP][46] ([i915#12311] / [i915#4212] / [i915#4215]) -> [SKIP][47] ([i915#12311] / [i915#4215])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg2-11:         [SKIP][48] ([i915#4212] / [i915#4215] / [i915#5190]) -> [SKIP][49] ([i915#4215] / [i915#5190])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg2-14:         [SKIP][50] ([i915#4212] / [i915#4215] / [i915#5190]) -> [SKIP][51] ([i915#4215] / [i915#5190])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/bat-dg2-14/igt@kms_addfb_basic@basic-y-tiled-legacy.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/bat-dg2-14/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - fi-kbl-8809g:       [FAIL][52] ([i915#12902]) -> [SKIP][53] +5 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8118/fi-kbl-8809g/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/fi-kbl-8809g/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#12311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12311
  [i915#12829]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12829
  [i915#12900]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12900
  [i915#12902]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12902
  [i915#12903]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12903
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#12915]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12915
  [i915#12918]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12918
  [i915#12919]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#9792]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9792


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8118 -> IGTPW_12158
  * Linux: CI_DRM_15720 -> CI_DRM_15725

  CI-20190529: 20190529
  CI_DRM_15720: f8f85a38f6c75e091805f01ceff4041ac2fdf3fd @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_15725: e46649e7764a9f6868ccbcba7b8b23b413303380 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_12158: 12158
  IGT_8118: 17707095f1e5d3c30f463b43022f01c0160579b6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12158/index.html

Re: [PATCH i-g-t v2 1/4] lib/gppgu_shader: Add write D32 to ppgtt virtual address

[Hajda, Andrzej]

W dniu 21.11.2024 o 13:22, Gwan-gyeong Mun pisze:
> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>
> Create a function that adds the capabilty to write an dword size at a given
> ppgtt address with a dword value. Use an Untyped 2D Block Array Store
> DataPort functionality of XE2+ with A64 flat addressing to direct accessing
> an entire ppgtt address space.
>
> For the write to succeed, the given ppgtt virtual address has to be bound.
> Otherwise a store page fault will be triggered.
>
> v2: Fix the function name to be more clear. (Andrzej)
>      Use lower_32_bits() / upper_32_bits() macro (Andrzej)
>      Drop unused code
>
> Suggested-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
> Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> ---
>   lib/gpgpu_shader.c          | 94 +++++++++++++++++++++++++++++++++++++
>   lib/gpgpu_shader.h          |  2 +
>   lib/iga64_generated_codes.c | 23 ++++++++-
>   3 files changed, 118 insertions(+), 1 deletion(-)
>
> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
> index 4e1b8d5e9..d9da35895 100644
> --- a/lib/gpgpu_shader.c
> +++ b/lib/gpgpu_shader.c
> @@ -803,3 +803,97 @@ void gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
>   	", 0x807fffff, /* leave breakpoint exception */
>   	y_offset, value, 0x7fffff /* clear all exceptions */ );
>   }
> +
> +/**
> + * gpgpu_shader__write_a64_dword:
> + * @shdr: shader to be modified
> + * @ppgtt_addr: write target ppgtt virtual address
> + * @value: dword to be written
> + *
> + * Write one D32 data (DW; DoubleWord) directly to the target ppgtt virtual
> + * address (A64 Flat Address model).
> + *
> + * Note: for the write to succeed, the address specified by @ppgtt_addr has
> + * to be bound. Otherwise a store page fault will be triggered.
> + */
> +void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_addr,
> +				   uint32_t value)


Nice name, could be even gpgpu_shader__write_a64_d32, to follow spec 
convention.


> +{
> +	uint64_t addr = CANONICAL(ppgtt_addr);
> +	igt_assert_f((addr & 0x3) == 0, "address must be aligned to DWord!\n");
> +
> +	emit_iga64_code(shdr, write_a64_dword, "				\n\
> +#if GEN_VER >= 2000								\n\
> +// Unyped 2D Block Store							\n\
> +// Instruction_Store2DBlock							\n\
> +// bspec: 63981									\n\
> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies both		\n\
> +//	the block parameters and the 2D Surface parameters.			\n\
> +// src1 data payload format is selected by Data Size.				\n\
> +// Untyped2DBLOCKAddressPayload							\n\
> +// bspec: 63986									\n\
> +// [243:240] Array Length: 0 (length is 1)					\n\
> +// [239:232] Block Height: 0 (height is 1)					\n\
> +// [231:224] Block Width: 0xf (width is 16)					\n\
> +// [223:192] Block Start Y: 0							\n\
> +// [191:160] Block Start X: 0							\n\
> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 bytes)			\n\
> +// [127:96] Untyped 2D Surface Height: 0 (height is 1)				\n\
> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 bytes)			\n\
> +// [63:0] Untyped 2D Surface Base Address					\n\
> +// initialize register								\n\
> +(W)	mov (8)			r30.0<1>:uq	0x0:uq				\n\
> +// [0:31] Untyped 2D Surface Base Address low					\n\
> +(W)	mov (1)			r30.0<1>:ud	ARG(0):ud			\n\
> +// [32:63] Untyped 2D Surface Base Address high					\n\
> +(W)	mov (1)			r30.1<1>:ud ARG(1):ud				\n\
> +// [95:64] Untyped 2D Surface Width: 0x3f					\n\
> +//	   (Width minus 1 (in bytes) of the 2D surface, it represents 64)	\n\
> +(W)	mov (1) 		r30.2<1>:ud	0x3f:ud				\n\
> +// [127:96] Untyped 2D Surface Height: 0x0					\n\
> +//	    (Height minus 1 (in number of data elements) of			\n\
> +//	    the Untyped 2D surface, it represents 1)				\n\
> +(W)	mov (1) 		r30.3<1>:ud	0x0:ud				\n\
> +// [159:128] Untyped 2D Surface Pitch: 0x3f					\n\
> +//	     (Pitch minus 1 (in bytes) of the 2D surface, it represents 64)	\n\
> +(W)	mov (1)			r30.4<1>:ud	0x3f:ud				\n\
> +// [231:224] Block Width: 0xf (15)						\n\
> +//	     (Specifies the width minus 1 (in number of data elements) for this	\n\
> +//	     rectangular region, it represents 16)				\n\
> +// Block width (encoded_value + 1) must be a multiple of DW (4 bytes).		\n\
> +// [239:232] Block Height: 0							\n\
> +//	     (Specifies the height minus 1 (in number of data elements) for	\n\
> +//	     this rectangular region, it represents 1)				\n\
> +// [243:240] Array Length: 0							\n\
> +//	     (Specifies Array Length minus 1 for Load2DBlockArray messages,	\n\
> +//	     must be zero for 2D Block Store messages, it represents 1)		\n\
> +(W)	mov (1)			r30.7<1>:ud	0xf:ud				\n\


Shouldn't this be 0x3:ud now, for dword ?

Beside those details:

Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>

Regards
Andrzej

> +// src1 data payload size							\n\
> +// Block Height x Block Width x Data size / GRF Register size			\n\
> +//	=> 1 x 16 x 32bit / 512bit = 1						\n\
> +// data payload size is 1							\n\
> +(W)	mov (8)			r31.0<1>:uq	0x0:uq				\n\
> +(W)	mov (1|M0)		r31.0<1>:ud 	ARG(2):ud			\n\
> +// send.ugm Untyped 2D Block Array Store					\n\
> +// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc				\n\
> +// Execution Mask restriction: SIMT1						\n\
> +//										\n\
> +// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D Block)	\n\
> +// bspec: 67780									\n\
> +// 0x0 =>									\n\
> +// [32:22] Global Y_offset: 0							\n\
> +// [21:12] Global X_offset: 0							\n\
> +//										\n\
> +// Message Descriptor								\n\
> +// bspec: 63981									\n\
> +// 0x2020407 =>									\n\
> +// [30:29] Address Type: 0 (FLAT)						\n\
> +// [28:25] Src0 Length: 1							\n\
> +// [24:20] Dest Length: 0							\n\
> +// [19:16] Cache : 2 (L1UC_L3UC)						\n\
> +// [11:9] Data Size: 2 (D32)							\n\
> +// [5:0] Store Operation: 7							\n\
> +(W)	send.ugm (1)		null	r30	r31:1	0x0	0x2020407	\n\
> +#endif										\n\
> +	", lower_32_bits(addr), upper_32_bits(addr), value);
> +}
> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
> index c7c21c115..18a4c9725 100644
> --- a/lib/gpgpu_shader.h
> +++ b/lib/gpgpu_shader.h
> @@ -85,6 +85,8 @@ void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
>   			       uint32_t y_offset);
>   void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, uint32_t x_offset,
>   				      uint32_t y_offset, uint32_t mask, uint32_t value);
> +void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_addr,
> +				   uint32_t value);
>   void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
>   void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
>   void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
> index 6638be07b..e97bcf042 100644
> --- a/lib/iga64_generated_codes.c
> +++ b/lib/iga64_generated_codes.c
> @@ -3,7 +3,7 @@
>   
>   #include "gpgpu_shader.h"
>   
> -#define MD5_SUM_IGA64_ASMS ec9d477415eebb7d6983395f1bcde78f
> +#define MD5_SUM_IGA64_ASMS a1ee0173014ab4cda3090faeca1cbae1
>   
>   struct iga64_template const iga64_code_gpgpu_fill[] = {
>   	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> @@ -79,6 +79,27 @@ struct iga64_template const iga64_code_gpgpu_fill[] = {
>   	}}
>   };
>   
> +struct iga64_template const iga64_code_write_a64_dword[] = {
> +	{ .gen_ver = 2000, .size = 52, .code = (const uint32_t []) {
> +		0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
> +		0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
> +		0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
> +		0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
> +		0x80000061, 0x1e354220, 0x00000000, 0x00000000,
> +		0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
> +		0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
> +		0x800c0061, 0x1f054330, 0x00000000, 0x00000000,
> +		0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
> +		0x80032031, 0x00000000, 0xf80e1e0c, 0x00801f0c,
> +		0x80000001, 0x00010000, 0x20000000, 0x00000000,
> +		0x80000001, 0x00010000, 0x30000000, 0x00000000,
> +		0x80000901, 0x00010000, 0x00000000, 0x00000000,
> +	}},
> +	{ .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
> +
> +	}}
> +};
> +
>   struct iga64_template const iga64_code_end_system_routine_step_if_eq[] = {
>   	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>   		0x80000966, 0x80018220, 0x02008000, 0x00008000,

Re: [PATCH i-g-t v2 2/4] lib/gppgu_shader: Add read D32 from ppgtt virtual address

[Hajda, Andrzej]

W dniu 21.11.2024 o 13:22, Gwan-gyeong Mun pisze:
> Create a function that adds the capabilty to read an dword size from a
> given ppgtt address. Use an Untyped 2D Block Array Load DataPort
> functionality of XE2+ with A64 flat addressing to direct accessing an
> entire ppgtt address space.
>
> For the read to succeed, the given ppgtt virtual address has to be bound.
> Otherwise a load page fault will be triggered.
>
> v2: Fix the function name to be more clear. (Christoph)
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>   lib/gpgpu_shader.c          | 94 +++++++++++++++++++++++++++++++++++++
>   lib/gpgpu_shader.h          |  1 +
>   lib/iga64_generated_codes.c | 21 ++++++++-
>   3 files changed, 115 insertions(+), 1 deletion(-)
>
> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
> index d9da35895..147df3a3d 100644
> --- a/lib/gpgpu_shader.c
> +++ b/lib/gpgpu_shader.c
> @@ -897,3 +897,97 @@ void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_add
>   #endif										\n\
>   	", lower_32_bits(addr), upper_32_bits(addr), value);
>   }
> +
> +/**
> + * gpgpu_shader__read_a64_dword:
> + * @shdr: shader to be modified
> + * @ppgtt_addr: read target ppgtt virtual address
> + *
> + * Read one D32 data (DW; DoubleWord) directly from the target ppgtt virtual
> + * address (A64 Flat Address model).
> + *
> + * Note: for the read to succeed, the address specified by @ppgtt_addr has
> + * to be bound. Otherwise a load page fault will be triggered.
> + */
> +void gpgpu_shader__read_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_addr)
> +{
> +	uint64_t addr = CANONICAL(ppgtt_addr);
> +
> +	igt_assert_f((addr & 0x3) == 0, "address must be aligned to DWord!\n");
> +
> +	emit_iga64_code(shdr, read_a64_dword, "					\n\
> +#if GEN_VER >= 2000								\n\
> +// Unyped 2D Block Array Load 							\n\
> +// Instruction_Load2DBlockArray							\n\
> +// bspec: 63972									\n\
> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies both		\n\
> +//	the block parameters and the 2D Surface parameters.			\n\
> +// Untyped2DBLOCKAddressPayload							\n\
> +// bspec: 63986									\n\
> +// [243:240] Array Length: 0 (length is 1)					\n\
> +// [239:232] Block Height: 0 (height is 1)					\n\
> +// [231:224] Block Width: 0xf (width is 16)					\n\
> +// [223:192] Block Start Y: 0							\n\
> +// [191:160] Block Start X: 0							\n\
> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 bytes)			\n\
> +// [127:96] Untyped 2D Surface Height: 0 (height is 1)				\n\
> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 bytes)			\n\
> +// [63:0] Untyped 2D Surface Base Address					\n\
> +// initialize register								\n\
> +(W)	mov (8)			r30.0<1>:uq	0x0:uq				\n\
> +// [0:31] Untyped 2D Surface Base Address low					\n\
> +(W)	mov (1)			r30.0<1>:ud	ARG(0):ud			\n\
> +// [32:63] Untyped 2D Surface Base Address high					\n\
> +(W)	mov (1)			r30.1<1>:ud ARG(1):ud				\n\
> +// [95:64] Untyped 2D Surface Width: 0x3f					\n\
> +//	   (Width minus 1 (in bytes) of the 2D surface, it represents 64)	\n\
> +(W)	mov (1) 		r30.2<1>:ud	0x3f:ud				\n\
> +// [127:96] Untyped 2D Surface Height: 0x0					\n\
> +//	    (Height minus 1 (in number of data elements) of			\n\
> +//	    the Untyped 2D surface, it represents 1)				\n\
> +(W)	mov (1) 		r30.3<1>:ud	0x0:ud				\n\


No need to setting to 0 twice.


> +// [159:128] Untyped 2D Surface Pitch: 0x3f					\n\
> +//	     (Pitch minus 1 (in bytes) of the 2D surface, it represents 64)	\n\
> +(W)	mov (1)			r30.4<1>:ud	0x3f:ud				\n\
> +// [231:224] Block Width: 0xf (15)						\n\
> +//	     (Specifies the width minus 1 (in number of data elements) for this	\n\
> +//	     rectangular region, it represents 16)				\n\
> +// Block width (encoded_value + 1) must be a multiple of DW (4 bytes).		\n\
> +// [239:232] Block Height: 0							\n\
> +//	     (Specifies the height minus 1 (in number of data elements) for	\n\
> +//	     this rectangular region, it represents 1)				\n\
> +// [243:240] Array Length: 0							\n\
> +//	     (Specifies Array Length minus 1 for Load2DBlockArray messages,	\n\
> +//	     must be zero for 2D Block Store messages, it represents 1)		\n\
> +(W)	mov (1)			r30.7<1>:ud	0xf:ud				\n\


Again maybe 0x3.


> +//										\n\
> +// dest data payload format is selected by Data Size.				\n\
> +// Block Height x Block Width x Data size / GRF Register size			\n\
> +//	=> 1 x 16 x 32bit / 512bit = 1						\n\
> +// data payload format size is 1 GRF Register.					\n\
> +//										\n\
> +// send.ugm Untyped 2D Block Array Load						\n\
> +// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc				\n\
> +// Execution Mask restriction: SIMT1						\n\
> +//										\n\
> +// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D Block)	\n\
> +// bspec: 67780									\n\
> +// 0x0 =>									\n\
> +// [32:22] Global Y_offset: 0							\n\
> +// [21:12] Global X_offset: 0							\n\
> +//										\n\
> +// Message Descriptor								\n\
> +// bspec: 63972									\n\
> +// 0x2128403 =>									\n\
> +// [30:29] Address Type: 0 (FLAT)						\n\
> +// [28:25] Src0 Length: 1							\n\
> +// [24:20] Dest Length: 1							\n\
> +// [19:16] Cache : 2 (L1UC_L3UC) 10						\n\
> +// [15] Transpose Block: 1							\n\
> +// [11:9] Data Size: 2 (D32) 10							\n\
> +// [7] VNNI Transform: 0							\n\
> +// [5:0] Load Operation: 3 (Load 2D Block) 11					\n\
> +(W)	send.ugm (1)		r31	r30	null	0x0	0x2128403	\n\
> +#endif										\n\
> +	", lower_32_bits(addr), upper_32_bits(addr));

Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>

Regards
Andrzej

> +}
> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
> index 18a4c9725..07ed0fe1b 100644
> --- a/lib/gpgpu_shader.h
> +++ b/lib/gpgpu_shader.h
> @@ -87,6 +87,7 @@ void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, ui
>   				      uint32_t y_offset, uint32_t mask, uint32_t value);
>   void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_addr,
>   				   uint32_t value);
> +void gpgpu_shader__read_a64_dword(struct gpgpu_shader *shdr, uint64_t ppgtt_addr);
>   void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
>   void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
>   void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
> index e97bcf042..721ac267f 100644
> --- a/lib/iga64_generated_codes.c
> +++ b/lib/iga64_generated_codes.c
> @@ -3,7 +3,7 @@
>   
>   #include "gpgpu_shader.h"
>   
> -#define MD5_SUM_IGA64_ASMS a1ee0173014ab4cda3090faeca1cbae1
> +#define MD5_SUM_IGA64_ASMS bdc80eeb9a11b97ff51422a39f4623f5
>   
>   struct iga64_template const iga64_code_gpgpu_fill[] = {
>   	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> @@ -79,6 +79,25 @@ struct iga64_template const iga64_code_gpgpu_fill[] = {
>   	}}
>   };
>   
> +struct iga64_template const iga64_code_read_a64_dword[] = {
> +	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> +		0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
> +		0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
> +		0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
> +		0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
> +		0x80000061, 0x1e354220, 0x00000000, 0x00000000,
> +		0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
> +		0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
> +		0x80032031, 0x1f0c0000, 0xf8061e0c, 0x00a00000,
> +		0x80000001, 0x00010000, 0x20000000, 0x00000000,
> +		0x80000001, 0x00010000, 0x30000000, 0x00000000,
> +		0x80000901, 0x00010000, 0x00000000, 0x00000000,
> +	}},
> +	{ .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
> +
> +	}}
> +};
> +
>   struct iga64_template const iga64_code_write_a64_dword[] = {
>   	{ .gen_ver = 2000, .size = 52, .code = (const uint32_t []) {
>   		0x800c0061, 0x1e054330, 0x00000000, 0x00000000,

Re: [PATCH i-g-t v2 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests

[Hajda, Andrzej]

W dniu 21.11.2024 o 13:22, Gwan-gyeong Mun pisze:
> Add read and write pagefault tests to xe_eudebug_online that checks if a
> pagefault event is submitted by the KMD debugger when a pagefault occurs.
>
> Test that read (load instruction) and write(store instruction) attempt to
> load or store access to unallocated memory, causing a pagefault.
> Examine the address causing the page fault and the number of eu threads
> causing the pagefault.
>
> v2: Refactor of output attention bits on pagefault event handling (Andrzej)
>      remove / update redudant code (Andrzej, Christoph)
>      use igt_container_of() macro (Christoph)
>
> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>


Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>

Regards
Andrzej

> ---
>   tests/intel/xe_eudebug_online.c | 178 +++++++++++++++++++++++++++++++-
>   1 file changed, 173 insertions(+), 5 deletions(-)
>
> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/xe_eudebug_online.c
> index 0ef0d8093..a70d18ee4 100644
> --- a/tests/intel/xe_eudebug_online.c
> +++ b/tests/intel/xe_eudebug_online.c
> @@ -36,6 +36,8 @@
>   #define BB_IN_VRAM			(1 << 11)
>   #define TARGET_IN_SRAM			(1 << 12)
>   #define TARGET_IN_VRAM			(1 << 13)
> +#define SHADER_PAGEFAULT_READ		(1 << 14)
> +#define SHADER_PAGEFAULT_WRITE		(1 << 15)
>   #define TRIGGER_UFENCE_SET_BREAKPOINT	(1 << 24)
>   #define TRIGGER_RESUME_SINGLE_WALK	(1 << 25)
>   #define TRIGGER_RESUME_PARALLEL_WALK	(1 << 26)
> @@ -45,6 +47,7 @@
>   #define TRIGGER_RESUME_DSS		(1 << 30)
>   #define TRIGGER_RESUME_ONE		(1 << 31)
>   
> +#define SHADER_PAGEFAULT	(SHADER_PAGEFAULT_READ | SHADER_PAGEFAULT_WRITE)
>   #define BB_REGION_BITMASK	(BB_IN_SRAM | BB_IN_VRAM)
>   #define TARGET_REGION_BITMASK	(TARGET_IN_SRAM | TARGET_IN_VRAM)
>   
> @@ -61,6 +64,8 @@
>   #define CACHING_VALUE(n)	(CACHING_INIT_VALUE + (n))
>   
>   #define SHADER_CANARY 0x01010101
> +#define BAD_CANARY 0xf1f1f1f
> +#define BAD_OFFSET (0x12345678ull << 12)
>   
>   #define WALKER_X_DIM		4
>   #define WALKER_ALIGNMENT	16
> @@ -120,7 +125,7 @@ static struct intel_buf *create_uc_buf(int fd, int width, int height, uint64_t r
>   
>   static int get_number_of_threads(uint64_t flags)
>   {
> -	if (flags & SHADER_MIN_THREADS)
> +	if (flags & (SHADER_MIN_THREADS | SHADER_PAGEFAULT))
>   		return 16;
>   
>   	if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
> @@ -179,6 +184,16 @@ static struct gpgpu_shader *get_shader(int fd, const unsigned int flags)
>   			gpgpu_shader__common_target_write_u32(shader, s_dim.y + i, CACHING_VALUE(i));
>   		gpgpu_shader__nop(shader);
>   		gpgpu_shader__breakpoint(shader);
> +	} else if (flags & SHADER_PAGEFAULT) {
> +		if (flags & SHADER_PAGEFAULT_READ)
> +			gpgpu_shader__read_a64_dword(shader, BAD_OFFSET);
> +		else
> +			gpgpu_shader__write_a64_dword(shader, BAD_OFFSET, BAD_CANARY);
> +
> +		gpgpu_shader__label(shader, 0);
> +		gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
> +		gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
> +		gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>   	}
>   
>   	gpgpu_shader__eot(shader);
> @@ -217,6 +232,16 @@ static int count_set_bits(void *ptr, size_t size)
>   	return count;
>   }
>   
> +static int eu_attentions_xor_count(const uint32_t *a, const uint32_t *b, uint32_t size)
> +{
> +	int count = 0;
> +
> +	for (int i = 0; i < size / 4 ; i++)
> +		count += igt_hweight(a[i] ^ b[i]);
> +
> +	return count;
> +}
> +
>   static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim, uint32_t value)
>   {
>   	int count = 0;
> @@ -636,7 +661,7 @@ static void eu_attention_resume_trigger(struct xe_eudebug_debugger *d,
>   		}
>   	}
>   
> -	if (d->flags & SHADER_LOOP) {
> +	if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
>   		uint32_t threads = get_number_of_threads(d->flags);
>   		uint32_t val = STEERING_END_LOOP;
>   
> @@ -746,6 +771,44 @@ static void eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
>   			data->single_step_bitmask[i] &= ~att->bitmask[i];
>   }
>   
> +static void eu_attention_resume_pagefault_trigger(struct xe_eudebug_debugger *d,
> +						  struct drm_xe_eudebug_event *e)
> +{
> +	struct drm_xe_eudebug_event_eu_attention *att = igt_container_of(e, att, base);
> +	struct online_debug_data *data = d->ptr;
> +	uint32_t bitmask_size = att->bitmask_size;
> +	uint8_t *bitmask;
> +
> +	if (data->last_eu_control_seqno > att->base.seqno)
> +		return;
> +
> +	bitmask = calloc(1, att->bitmask_size);
> +	igt_assert(bitmask);
> +
> +	eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
> +		       att->lrc_handle, bitmask, &bitmask_size);
> +	igt_assert(bitmask_size == att->bitmask_size);
> +
> +	pthread_mutex_lock(&data->mutex);
> +
> +	if (d->flags & SHADER_PAGEFAULT) {
> +		uint32_t threads = get_number_of_threads(d->flags);
> +		uint32_t val = STEERING_END_LOOP;
> +
> +		igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
> +				     data->target_offset + steering_offset(threads)),
> +			      sizeof(uint32_t));
> +		fsync(data->vm_fd);
> +	}
> +	pthread_mutex_unlock(&data->mutex);
> +
> +	data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, att->client_handle,
> +						    att->exec_queue_handle, att->lrc_handle,
> +						    bitmask, att->bitmask_size);
> +
> +	free(bitmask);
> +}
> +
>   static void open_trigger(struct xe_eudebug_debugger *d,
>   			 struct drm_xe_eudebug_event *e)
>   {
> @@ -1015,7 +1078,7 @@ static void run_online_client(struct xe_eudebug_client *c)
>   	struct intel_bb *ibb;
>   	struct intel_buf *buf;
>   	uint32_t *ptr;
> -	int fd;
> +	int fd, vm_flags;
>   
>   	metadata[0] = calloc(2, sizeof(*metadata));
>   	metadata[1] = calloc(2, sizeof(*metadata));
> @@ -1025,7 +1088,7 @@ static void run_online_client(struct xe_eudebug_client *c)
>   	fd = xe_eudebug_client_open_driver(c);
>   
>   	/* Additional memory for steering control */
> -	if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
> +	if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || c->flags & SHADER_PAGEFAULT)
>   		s_dim.y++;
>   	/* Additional memory for caching check */
>   	if ((c->flags & SHADER_CACHING_SRAM) || (c->flags & SHADER_CACHING_VRAM))
> @@ -1045,7 +1108,11 @@ static void run_online_client(struct xe_eudebug_client *c)
>   							   DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
>   							   2 * sizeof(*metadata), metadata[1]);
>   
> -	create.vm_id = xe_eudebug_client_vm_create(c, fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> +	vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
> +	vm_flags |= c->flags & SHADER_PAGEFAULT ? DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
> +
> +	create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
> +
>   	xe_eudebug_client_exec_queue_create(c, fd, &create);
>   
>   	ibb = xe_bb_create_on_offset(fd, create.exec_queue_id, create.vm_id, bb_offset, bb_size,
> @@ -1245,11 +1312,13 @@ match_attention_with_exec_queue(struct xe_eudebug_event_log *log,
>   static void online_session_check(struct xe_eudebug_session *s, int flags)
>   {
>   	struct drm_xe_eudebug_event_eu_attention *ea = NULL;
> +	struct drm_xe_eudebug_event_pagefault *pf = NULL;
>   	struct drm_xe_eudebug_event *event = NULL;
>   	struct online_debug_data *data = s->client->ptr;
>   	bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
>   	int sum = 0;
>   	int bitmask_size;
> +	int pagefault_threads = 0;
>   
>   	xe_eudebug_session_check(s, true, XE_EUDEBUG_FILTER_EVENT_VM_BIND |
>   					  XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
> @@ -1265,6 +1334,17 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
>   			igt_assert_eq(ea->bitmask_size, bitmask_size);
>   			sum += count_set_bits(ea->bitmask, bitmask_size);
>   			igt_assert(match_attention_with_exec_queue(s->debugger->log, ea));
> +		} else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
> +			uint32_t after_offset = bitmask_size / sizeof(uint32_t);
> +			uint32_t resolved_offset = bitmask_size / sizeof(uint32_t) * 2;
> +			uint32_t *ptr = NULL;
> +
> +			pf = igt_container_of(event, pf, base);
> +			ptr = (uint32_t *) pf->bitmask;
> +			igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
> +			pagefault_threads += eu_attentions_xor_count(ptr + after_offset,
> +								     ptr + resolved_offset,
> +								     bitmask_size);
>   		}
>   	}
>   
> @@ -1279,6 +1359,9 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
>   		igt_assert(sum > 0);
>   	else
>   		igt_assert(sum == 0);
> +
> +	if (flags & SHADER_PAGEFAULT)
> +		igt_assert(pagefault_threads > 0);
>   }
>   
>   static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
> @@ -1302,6 +1385,43 @@ static void ufence_ack_set_bp_trigger(struct xe_eudebug_debugger *d,
>   	}
>   }
>   
> +static void pagefault_trigger(struct xe_eudebug_debugger *d,
> +			      struct drm_xe_eudebug_event *e)
> +{
> +	struct drm_xe_eudebug_event_pagefault *pf = igt_container_of(e, pf, base);
> +	uint32_t attn_size = pf->bitmask_size / 3;
> +	int attn_size_as_u32 = attn_size / sizeof(uint32_t);
> +	uint32_t *ptr = (uint32_t *) pf->bitmask;
> +	uint32_t *ptrs[3] = {ptr, ptr + attn_size_as_u32, ptr + 2 * attn_size_as_u32};
> +	const char * const name[3] = {"before", "after", "resolved"};
> +	int threads[3], pagefault_threads, idx;
> +
> +	for (idx = 0; idx < 3; idx++)
> +		threads[idx] = count_set_bits(ptrs[idx], attn_size);
> +
> +	pagefault_threads = eu_attentions_xor_count(ptrs[1], ptrs[2], attn_size);
> +
> +	igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
> +		  "resolved=%d, pagefault=%d] "
> +		  "client[%llu], exec_queue[%llu], lrc[%llu], bitmask_size[%d], "
> +		  "pagefault_address[0x%llx]\n",
> +		  pf->base.seqno, threads[0], threads[1], threads[2],
> +		  pagefault_threads, pf->client_handle, pf->exec_queue_handle,
> +		  pf->lrc_handle, pf->bitmask_size,
> +		  pf->pagefault_address);
> +
> +	for (idx = 0; idx < 3; idx++) {
> +		igt_debug("=== Attentions %s ===\n", name[idx]);
> +
> +		for (uint32_t i = 0; i < attn_size_as_u32; i += 2)
> +			igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
> +				  ptrs[idx][i], ptrs[idx][i + 1]);
> +	}
> +
> +	igt_assert(pagefault_threads > 0);
> +	igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
> +}
> +
>   /**
>    * SUBTEST: basic-breakpoint
>    * Description:
> @@ -1383,6 +1503,49 @@ static void test_set_breakpoint_online(int fd, struct drm_xe_engine_class_instan
>   	online_debug_data_destroy(data);
>   }
>   
> +/**
> + * SUBTEST: pagefault-read
> + * Description:
> + *     Check whether KMD sends pagefault event for workload in debug mode that
> + *     triggers a read pagefault.
> + *
> + * SUBTEST: pagefault-write
> + * Description:
> + *     Check whether KMD sends pagefault event for workload in debug mode that
> + *     triggers a write pagefault.
> + */
> +static void test_pagefault_online(int fd, struct drm_xe_engine_class_instance *hwe,
> +				  int flags)
> +{
> +	struct xe_eudebug_session *s;
> +	struct online_debug_data *data;
> +
> +	data = online_debug_data_create(hwe);
> +	s = xe_eudebug_session_create(fd, run_online_client, flags, data);
> +
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_OPEN,
> +					open_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
> +					exec_queue_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
> +					eu_attention_debug_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
> +					eu_attention_resume_pagefault_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_METADATA,
> +					create_metadata_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
> +					ufence_ack_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
> +					pagefault_trigger);
> +
> +	xe_eudebug_session_run(s);
> +	online_session_check(s, s->flags);
> +
> +	xe_eudebug_session_destroy(s);
> +	online_debug_data_destroy(data);
> +}
> +
>   /**
>    * SUBTEST: preempt-breakpoint
>    * Description:
> @@ -2344,6 +2507,11 @@ igt_main
>   	igt_subtest("breakpoint-many-sessions-tiles")
>   		test_many_sessions_on_tiles(fd, true);
>   
> +	test_gt_render_or_compute("pagefault-read", fd, hwe)
> +		test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
> +	test_gt_render_or_compute("pagefault-write", fd, hwe)
> +		test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
> +
>   	igt_fixture {
>   		xe_eudebug_enable(fd, was_enabled);
>   

Re: [PATCH i-g-t v2 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests

[Manszewski, Christoph]

Hi Gwan-gyeong,

On 21.11.2024 13:22, Gwan-gyeong Mun wrote:
> Add read and write pagefault tests to xe_eudebug_online that checks if a
> pagefault event is submitted by the KMD debugger when a pagefault occurs.
> 
> Test that read (load instruction) and write(store instruction) attempt to
> load or store access to unallocated memory, causing a pagefault.
> Examine the address causing the page fault and the number of eu threads
> causing the pagefault.
> 
> v2: Refactor of output attention bits on pagefault event handling (Andrzej)
>      remove / update redudant code (Andrzej, Christoph)
>      use igt_container_of() macro (Christoph)
> 
> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>   tests/intel/xe_eudebug_online.c | 178 +++++++++++++++++++++++++++++++-
>   1 file changed, 173 insertions(+), 5 deletions(-)
> 
> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/xe_eudebug_online.c
> index 0ef0d8093..a70d18ee4 100644
> --- a/tests/intel/xe_eudebug_online.c
> +++ b/tests/intel/xe_eudebug_online.c
> @@ -36,6 +36,8 @@
>   #define BB_IN_VRAM			(1 << 11)
>   #define TARGET_IN_SRAM			(1 << 12)
>   #define TARGET_IN_VRAM			(1 << 13)
> +#define SHADER_PAGEFAULT_READ		(1 << 14)
> +#define SHADER_PAGEFAULT_WRITE		(1 << 15)
>   #define TRIGGER_UFENCE_SET_BREAKPOINT	(1 << 24)
>   #define TRIGGER_RESUME_SINGLE_WALK	(1 << 25)
>   #define TRIGGER_RESUME_PARALLEL_WALK	(1 << 26)
> @@ -45,6 +47,7 @@
>   #define TRIGGER_RESUME_DSS		(1 << 30)
>   #define TRIGGER_RESUME_ONE		(1 << 31)
>   
> +#define SHADER_PAGEFAULT	(SHADER_PAGEFAULT_READ | SHADER_PAGEFAULT_WRITE)
>   #define BB_REGION_BITMASK	(BB_IN_SRAM | BB_IN_VRAM)
>   #define TARGET_REGION_BITMASK	(TARGET_IN_SRAM | TARGET_IN_VRAM)
>   
> @@ -61,6 +64,8 @@
>   #define CACHING_VALUE(n)	(CACHING_INIT_VALUE + (n))
>   
>   #define SHADER_CANARY 0x01010101
> +#define BAD_CANARY 0xf1f1f1f
> +#define BAD_OFFSET (0x12345678ull << 12)
>   
>   #define WALKER_X_DIM		4
>   #define WALKER_ALIGNMENT	16
> @@ -120,7 +125,7 @@ static struct intel_buf *create_uc_buf(int fd, int width, int height, uint64_t r
>   
>   static int get_number_of_threads(uint64_t flags)
>   {
> -	if (flags & SHADER_MIN_THREADS)
> +	if (flags & (SHADER_MIN_THREADS | SHADER_PAGEFAULT))
>   		return 16;
>   
>   	if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
> @@ -179,6 +184,16 @@ static struct gpgpu_shader *get_shader(int fd, const unsigned int flags)
>   			gpgpu_shader__common_target_write_u32(shader, s_dim.y + i, CACHING_VALUE(i));
>   		gpgpu_shader__nop(shader);
>   		gpgpu_shader__breakpoint(shader);
> +	} else if (flags & SHADER_PAGEFAULT) {
> +		if (flags & SHADER_PAGEFAULT_READ)
> +			gpgpu_shader__read_a64_dword(shader, BAD_OFFSET);
> +		else
> +			gpgpu_shader__write_a64_dword(shader, BAD_OFFSET, BAD_CANARY);
> +
> +		gpgpu_shader__label(shader, 0);
> +		gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
> +		gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
> +		gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);

Now that I think about - do we need this to be a loop? Can't we just do 
the read/write instructions? This would simplify the code and I don't 
yet see why we need to loop within the shader. The SHADER_LOOP is used 
for interrupt-all because we want to interrupt the workload from the 
user/main igt thread. But here, similar to the basic-breakpoint test, we 
just submit a workload that will halt because of the hardware/kmd 
intervention.

>   	}
>   
>   	gpgpu_shader__eot(shader);
> @@ -217,6 +232,16 @@ static int count_set_bits(void *ptr, size_t size)
>   	return count;
>   }
>   
> +static int eu_attentions_xor_count(const uint32_t *a, const uint32_t *b, uint32_t size)
> +{
> +	int count = 0;
> +
> +	for (int i = 0; i < size / 4 ; i++)
> +		count += igt_hweight(a[i] ^ b[i]);
> +
> +	return count;
> +}
> +
>   static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim, uint32_t value)
>   {
>   	int count = 0;
> @@ -636,7 +661,7 @@ static void eu_attention_resume_trigger(struct xe_eudebug_debugger *d,
>   		}
>   	}
>   
> -	if (d->flags & SHADER_LOOP) {
> +	if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {

If we drop the loop we can drop also this.

>   		uint32_t threads = get_number_of_threads(d->flags);
>   		uint32_t val = STEERING_END_LOOP;
>   
> @@ -746,6 +771,44 @@ static void eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
>   			data->single_step_bitmask[i] &= ~att->bitmask[i];
>   }
>   
> +static void eu_attention_resume_pagefault_trigger(struct xe_eudebug_debugger *d,
> +						  struct drm_xe_eudebug_event *e)
> +{
> +	struct drm_xe_eudebug_event_eu_attention *att = igt_container_of(e, att, base);
> +	struct online_debug_data *data = d->ptr;
> +	uint32_t bitmask_size = att->bitmask_size;
> +	uint8_t *bitmask;
> +
> +	if (data->last_eu_control_seqno > att->base.seqno)
> +		return;
> +
> +	bitmask = calloc(1, att->bitmask_size);
> +	igt_assert(bitmask);
> +
> +	eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
> +		       att->lrc_handle, bitmask, &bitmask_size);
> +	igt_assert(bitmask_size == att->bitmask_size);
> +
> +	pthread_mutex_lock(&data->mutex);
> +
> +	if (d->flags & SHADER_PAGEFAULT) {
> +		uint32_t threads = get_number_of_threads(d->flags);
> +		uint32_t val = STEERING_END_LOOP;
> +
> +		igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
> +				     data->target_offset + steering_offset(threads)),
> +			      sizeof(uint32_t));
> +		fsync(data->vm_fd);
> +	}

We can also drop this when we remove the loop. Btw. why can't we just 
use 'eu_attention_resume_trigger' instead of this whole function?

> +	pthread_mutex_unlock(&data->mutex);
> +
> +	data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, att->client_handle,
> +						    att->exec_queue_handle, att->lrc_handle,
> +						    bitmask, att->bitmask_size);
> +
> +	free(bitmask);
> +}
> +
>   static void open_trigger(struct xe_eudebug_debugger *d,
>   			 struct drm_xe_eudebug_event *e)
>   {
> @@ -1015,7 +1078,7 @@ static void run_online_client(struct xe_eudebug_client *c)
>   	struct intel_bb *ibb;
>   	struct intel_buf *buf;
>   	uint32_t *ptr;
> -	int fd;
> +	int fd, vm_flags;
>   
>   	metadata[0] = calloc(2, sizeof(*metadata));
>   	metadata[1] = calloc(2, sizeof(*metadata));
> @@ -1025,7 +1088,7 @@ static void run_online_client(struct xe_eudebug_client *c)
>   	fd = xe_eudebug_client_open_driver(c);
>   
>   	/* Additional memory for steering control */
> -	if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
> +	if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || c->flags & SHADER_PAGEFAULT)
>   		s_dim.y++;
>   	/* Additional memory for caching check */
>   	if ((c->flags & SHADER_CACHING_SRAM) || (c->flags & SHADER_CACHING_VRAM))
> @@ -1045,7 +1108,11 @@ static void run_online_client(struct xe_eudebug_client *c)
>   							   DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
>   							   2 * sizeof(*metadata), metadata[1]);
>   
> -	create.vm_id = xe_eudebug_client_vm_create(c, fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> +	vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
> +	vm_flags |= c->flags & SHADER_PAGEFAULT ? DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
> +
> +	create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
> +
>   	xe_eudebug_client_exec_queue_create(c, fd, &create);
>   
>   	ibb = xe_bb_create_on_offset(fd, create.exec_queue_id, create.vm_id, bb_offset, bb_size,
> @@ -1245,11 +1312,13 @@ match_attention_with_exec_queue(struct xe_eudebug_event_log *log,
>   static void online_session_check(struct xe_eudebug_session *s, int flags)
>   {
>   	struct drm_xe_eudebug_event_eu_attention *ea = NULL;
> +	struct drm_xe_eudebug_event_pagefault *pf = NULL;
>   	struct drm_xe_eudebug_event *event = NULL;
>   	struct online_debug_data *data = s->client->ptr;
>   	bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
>   	int sum = 0;
>   	int bitmask_size;
> +	int pagefault_threads = 0;
>   
>   	xe_eudebug_session_check(s, true, XE_EUDEBUG_FILTER_EVENT_VM_BIND |
>   					  XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
> @@ -1265,6 +1334,17 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
>   			igt_assert_eq(ea->bitmask_size, bitmask_size);
>   			sum += count_set_bits(ea->bitmask, bitmask_size);
>   			igt_assert(match_attention_with_exec_queue(s->debugger->log, ea));
> +		} else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
> +			uint32_t after_offset = bitmask_size / sizeof(uint32_t);
> +			uint32_t resolved_offset = bitmask_size / sizeof(uint32_t) * 2;
> +			uint32_t *ptr = NULL;
> +
> +			pf = igt_container_of(event, pf, base);
> +			ptr = (uint32_t *) pf->bitmask;
> +			igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
> +			pagefault_threads += eu_attentions_xor_count(ptr + after_offset,
> +								     ptr + resolved_offset,
> +								     bitmask_size);
>   		}
>   	}
>   
> @@ -1279,6 +1359,9 @@ static void online_session_check(struct xe_eudebug_session *s, int flags)
>   		igt_assert(sum > 0);
>   	else
>   		igt_assert(sum == 0);
> +
> +	if (flags & SHADER_PAGEFAULT)
> +		igt_assert(pagefault_threads > 0);
>   }
>   
>   static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
> @@ -1302,6 +1385,43 @@ static void ufence_ack_set_bp_trigger(struct xe_eudebug_debugger *d,
>   	}
>   }
>   
> +static void pagefault_trigger(struct xe_eudebug_debugger *d,
> +			      struct drm_xe_eudebug_event *e)
> +{
> +	struct drm_xe_eudebug_event_pagefault *pf = igt_container_of(e, pf, base);
> +	uint32_t attn_size = pf->bitmask_size / 3;
> +	int attn_size_as_u32 = attn_size / sizeof(uint32_t);
> +	uint32_t *ptr = (uint32_t *) pf->bitmask;
> +	uint32_t *ptrs[3] = {ptr, ptr + attn_size_as_u32, ptr + 2 * attn_size_as_u32};
> +	const char * const name[3] = {"before", "after", "resolved"};
> +	int threads[3], pagefault_threads, idx;
> +
> +	for (idx = 0; idx < 3; idx++)
> +		threads[idx] = count_set_bits(ptrs[idx], attn_size);
> +
> +	pagefault_threads = eu_attentions_xor_count(ptrs[1], ptrs[2], attn_size);
> +
> +	igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
> +		  "resolved=%d, pagefault=%d] "
> +		  "client[%llu], exec_queue[%llu], lrc[%llu], bitmask_size[%d], "
> +		  "pagefault_address[0x%llx]\n",
> +		  pf->base.seqno, threads[0], threads[1], threads[2],
> +		  pagefault_threads, pf->client_handle, pf->exec_queue_handle,
> +		  pf->lrc_handle, pf->bitmask_size,
> +		  pf->pagefault_address);
> +
> +	for (idx = 0; idx < 3; idx++) {
> +		igt_debug("=== Attentions %s ===\n", name[idx]);
> +
> +		for (uint32_t i = 0; i < attn_size_as_u32; i += 2)
> +			igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
> +				  ptrs[idx][i], ptrs[idx][i + 1]);
> +	}
> +
> +	igt_assert(pagefault_threads > 0);
> +	igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
> +}
> +
>   /**
>    * SUBTEST: basic-breakpoint
>    * Description:
> @@ -1383,6 +1503,49 @@ static void test_set_breakpoint_online(int fd, struct drm_xe_engine_class_instan
>   	online_debug_data_destroy(data);
>   }
>   
> +/**
> + * SUBTEST: pagefault-read
> + * Description:
> + *     Check whether KMD sends pagefault event for workload in debug mode that
> + *     triggers a read pagefault.
> + *
> + * SUBTEST: pagefault-write
> + * Description:
> + *     Check whether KMD sends pagefault event for workload in debug mode that
> + *     triggers a write pagefault.
> + */
> +static void test_pagefault_online(int fd, struct drm_xe_engine_class_instance *hwe,
> +				  int flags)
> +{
> +	struct xe_eudebug_session *s;
> +	struct online_debug_data *data;
> +
> +	data = online_debug_data_create(hwe);
> +	s = xe_eudebug_session_create(fd, run_online_client, flags, data);
> +
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_OPEN,
> +					open_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
> +					exec_queue_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
> +					eu_attention_debug_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
> +					eu_attention_resume_pagefault_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_METADATA,
> +					create_metadata_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
> +					ufence_ack_trigger);
> +	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
> +					pagefault_trigger);

Removing the loop would make it possible to reduce this to 3 triggers.

So again, I may be missing some detail that implies we need a loop in 
the shader. But for now it looks to me like we don't.

Thanks,
Christoph

> +
> +	xe_eudebug_session_run(s);
> +	online_session_check(s, s->flags);
> +
> +	xe_eudebug_session_destroy(s);
> +	online_debug_data_destroy(data);
> +}
> +
>   /**
>    * SUBTEST: preempt-breakpoint
>    * Description:
> @@ -2344,6 +2507,11 @@ igt_main
>   	igt_subtest("breakpoint-many-sessions-tiles")
>   		test_many_sessions_on_tiles(fd, true);
>   
> +	test_gt_render_or_compute("pagefault-read", fd, hwe)
> +		test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
> +	test_gt_render_or_compute("pagefault-write", fd, hwe)
> +		test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
> +
>   	igt_fixture {
>   		xe_eudebug_enable(fd, was_enabled);
>   

✗ Xe.CI.Full: failure for tests/intel/xe_eudebug_online: Introduce read/write pagefault tests (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 137878 bytes --]

== Series Details ==

Series: tests/intel/xe_eudebug_online: Introduce read/write pagefault tests (rev2)
URL   : https://patchwork.freedesktop.org/series/141401/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8118_full -> XEIGTPW_12158_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_12158_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_12158_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_12158_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4:
    - shard-dg2-set2:     [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][3]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][4]
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][5] +1 other test dmesg-warn
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * {igt@xe_eudebug_online@pagefault-read} (NEW):
    - shard-bmg:          NOTRUN -> [SKIP][6] +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@xe_eudebug_online@pagefault-read.html
    - shard-lnl:          NOTRUN -> [SKIP][7] +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-3/igt@xe_eudebug_online@pagefault-read.html

  * igt@xe_exec_compute_mode@many-execqueues-bindexecqueue-userptr-rebind:
    - shard-lnl:          [PASS][8] -> [FAIL][9]
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-7/igt@xe_exec_compute_mode@many-execqueues-bindexecqueue-userptr-rebind.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-5/igt@xe_exec_compute_mode@many-execqueues-bindexecqueue-userptr-rebind.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank@c-dp2:
    - shard-bmg:          [DMESG-WARN][10] ([Intel XE#3468]) -> [FAIL][11]
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-5/igt@kms_flip@flip-vs-expired-vblank@c-dp2.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_flip@flip-vs-expired-vblank@c-dp2.html

  * igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_prepare:
    - shard-lnl:          [FAIL][12] ([Intel XE#3499]) -> [FAIL][13] +4 other tests fail
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-6/igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_prepare.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-3/igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_prepare.html

  * igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_run:
    - shard-bmg:          [FAIL][14] ([Intel XE#3499]) -> [FAIL][15]
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-2/igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_run.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_run.html

  * igt@xe_module_load@reload:
    - shard-bmg:          [DMESG-WARN][16] ([Intel XE#3468]) -> [DMESG-WARN][17]
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-1/igt@xe_module_load@reload.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@xe_module_load@reload.html

  
New tests
---------

  New tests have been introduced between XEIGT_8118_full and XEIGTPW_12158_full:

### New IGT tests (2) ###

  * igt@xe_eudebug_online@pagefault-read:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_eudebug_online@pagefault-write:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_12158_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_getversion@basic:
    - shard-dg2-set2:     NOTRUN -> [FAIL][18] ([Intel XE#3440])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@core_getversion@basic.html

  * igt@core_hotunplug@unplug-rescan:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#1885])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@core_hotunplug@unplug-rescan.html

  * igt@fbdev@info:
    - shard-dg2-set2:     [PASS][20] -> [SKIP][21] ([Intel XE#2134])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@fbdev@info.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@fbdev@info.html

  * igt@fbdev@read:
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#2134])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@fbdev@read.html

  * igt@kms_async_flips@crc@pipe-a-hdmi-a-3:
    - shard-bmg:          [PASS][23] -> [FAIL][24] ([Intel XE#3557])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-5/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#3279])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#1407])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-8/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - shard-dg2-set2:     [PASS][27] -> [SKIP][28] ([Intel XE#2136]) +35 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2327]) +3 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-bmg:          [PASS][30] -> [DMESG-FAIL][31] ([Intel XE#2705] / [Intel XE#3468]) +1 other test dmesg-fail
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#1124]) +6 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#1124]) +4 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#2191]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-3/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-3-displays-2560x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][36] ([Intel XE#367])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#367]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][38] ([Intel XE#1727])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#2887]) +8 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-3/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2887]) +11 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2652] / [Intel XE#787]) +8 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#3433]) +3 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#787]) +48 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][44] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][45] ([Intel XE#1727])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [PASS][46] -> [INCOMPLETE][47] ([Intel XE#1727])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [PASS][48] -> [DMESG-WARN][49] ([Intel XE#1727] / [Intel XE#3113])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][50] ([Intel XE#1727] / [Intel XE#3113])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#1152]) +3 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#373]) +8 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-3/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2325])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#2252]) +4 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#3278])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-5/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#307])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-5/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@legacy@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][57] ([Intel XE#1178])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_content_protection@legacy@pipe-a-dp-4.html

  * igt@kms_content_protection@lic-type-0:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#2341])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_content_protection@lic-type-0.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#2320]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#2321])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-6/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#1424]) +2 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-1/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#2321])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#2291])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#309]) +2 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][65] -> [DMESG-WARN][66] ([Intel XE#877])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][67] -> [SKIP][68] ([Intel XE#2291]) +4 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@torture-move@pipe-d:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][69] ([Intel XE#3184])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_cursor_legacy@torture-move@pipe-d.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#1508])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#1340])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([i915#3804])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#3070])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-1/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#2244]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#2244])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_feature_discovery@display-4x:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#1138])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-dg2-set2:     [PASS][77] -> [SKIP][78] ([Intel XE#2423] / [i915#2575]) +106 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@kms_flip@2x-dpms-vs-vblank-race.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][79] -> [FAIL][80] ([Intel XE#3486])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][81] -> [FAIL][82] ([Intel XE#301])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-hdmi-a6-dp4.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3:
    - shard-bmg:          [PASS][83] -> [FAIL][84] ([Intel XE#2882]) +1 other test fail
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3:
    - shard-bmg:          [PASS][85] -> [FAIL][86] ([Intel XE#3321] / [Intel XE#3487])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#2316])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-flip-vs-panning-interruptible@cd-dp2-hdmi-a3:
    - shard-bmg:          [PASS][88] -> [DMESG-WARN][89] ([Intel XE#3468]) +136 other tests dmesg-warn
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-7/igt@kms_flip@2x-flip-vs-panning-interruptible@cd-dp2-hdmi-a3.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_flip@2x-flip-vs-panning-interruptible@cd-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-rmfb:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#1421]) +3 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-4/igt@kms_flip@2x-flip-vs-rmfb.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [PASS][91] -> [SKIP][92] ([Intel XE#2316]) +4 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@blocking-wf_vblank:
    - shard-lnl:          [PASS][93] -> [FAIL][94] ([Intel XE#886]) +2 other tests fail
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-5/igt@kms_flip@blocking-wf_vblank.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-6/igt@kms_flip@blocking-wf_vblank.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@a-dp2:
    - shard-bmg:          [PASS][95] -> [DMESG-FAIL][96] ([Intel XE#3468]) +23 other tests dmesg-fail
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-7/igt@kms_flip@flip-vs-absolute-wf_vblank@a-dp2.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_flip@flip-vs-absolute-wf_vblank@a-dp2.html

  * igt@kms_flip@flip-vs-suspend@a-dp4:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][97] ([Intel XE#1727] / [Intel XE#3468])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@kms_flip@flip-vs-suspend@a-dp4.html

  * igt@kms_flip@flip-vs-suspend@a-hdmi-a6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][98] ([Intel XE#3468]) +1 other test dmesg-warn
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@kms_flip@flip-vs-suspend@a-hdmi-a6.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-FAIL][99] ([Intel XE#3468]) +1 other test dmesg-fail
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@kms_flip@flip-vs-suspend@b-hdmi-a6.html

  * igt@kms_flip@flip-vs-suspend@c-dp2:
    - shard-bmg:          [PASS][100] -> [DMESG-FAIL][101] ([Intel XE#1727] / [Intel XE#3468]) +9 other tests dmesg-fail
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-2/igt@kms_flip@flip-vs-suspend@c-dp2.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@kms_flip@flip-vs-suspend@c-dp2.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][102] ([Intel XE#1397] / [Intel XE#1745])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#1397])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][104] ([Intel XE#2380]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][105] ([Intel XE#2293] / [Intel XE#2380]) +2 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][106] ([Intel XE#455]) +7 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#1401] / [Intel XE#1745]) +2 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][108] ([Intel XE#1401]) +2 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][109] ([Intel XE#2293]) +2 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][110] ([Intel XE#651]) +8 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][111] ([Intel XE#2311]) +15 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][112] ([Intel XE#651]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [FAIL][113] ([Intel XE#2333]) +6 other tests fail
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     [PASS][114] -> [SKIP][115] ([Intel XE#2136] / [Intel XE#2351]) +8 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][116] ([Intel XE#2312]) +6 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][117] ([Intel XE#656]) +21 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][118] ([Intel XE#2352])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][119] ([Intel XE#2313]) +14 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][120] ([Intel XE#653]) +2 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][121] ([Intel XE#1503])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-7/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][122] -> [DMESG-WARN][123] ([Intel XE#3468]) +2 other tests dmesg-warn
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-bmg:          [PASS][124] -> [SKIP][125] ([Intel XE#3012])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-8/igt@kms_joiner@basic-force-big-joiner.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_lease@lease-invalid-crtc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][126] ([Intel XE#2423] / [i915#2575]) +33 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_lease@lease-invalid-crtc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][127] -> [INCOMPLETE][128] ([Intel XE#1727] / [Intel XE#3468]) +1 other test incomplete
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-6.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-6.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-bmg:          [PASS][129] -> [INCOMPLETE][130] ([Intel XE#1727] / [Intel XE#3468]) +6 other tests incomplete
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-8/igt@kms_plane@plane-panning-bottom-right-suspend.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b:
    - shard-dg2-set2:     NOTRUN -> [SKIP][131] ([Intel XE#2763]) +5 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][132] ([Intel XE#3468]) +21 other tests dmesg-warn
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a:
    - shard-lnl:          NOTRUN -> [SKIP][133] ([Intel XE#2763]) +11 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d:
    - shard-bmg:          NOTRUN -> [SKIP][134] ([Intel XE#2763]) +9 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][135] ([Intel XE#2763] / [Intel XE#455]) +2 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - shard-dg2-set2:     NOTRUN -> [SKIP][136] ([Intel XE#2446])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_pm_rpm@basic-pci-d3-state.html

  * igt@kms_pm_rpm@cursor-dpms:
    - shard-dg2-set2:     [PASS][137] -> [SKIP][138] ([Intel XE#2446]) +2 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@kms_pm_rpm@cursor-dpms.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_pm_rpm@cursor-dpms.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][139] ([Intel XE#1439] / [Intel XE#3141])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-1/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@universal-planes:
    - shard-bmg:          [PASS][140] -> [INCOMPLETE][141] ([Intel XE#1727] / [Intel XE#2864] / [Intel XE#3468])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-5/igt@kms_pm_rpm@universal-planes.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@kms_pm_rpm@universal-planes.html

  * igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][142] ([Intel XE#2893]) +2 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-7/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][143] ([Intel XE#1489]) +2 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-dg2-set2:     NOTRUN -> [SKIP][144] ([Intel XE#1122])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-bmg:          NOTRUN -> [SKIP][145] ([Intel XE#2387])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_psr2_su@page_flip-p010.html
    - shard-lnl:          NOTRUN -> [SKIP][146] ([Intel XE#1128])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-4/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr-primary-page-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][147] ([Intel XE#2850] / [Intel XE#929])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@kms_psr@fbc-psr-primary-page-flip.html

  * igt@kms_psr@fbc-psr-sprite-plane-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][148] ([Intel XE#2136] / [Intel XE#2351]) +18 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_psr@fbc-psr-sprite-plane-onoff.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][149] ([Intel XE#2136]) +30 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html

  * igt@kms_psr@pr-cursor-plane-move:
    - shard-lnl:          NOTRUN -> [SKIP][150] ([Intel XE#1406]) +4 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-4/igt@kms_psr@pr-cursor-plane-move.html

  * igt@kms_psr@psr-cursor-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][151] ([Intel XE#2234] / [Intel XE#2850]) +10 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_psr@psr-cursor-plane-onoff.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-lnl:          NOTRUN -> [SKIP][152] ([Intel XE#3414]) +1 other test skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-3/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][153] ([Intel XE#3414])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
    - shard-bmg:          NOTRUN -> [SKIP][154] ([Intel XE#3414])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-bmg:          NOTRUN -> [SKIP][155] ([Intel XE#2330])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_setmode@basic:
    - shard-bmg:          NOTRUN -> [DMESG-FAIL][156] ([Intel XE#3468]) +6 other tests dmesg-fail
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_setmode@basic.html

  * igt@kms_setmode@basic@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [FAIL][157] ([Intel XE#3559]) +4 other tests fail
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_setmode@basic@pipe-a-hdmi-a-3.html

  * igt@kms_vblank@ts-continuation-dpms-rpm@pipe-d-hdmi-a-3:
    - shard-bmg:          [PASS][158] -> [DMESG-WARN][159] ([Intel XE#1727] / [Intel XE#3468]) +12 other tests dmesg-warn
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-4/igt@kms_vblank@ts-continuation-dpms-rpm@pipe-d-hdmi-a-3.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_vblank@ts-continuation-dpms-rpm@pipe-d-hdmi-a-3.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][160] -> [FAIL][161] ([Intel XE#2159]) +1 other test fail
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-1/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@kms_vrr@flip-basic:
    - shard-bmg:          NOTRUN -> [SKIP][162] ([Intel XE#1499])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_vrr@flip-basic.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-lnl:          NOTRUN -> [SKIP][163] ([Intel XE#756]) +2 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-7/igt@kms_writeback@writeback-fb-id.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-bmg:          NOTRUN -> [SKIP][164] ([Intel XE#756])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_writeback@writeback-pixel-formats.html

  * igt@testdisplay:
    - shard-dg2-set2:     [PASS][165] -> [SKIP][166] ([Intel XE#2423]) +2 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@testdisplay.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@testdisplay.html

  * igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-vram01-vram01:
    - shard-dg2-set2:     NOTRUN -> [DMESG-FAIL][167] ([Intel XE#1727] / [Intel XE#3468]) +10 other tests dmesg-fail
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-vram01-vram01.html

  * igt@xe_copy_basic@mem-copy-linear-0xfd:
    - shard-dg2-set2:     NOTRUN -> [SKIP][168] ([Intel XE#1123])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@xe_copy_basic@mem-copy-linear-0xfd.html

  * igt@xe_eudebug@basic-close:
    - shard-lnl:          NOTRUN -> [SKIP][169] ([Intel XE#2905]) +5 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-7/igt@xe_eudebug@basic-close.html

  * igt@xe_eudebug@basic-vm-bind-metadata-discovery:
    - shard-bmg:          NOTRUN -> [SKIP][170] ([Intel XE#2905]) +6 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html

  * igt@xe_eudebug_online@resume-one:
    - shard-dg2-set2:     NOTRUN -> [SKIP][171] ([Intel XE#2905])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@xe_eudebug_online@resume-one.html

  * igt@xe_evict@evict-beng-mixed-many-threads-large:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][172] ([Intel XE#1473])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-large.html
    - shard-bmg:          NOTRUN -> [TIMEOUT][173] ([Intel XE#1473])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@xe_evict@evict-beng-mixed-many-threads-large.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [PASS][174] -> [INCOMPLETE][175] ([Intel XE#1473] / [Intel XE#3468])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-8/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-reopen:
    - shard-lnl:          NOTRUN -> [SKIP][176] ([Intel XE#688]) +5 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-6/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-reopen.html

  * igt@xe_exec_balancer@once-parallel-rebind:
    - shard-dg2-set2:     NOTRUN -> [SKIP][177] ([Intel XE#1130]) +73 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@xe_exec_balancer@once-parallel-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][178] ([Intel XE#2322]) +8 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html

  * igt@xe_exec_basic@multigpu-once-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][179] ([Intel XE#1392]) +4 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-2/igt@xe_exec_basic@multigpu-once-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][180] ([Intel XE#288])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-imm.html

  * igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-prefetch:
    - shard-bmg:          [PASS][181] -> [DMESG-WARN][182] ([Intel XE#1727]) +2 other tests dmesg-warn
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-8/igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-prefetch.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-prefetch.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_pm_init_early:
    - shard-bmg:          [PASS][183] -> [DMESG-WARN][184] ([Intel XE#3467] / [Intel XE#3468])
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-5/igt@xe_fault_injection@inject-fault-probe-function-xe_pm_init_early.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@xe_fault_injection@inject-fault-probe-function-xe_pm_init_early.html

  * igt@xe_fault_injection@vm-create-fail-xe_vm_create_scratch:
    - shard-bmg:          [PASS][185] -> [DMESG-WARN][186] ([Intel XE#3467])
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-8/igt@xe_fault_injection@vm-create-fail-xe_vm_create_scratch.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@xe_fault_injection@vm-create-fail-xe_vm_create_scratch.html

  * igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit:
    - shard-lnl:          NOTRUN -> [SKIP][187] ([Intel XE#2229]) +1 other test skip
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-5/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html

  * igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit:
    - shard-dg2-set2:     NOTRUN -> [FAIL][188] ([Intel XE#1999]) +1 other test fail
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html

  * igt@xe_module_load@force-load:
    - shard-bmg:          NOTRUN -> [SKIP][189] ([Intel XE#2457])
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@xe_module_load@force-load.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][190] ([Intel XE#378])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@xe_module_load@force-load.html

  * igt@xe_oa@invalid-remove-userspace-config:
    - shard-dg2-set2:     NOTRUN -> [SKIP][191] ([Intel XE#2541])
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@xe_oa@invalid-remove-userspace-config.html

  * igt@xe_oa@oa-regs-whitelisted@rcs-0:
    - shard-bmg:          [PASS][192] -> [FAIL][193] ([Intel XE#2514]) +1 other test fail
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-1/igt@xe_oa@oa-regs-whitelisted@rcs-0.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@xe_oa@oa-regs-whitelisted@rcs-0.html

  * igt@xe_oa@oa-tlb-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][194] ([Intel XE#2248])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@xe_oa@oa-tlb-invalidate.html

  * igt@xe_pm@d3cold-mmap-system:
    - shard-lnl:          NOTRUN -> [SKIP][195] ([Intel XE#2284] / [Intel XE#366])
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-7/igt@xe_pm@d3cold-mmap-system.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-bmg:          NOTRUN -> [SKIP][196] ([Intel XE#2284])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@d3hot-mocs:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][197] ([Intel XE#1727] / [Intel XE#3468])
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@xe_pm@d3hot-mocs.html

  * igt@xe_pm@s2idle-mocs:
    - shard-dg2-set2:     [PASS][198] -> [DMESG-WARN][199] ([Intel XE#1727] / [Intel XE#3468])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@xe_pm@s2idle-mocs.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@xe_pm@s2idle-mocs.html

  * igt@xe_pm@s2idle-multiple-execs:
    - shard-bmg:          [PASS][200] -> [DMESG-WARN][201] ([Intel XE#1616] / [Intel XE#1727] / [Intel XE#3468])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-7/igt@xe_pm@s2idle-multiple-execs.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@xe_pm@s2idle-multiple-execs.html

  * igt@xe_pm@s2idle-vm-bind-unbind-all:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][202] ([Intel XE#1616] / [Intel XE#1727] / [Intel XE#3468])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@xe_pm@s2idle-vm-bind-unbind-all.html

  * igt@xe_pm@s3-vm-bind-userptr:
    - shard-bmg:          [PASS][203] -> [DMESG-WARN][204] ([Intel XE#1727] / [Intel XE#3468] / [Intel XE#569])
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-4/igt@xe_pm@s3-vm-bind-userptr.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@xe_pm@s3-vm-bind-userptr.html

  * igt@xe_pm@s4-multiple-execs:
    - shard-lnl:          [PASS][205] -> [ABORT][206] ([Intel XE#1358] / [Intel XE#1607] / [Intel XE#1794])
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-4/igt@xe_pm@s4-multiple-execs.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-2/igt@xe_pm@s4-multiple-execs.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-bmg:          [PASS][207] -> [DMESG-WARN][208] ([Intel XE#2280] / [Intel XE#3468])
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-4/igt@xe_pm@s4-vm-bind-unbind-all.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_pm_residency@cpg-basic:
    - shard-lnl:          NOTRUN -> [SKIP][209] ([Intel XE#584])
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-4/igt@xe_pm_residency@cpg-basic.html

  * igt@xe_pm_residency@gt-c6-freeze:
    - shard-lnl:          [PASS][210] -> [DMESG-WARN][211] ([Intel XE#3088]) +1 other test dmesg-warn
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-8/igt@xe_pm_residency@gt-c6-freeze.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-5/igt@xe_pm_residency@gt-c6-freeze.html

  * igt@xe_pm_residency@toggle-gt-c6:
    - shard-lnl:          [PASS][212] -> [FAIL][213] ([Intel XE#958])
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-6/igt@xe_pm_residency@toggle-gt-c6.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-2/igt@xe_pm_residency@toggle-gt-c6.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-bmg:          NOTRUN -> [SKIP][214] ([Intel XE#944]) +3 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-lnl:          NOTRUN -> [SKIP][215] ([Intel XE#3342])
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-8/igt@xe_sriov_flr@flr-each-isolation.html

  * igt@xe_vm@large-split-binds-536870912:
    - shard-dg2-set2:     [PASS][216] -> [SKIP][217] ([Intel XE#1130]) +168 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@xe_vm@large-split-binds-536870912.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@xe_vm@large-split-binds-536870912.html

  * igt@xe_wedged@basic-wedged:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][218] ([Intel XE#2919])
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@xe_wedged@basic-wedged.html

  
#### Possible fixes ####

  * igt@core_getstats:
    - shard-dg2-set2:     [SKIP][219] ([Intel XE#2423]) -> [PASS][220]
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@core_getstats.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@core_getstats.html

  * igt@core_hotunplug@hotreplug:
    - shard-bmg:          [DMESG-WARN][221] ([Intel XE#3521]) -> [PASS][222]
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-4/igt@core_hotunplug@hotreplug.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@core_hotunplug@hotreplug.html
    - shard-dg2-set2:     [SKIP][223] ([Intel XE#1885]) -> [PASS][224] +1 other test pass
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@core_hotunplug@hotreplug.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@core_hotunplug@hotreplug.html

  * igt@core_hotunplug@hotunplug-rescan:
    - shard-lnl:          [ABORT][225] -> [PASS][226] +2 other tests pass
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-4/igt@core_hotunplug@hotunplug-rescan.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-8/igt@core_hotunplug@hotunplug-rescan.html

  * igt@fbdev@eof:
    - shard-dg2-set2:     [SKIP][227] ([Intel XE#2134]) -> [PASS][228] +2 other tests pass
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@fbdev@eof.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@fbdev@eof.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-bmg:          [INCOMPLETE][229] ([Intel XE#2613]) -> [PASS][230]
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-bmg:          [DMESG-FAIL][231] ([Intel XE#3468]) -> [PASS][232] +24 other tests pass
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@linear-8bpp-rotate-180:
    - shard-lnl:          [INCOMPLETE][233] ([Intel XE#3466]) -> [PASS][234] +1 other test pass
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-7/igt@kms_big_fb@linear-8bpp-rotate-180.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-2/igt@kms_big_fb@linear-8bpp-rotate-180.html

  * igt@kms_dirtyfb@default-dirtyfb-ioctl@a-dp-2:
    - shard-bmg:          [DMESG-WARN][235] -> [PASS][236] +1 other test pass
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-5/igt@kms_dirtyfb@default-dirtyfb-ioctl@a-dp-2.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_dirtyfb@default-dirtyfb-ioctl@a-dp-2.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-bmg:          [INCOMPLETE][237] ([Intel XE#2597]) -> [PASS][238]
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-6/igt@kms_flip@2x-flip-vs-suspend.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp2:
    - shard-bmg:          [DMESG-WARN][239] ([Intel XE#3468]) -> [PASS][240] +127 other tests pass
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp2.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp2.html

  * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a6:
    - shard-dg2-set2:     [DMESG-FAIL][241] ([Intel XE#1727]) -> [PASS][242]
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a6.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a6.html

  * igt@kms_flip@flip-vs-panning-interruptible:
    - shard-bmg:          [DMESG-WARN][243] ([Intel XE#2705] / [Intel XE#3468]) -> [PASS][244]
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-6/igt@kms_flip@flip-vs-panning-interruptible.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@kms_flip@flip-vs-panning-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-2p-rte:
    - shard-dg2-set2:     [INCOMPLETE][245] ([Intel XE#1195] / [Intel XE#3468]) -> [PASS][246]
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-2p-rte.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][247] ([Intel XE#2136] / [Intel XE#2351]) -> [PASS][248] +3 other tests pass
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][249] ([Intel XE#2136]) -> [PASS][250] +14 other tests pass
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][251] ([Intel XE#1503]) -> [PASS][252]
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane_cursor@primary:
    - shard-lnl:          [DMESG-WARN][253] ([Intel XE#3466]) -> [PASS][254] +44 other tests pass
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-7/igt@kms_plane_cursor@primary.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-3/igt@kms_plane_cursor@primary.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format:
    - shard-bmg:          [DMESG-WARN][255] ([Intel XE#2566]) -> [PASS][256] +1 other test pass
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-2/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-lnl:          [FAIL][257] ([Intel XE#1430]) -> [PASS][258]
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-5/igt@kms_pm_dc@dc6-dpms.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-3/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_rpm@drm-resources-equal:
    - shard-dg2-set2:     [SKIP][259] ([Intel XE#2446]) -> [PASS][260]
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_pm_rpm@drm-resources-equal.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_pm_rpm@drm-resources-equal.html

  * igt@kms_pm_rpm@modeset-stress-extra-wait:
    - shard-bmg:          [INCOMPLETE][261] ([Intel XE#2864]) -> [PASS][262]
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-7/igt@kms_pm_rpm@modeset-stress-extra-wait.html
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_pm_rpm@modeset-stress-extra-wait.html
    - shard-dg2-set2:     [ABORT][263] ([Intel XE#3468]) -> [PASS][264]
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_pm_rpm@modeset-stress-extra-wait.html
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_pm_rpm@modeset-stress-extra-wait.html

  * igt@kms_psr@psr2-sprite-render:
    - shard-lnl:          [FAIL][265] ([Intel XE#3536]) -> [PASS][266] +1 other test pass
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-5/igt@kms_psr@psr2-sprite-render.html
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-6/igt@kms_psr@psr2-sprite-render.html

  * igt@kms_rotation_crc@sprite-rotation-180:
    - shard-dg2-set2:     [SKIP][267] ([Intel XE#2423] / [i915#2575]) -> [PASS][268] +51 other tests pass
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_rotation_crc@sprite-rotation-180.html
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@kms_rotation_crc@sprite-rotation-180.html

  * igt@kms_setmode@basic@pipe-b-edp-1:
    - shard-lnl:          [FAIL][269] ([Intel XE#2883]) -> [PASS][270] +2 other tests pass
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-2/igt@kms_setmode@basic@pipe-b-edp-1.html
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-2/igt@kms_setmode@basic@pipe-b-edp-1.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1:
    - shard-lnl:          [FAIL][271] ([Intel XE#899]) -> [PASS][272]
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-6/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-8/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html

  * igt@kms_vblank@query-busy:
    - shard-bmg:          [INCOMPLETE][273] ([Intel XE#1727]) -> [PASS][274] +3 other tests pass
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-1/igt@kms_vblank@query-busy.html
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_vblank@query-busy.html

  * igt@kms_vrr@negative-basic:
    - shard-bmg:          [INCOMPLETE][275] -> [PASS][276] +2 other tests pass
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-8/igt@kms_vrr@negative-basic.html
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_vrr@negative-basic.html

  * igt@xe_exec_basic@once-rebind:
    - shard-dg2-set2:     [SKIP][277] ([Intel XE#1130]) -> [PASS][278] +79 other tests pass
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_exec_basic@once-rebind.html
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@xe_exec_basic@once-rebind.html

  * igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate:
    - shard-lnl:          [DMESG-WARN][279] ([Intel XE#3371]) -> [PASS][280]
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-5/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate.html
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-5/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate.html

  * igt@xe_live_ktest@xe_bo:
    - shard-lnl:          [DMESG-FAIL][281] ([Intel XE#3466]) -> [PASS][282] +9 other tests pass
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-7/igt@xe_live_ktest@xe_bo.html
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-5/igt@xe_live_ktest@xe_bo.html

  * igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit:
    - shard-bmg:          [INCOMPLETE][283] ([Intel XE#2998]) -> [PASS][284] +1 other test pass
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-7/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html

  * igt@xe_live_ktest@xe_mocs:
    - shard-bmg:          [SKIP][285] ([Intel XE#1192]) -> [PASS][286]
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-5/igt@xe_live_ktest@xe_mocs.html
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@xe_live_ktest@xe_mocs.html

  * igt@xe_module_load@reload-no-display:
    - shard-bmg:          [DMESG-WARN][287] ([Intel XE#3467]) -> [PASS][288] +1 other test pass
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-1/igt@xe_module_load@reload-no-display.html
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@xe_module_load@reload-no-display.html

  * igt@xe_pm@s3-multiple-execs:
    - shard-bmg:          [DMESG-WARN][289] ([Intel XE#569]) -> [PASS][290]
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-6/igt@xe_pm@s3-multiple-execs.html
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@xe_pm@s3-multiple-execs.html

  * igt@xe_pm@s4-basic-exec:
    - shard-lnl:          [ABORT][291] ([Intel XE#1358] / [Intel XE#1607] / [Intel XE#1794]) -> [PASS][292]
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-2/igt@xe_pm@s4-basic-exec.html
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-7/igt@xe_pm@s4-basic-exec.html

  * igt@xe_pm_residency@gt-c6-freeze@gt1:
    - shard-bmg:          [DMESG-FAIL][293] ([Intel XE#1727]) -> [PASS][294] +1 other test pass
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-7/igt@xe_pm_residency@gt-c6-freeze@gt1.html
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@xe_pm_residency@gt-c6-freeze@gt1.html

  * igt@xe_vm@munmap-style-unbind-either-side-partial-split-page-hammer:
    - shard-bmg:          [DMESG-WARN][295] ([Intel XE#1727]) -> [PASS][296] +9 other tests pass
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-6/igt@xe_vm@munmap-style-unbind-either-side-partial-split-page-hammer.html
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@xe_vm@munmap-style-unbind-either-side-partial-split-page-hammer.html

  * igt@xe_vm@unbind-all-2-vmas:
    - shard-dg2-set2:     [DMESG-WARN][297] ([Intel XE#1727]) -> [PASS][298]
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@xe_vm@unbind-all-2-vmas.html
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@xe_vm@unbind-all-2-vmas.html

  
#### Warnings ####

  * igt@core_hotunplug@hotunbind-rebind:
    - shard-dg2-set2:     [DMESG-WARN][299] ([Intel XE#3521]) -> [SKIP][300] ([Intel XE#1885])
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@core_hotunplug@hotunbind-rebind.html
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@core_hotunplug@hotunbind-rebind.html

  * igt@kms_async_flips@invalid-async-flip:
    - shard-dg2-set2:     [SKIP][301] ([Intel XE#2423] / [i915#2575]) -> [SKIP][302] ([Intel XE#873])
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_async_flips@invalid-async-flip.html
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_async_flips@invalid-async-flip.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][303] ([Intel XE#316]) -> [SKIP][304] ([Intel XE#2136] / [Intel XE#2351])
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][305] ([Intel XE#2136]) -> [SKIP][306] ([Intel XE#316]) +3 other tests skip
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][307] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][308] ([Intel XE#316])
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_big_fb@linear-16bpp-rotate-90.html
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][309] ([Intel XE#316]) -> [SKIP][310] ([Intel XE#2136]) +1 other test skip
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][311] ([Intel XE#2136]) -> [SKIP][312] ([Intel XE#1124]) +7 other tests skip
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-dg2-set2:     [SKIP][313] ([Intel XE#1124]) -> [SKIP][314] ([Intel XE#2136]) +11 other tests skip
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2-set2:     [SKIP][315] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][316] ([Intel XE#619])
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_big_fb@yf-tiled-addfb.html
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-dg2-set2:     [SKIP][317] ([Intel XE#2136]) -> [SKIP][318] ([Intel XE#607])
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-dg2-set2:     [SKIP][319] ([Intel XE#1124]) -> [SKIP][320] ([Intel XE#2136] / [Intel XE#2351]) +3 other tests skip
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_bw@connected-linear-tiling-1-displays-2160x1440p:
    - shard-dg2-set2:     [SKIP][321] ([Intel XE#2423] / [i915#2575]) -> [SKIP][322] ([Intel XE#367]) +2 other tests skip
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_bw@connected-linear-tiling-1-displays-2160x1440p.html
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_bw@connected-linear-tiling-1-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
    - shard-dg2-set2:     [SKIP][323] ([Intel XE#2191]) -> [SKIP][324] ([Intel XE#2423] / [i915#2575])
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-dg2-set2:     [SKIP][325] ([Intel XE#367]) -> [SKIP][326] ([Intel XE#2423] / [i915#2575]) +3 other tests skip
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [SKIP][327] ([Intel XE#2136] / [Intel XE#2351]) -> [DMESG-WARN][328] ([Intel XE#1727])
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs:
    - shard-dg2-set2:     [SKIP][329] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][330] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs.html
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs:
    - shard-dg2-set2:     [SKIP][331] ([Intel XE#2136]) -> [SKIP][332] ([Intel XE#455] / [Intel XE#787]) +3 other tests skip
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs.html
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs:
    - shard-dg2-set2:     [SKIP][333] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][334] ([Intel XE#2136]) +11 other tests skip
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-dg2-set2:     [SKIP][335] ([Intel XE#3442]) -> [SKIP][336] ([Intel XE#2136])
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [FAIL][337] ([Intel XE#616]) -> [SKIP][338] ([Intel XE#2136])
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-dg2-set2:     [SKIP][339] ([Intel XE#2907]) -> [SKIP][340] ([Intel XE#2136]) +1 other test skip
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
   [340]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs:
    - shard-dg2-set2:     [SKIP][341] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][342] ([Intel XE#2136] / [Intel XE#2351]) +4 other tests skip
   [341]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs.html
   [342]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
    - shard-dg2-set2:     [SKIP][343] ([Intel XE#2136]) -> [SKIP][344] ([Intel XE#2907]) +1 other test skip
   [343]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
   [344]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html

  * igt@kms_chamelium_color@ctm-limited-range:
    - shard-dg2-set2:     [SKIP][345] ([Intel XE#306]) -> [SKIP][346] ([Intel XE#2423] / [i915#2575]) +2 other tests skip
   [345]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_chamelium_color@ctm-limited-range.html
   [346]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_chamelium_color@ctm-limited-range.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate:
    - shard-dg2-set2:     [SKIP][347] ([Intel XE#2423] / [i915#2575]) -> [SKIP][348] ([Intel XE#373]) +4 other tests skip
   [347]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate.html
   [348]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate.html

  * igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
    - shard-dg2-set2:     [SKIP][349] ([Intel XE#373]) -> [SKIP][350] ([Intel XE#2423] / [i915#2575]) +12 other tests skip
   [349]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html
   [350]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [FAIL][351] ([Intel XE#1178]) -> [SKIP][352] ([Intel XE#2341])
   [351]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-5/igt@kms_content_protection@atomic.html
   [352]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@legacy:
    - shard-dg2-set2:     [SKIP][353] ([Intel XE#2423] / [i915#2575]) -> [FAIL][354] ([Intel XE#1178])
   [353]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_content_protection@legacy.html
   [354]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg2-set2:     [SKIP][355] ([Intel XE#455]) -> [INCOMPLETE][356] ([Intel XE#1727])
   [355]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_content_protection@mei-interface.html
   [356]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [FAIL][357] ([Intel XE#1178]) -> [INCOMPLETE][358] ([Intel XE#2715] / [Intel XE#3468]) +3 other tests incomplete
   [357]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-6/igt@kms_content_protection@srm.html
   [358]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-dg2-set2:     [SKIP][359] ([Intel XE#2423] / [i915#2575]) -> [SKIP][360] ([Intel XE#308]) +1 other test skip
   [359]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_cursor_crc@cursor-offscreen-512x170.html
   [360]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-dg2-set2:     [SKIP][361] ([Intel XE#308]) -> [SKIP][362] ([Intel XE#2423] / [i915#2575]) +1 other test skip
   [361]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_cursor_crc@cursor-onscreen-512x170.html
   [362]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-dg2-set2:     [SKIP][363] ([Intel XE#2423] / [i915#2575]) -> [SKIP][364] ([Intel XE#455]) +5 other tests skip
   [363]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_cursor_crc@cursor-sliding-max-size.html
   [364]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     [SKIP][365] ([Intel XE#323]) -> [SKIP][366] ([Intel XE#2423] / [i915#2575])
   [365]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
   [366]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@torture-move:
    - shard-dg2-set2:     [SKIP][367] ([Intel XE#2423] / [i915#2575]) -> [DMESG-WARN][368] ([Intel XE#3184])
   [367]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_cursor_legacy@torture-move.html
   [368]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_cursor_legacy@torture-move.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - shard-bmg:          [FAIL][369] ([Intel XE#2141]) -> [DMESG-FAIL][370] ([Intel XE#3468]) +2 other tests dmesg-fail
   [369]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-5/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html
   [370]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-dg2-set2:     [SKIP][371] ([Intel XE#2423] / [i915#2575]) -> [SKIP][372] ([Intel XE#307]) +1 other test skip
   [371]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_display_modes@mst-extended-mode-negative.html
   [372]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-bmg:          [DMESG-FAIL][373] ([Intel XE#3468]) -> [FAIL][374] ([Intel XE#1695])
   [373]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-1/igt@kms_fbcon_fbt@fbc-suspend.html
   [374]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-dg2-set2:     [SKIP][375] ([Intel XE#776]) -> [SKIP][376] ([Intel XE#2136]) +1 other test skip
   [375]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@kms_fbcon_fbt@psr-suspend.html
   [376]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2-set2:     [SKIP][377] ([Intel XE#2423] / [i915#2575]) -> [SKIP][378] ([Intel XE#701])
   [377]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_feature_discovery@chamelium.html
   [378]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@psr2:
    - shard-dg2-set2:     [SKIP][379] ([Intel XE#1135]) -> [SKIP][380] ([Intel XE#2423] / [i915#2575])
   [379]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_feature_discovery@psr2.html
   [380]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-dg2-set2:     [FAIL][381] ([Intel XE#301]) -> [SKIP][382] ([Intel XE#2423] / [i915#2575])
   [381]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [382]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-bmg:          [FAIL][383] ([Intel XE#2882]) -> [DMESG-WARN][384] ([Intel XE#3468])
   [383]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [384]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][385] ([Intel XE#3321] / [Intel XE#3486]) -> [DMESG-WARN][386] ([Intel XE#3468])
   [385]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-dp2-hdmi-a3.html
   [386]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ad-dp2-hdmi-a3.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-bmg:          [DMESG-WARN][387] ([Intel XE#3468]) -> [FAIL][388] ([Intel XE#2882])
   [387]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-5/igt@kms_flip@flip-vs-expired-vblank.html
   [388]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_flip@flip-vs-expired-vblank.html
    - shard-dg2-set2:     [DMESG-FAIL][389] ([Intel XE#1727]) -> [FAIL][390] ([Intel XE#301])
   [389]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank.html
   [390]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank@a-dp4:
    - shard-dg2-set2:     [FAIL][391] ([Intel XE#3487]) -> [FAIL][392] ([Intel XE#3321] / [Intel XE#3487])
   [391]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html
   [392]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html

  * igt@kms_flip@flip-vs-expired-vblank@c-dp4:
    - shard-dg2-set2:     [FAIL][393] ([Intel XE#301] / [Intel XE#3487]) -> [FAIL][394] ([Intel XE#301] / [Intel XE#3321] / [Intel XE#3487]) +1 other test fail
   [393]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
   [394]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-dg2-set2:     [SKIP][395] ([Intel XE#2423] / [i915#2575]) -> [DMESG-FAIL][396] ([Intel XE#1727] / [Intel XE#3468])
   [395]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_flip@flip-vs-suspend.html
   [396]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling:
    - shard-dg2-set2:     [INCOMPLETE][397] ([Intel XE#1195] / [Intel XE#1727]) -> [SKIP][398] ([Intel XE#2136])
   [397]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling.html
   [398]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-dg2-set2:     [SKIP][399] ([Intel XE#2136]) -> [SKIP][400] ([Intel XE#455])
   [399]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
   [400]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2-set2:     [SKIP][401] ([Intel XE#455]) -> [SKIP][402] ([Intel XE#2136] / [Intel XE#2351])
   [401]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [402]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-dg2-set2:     [SKIP][403] ([Intel XE#455]) -> [SKIP][404] ([Intel XE#2136]) +3 other tests skip
   [403]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
   [404]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2-set2:     [SKIP][405] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][406] ([Intel XE#455]) +3 other tests skip
   [405]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
   [406]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - shard-dg2-set2:     [SKIP][407] ([i915#5274]) -> [SKIP][408] ([Intel XE#2423] / [i915#2575])
   [407]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@kms_force_connector_basic@prune-stale-modes.html
   [408]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
    - shard-bmg:          [SKIP][409] ([Intel XE#2311]) -> [SKIP][410] ([Intel XE#2312]) +12 other tests skip
   [409]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html
   [410]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     [SKIP][411] ([Intel XE#2136]) -> [SKIP][412] ([Intel XE#651]) +13 other tests skip
   [411]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html
   [412]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-dg2-set2:     [INCOMPLETE][413] ([Intel XE#1195]) -> [INCOMPLETE][414] ([Intel XE#1727] / [Intel XE#3468])
   [413]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
   [414]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [DMESG-FAIL][415] ([Intel XE#3468]) -> [SKIP][416] ([Intel XE#2312]) +1 other test skip
   [415]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [416]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [FAIL][417] ([Intel XE#2333]) -> [DMESG-FAIL][418] ([Intel XE#3468]) +15 other tests dmesg-fail
   [417]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [418]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          [FAIL][419] ([Intel XE#2333]) -> [SKIP][420] ([Intel XE#2312]) +7 other tests skip
   [419]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
   [420]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-blt:
    - shard-dg2-set2:     [SKIP][421] ([Intel XE#2136]) -> [INCOMPLETE][422] ([Intel XE#1727])
   [421]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-blt.html
   [422]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-linear:
    - shard-bmg:          [DMESG-FAIL][423] ([Intel XE#3468]) -> [FAIL][424] ([Intel XE#2333]) +8 other tests fail
   [423]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
   [424]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2-set2:     [SKIP][425] ([Intel XE#658]) -> [SKIP][426] ([Intel XE#2136] / [Intel XE#2351])
   [425]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
   [426]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
    - shard-dg2-set2:     [SKIP][427] ([Intel XE#651]) -> [SKIP][428] ([Intel XE#2136]) +25 other tests skip
   [427]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
   [428]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     [SKIP][429] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][430] ([Intel XE#651]) +6 other tests skip
   [429]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render.html
   [430]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][431] ([Intel XE#651]) -> [SKIP][432] ([Intel XE#2136] / [Intel XE#2351]) +12 other tests skip
   [431]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt.html
   [432]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2-set2:     [SKIP][433] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][434] ([Intel XE#653]) +3 other tests skip
   [433]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html
   [434]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][435] ([Intel XE#2313]) -> [SKIP][436] ([Intel XE#2312]) +16 other tests skip
   [435]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
   [436]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][437] ([Intel XE#653]) -> [SKIP][438] ([Intel XE#2136] / [Intel XE#2351]) +10 other tests skip
   [437]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html
   [438]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     [SKIP][439] ([Intel XE#653]) -> [SKIP][440] ([Intel XE#2136]) +26 other tests skip
   [439]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
   [440]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][441] ([Intel XE#2136]) -> [SKIP][442] ([Intel XE#653]) +11 other tests skip
   [441]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html
   [442]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-dg2-set2:     [SKIP][443] ([Intel XE#605]) -> [SKIP][444] ([Intel XE#2423] / [i915#2575])
   [443]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@kms_getfb@getfb-reject-ccs.html
   [444]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-lnl:          [SKIP][445] ([Intel XE#3374]) -> [SKIP][446] ([Intel XE#3374] / [Intel XE#3544])
   [445]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-lnl-5/igt@kms_hdr@brightness-with-hdr.html
   [446]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-lnl-1/igt@kms_hdr@brightness-with-hdr.html
    - shard-bmg:          [SKIP][447] ([Intel XE#3374]) -> [SKIP][448] ([Intel XE#3374] / [Intel XE#3544])
   [447]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-4/igt@kms_hdr@brightness-with-hdr.html
   [448]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-dg2-set2:     [SKIP][449] ([Intel XE#2423] / [i915#2575]) -> [SKIP][450] ([Intel XE#356])
   [449]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [450]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane_cursor@primary:
    - shard-dg2-set2:     [FAIL][451] ([Intel XE#616]) -> [SKIP][452] ([Intel XE#2423] / [i915#2575])
   [451]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@kms_plane_cursor@primary.html
   [452]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_plane_cursor@primary.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
    - shard-dg2-set2:     [SKIP][453] ([Intel XE#2423] / [i915#2575]) -> [SKIP][454] ([Intel XE#2763] / [Intel XE#455])
   [453]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
   [454]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling:
    - shard-dg2-set2:     [SKIP][455] ([Intel XE#2763] / [Intel XE#455]) -> [SKIP][456] ([Intel XE#2423] / [i915#2575]) +1 other test skip
   [455]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html
   [456]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2-set2:     [SKIP][457] ([Intel XE#3309]) -> [SKIP][458] ([Intel XE#2136])
   [457]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@kms_pm_dc@dc5-retention-flops.html
   [458]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_rpm@basic-rte:
    - shard-dg2-set2:     [ABORT][459] ([Intel XE#3468]) -> [SKIP][460] ([Intel XE#2446])
   [459]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@kms_pm_rpm@basic-rte.html
   [460]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_pm_rpm@basic-rte.html

  * igt@kms_pm_rpm@cursor:
    - shard-dg2-set2:     [SKIP][461] ([Intel XE#2446]) -> [ABORT][462] ([Intel XE#3468])
   [461]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_pm_rpm@cursor.html
   [462]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@kms_pm_rpm@cursor.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-bmg:          [DMESG-WARN][463] ([Intel XE#3468]) -> [DMESG-WARN][464] ([Intel XE#1727] / [Intel XE#3468]) +1 other test dmesg-warn
   [463]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [464]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
    - shard-dg2-set2:     [SKIP][465] ([Intel XE#2446]) -> [DMESG-WARN][466] ([Intel XE#1727] / [Intel XE#3468])
   [465]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [466]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@universal-planes-dpms:
    - shard-dg2-set2:     [DMESG-WARN][467] ([Intel XE#2042]) -> [SKIP][468] ([Intel XE#2446])
   [467]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@kms_pm_rpm@universal-planes-dpms.html
   [468]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_pm_rpm@universal-planes-dpms.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     [SKIP][469] ([Intel XE#2136]) -> [SKIP][470] ([Intel XE#1489]) +4 other tests skip
   [469]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf.html
   [470]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
    - shard-dg2-set2:     [SKIP][471] ([Intel XE#1489]) -> [SKIP][472] ([Intel XE#2136]) +10 other tests skip
   [471]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html
   [472]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2-set2:     [SKIP][473] ([Intel XE#1122]) -> [SKIP][474] ([Intel XE#2136])
   [473]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@kms_psr2_su@page_flip-p010.html
   [474]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr-sprite-plane-move:
    - shard-dg2-set2:     [SKIP][475] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][476] ([Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [475]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_psr@fbc-psr-sprite-plane-move.html
   [476]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@kms_psr@fbc-psr-sprite-plane-move.html

  * igt@kms_psr@fbc-psr2-no-drrs:
    - shard-dg2-set2:     [SKIP][477] ([Intel XE#2136]) -> [SKIP][478] ([Intel XE#2850] / [Intel XE#929]) +6 other tests skip
   [477]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_psr@fbc-psr2-no-drrs.html
   [478]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_psr@fbc-psr2-no-drrs.html

  * igt@kms_psr@pr-sprite-blt:
    - shard-dg2-set2:     [SKIP][479] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][480] ([Intel XE#2136]) +11 other tests skip
   [479]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@kms_psr@pr-sprite-blt.html
   [480]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_psr@pr-sprite-blt.html

  * igt@kms_psr@psr-dpms:
    - shard-dg2-set2:     [SKIP][481] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][482] ([Intel XE#2136] / [Intel XE#2351]) +5 other tests skip
   [481]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_psr@psr-dpms.html
   [482]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_psr@psr-dpms.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-dg2-set2:     [SKIP][483] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][484] ([Intel XE#2351])
   [483]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@kms_psr@psr-sprite-plane-onoff.html
   [484]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-dg2-set2:     [SKIP][485] ([Intel XE#3414]) -> [SKIP][486] ([Intel XE#2423] / [i915#2575])
   [485]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_rotation_crc@primary-rotation-90.html
   [486]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-dg2-set2:     [SKIP][487] ([Intel XE#1127]) -> [SKIP][488] ([Intel XE#2423] / [i915#2575])
   [487]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
   [488]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-dg2-set2:     [SKIP][489] ([Intel XE#2423] / [i915#2575]) -> [SKIP][490] ([Intel XE#3414])
   [489]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
   [490]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][491] ([Intel XE#2426]) -> [FAIL][492] ([Intel XE#1729])
   [491]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern.html
   [492]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][493] ([Intel XE#2423] / [i915#2575]) -> [SKIP][494] ([Intel XE#1500])
   [493]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [494]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-dpms:
    - shard-dg2-set2:     [SKIP][495] ([Intel XE#455]) -> [SKIP][496] ([Intel XE#2423] / [i915#2575]) +8 other tests skip
   [495]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@kms_vrr@flip-dpms.html
   [496]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_vrr@flip-dpms.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-dg2-set2:     [SKIP][497] ([Intel XE#756]) -> [SKIP][498] ([Intel XE#2423] / [i915#2575]) +2 other tests skip
   [497]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@kms_writeback@writeback-pixel-formats.html
   [498]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@kms_writeback@writeback-pixel-formats.html

  * igt@xe_ccs@suspend-resume:
    - shard-dg2-set2:     [SKIP][499] ([Intel XE#1130]) -> [DMESG-FAIL][500] ([Intel XE#1727] / [Intel XE#3468])
   [499]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_ccs@suspend-resume.html
   [500]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@xe_ccs@suspend-resume.html

  * igt@xe_compute_preempt@compute-preempt-many:
    - shard-dg2-set2:     [SKIP][501] ([Intel XE#1280] / [Intel XE#455]) -> [SKIP][502] ([Intel XE#1130])
   [501]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@xe_compute_preempt@compute-preempt-many.html
   [502]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@xe_compute_preempt@compute-preempt-many.html

  * igt@xe_copy_basic@mem-copy-linear-0x3fff:
    - shard-dg2-set2:     [SKIP][503] ([Intel XE#1130]) -> [SKIP][504] ([Intel XE#1123])
   [503]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@xe_copy_basic@mem-copy-linear-0x3fff.html
   [504]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@xe_copy_basic@mem-copy-linear-0x3fff.html

  * igt@xe_copy_basic@mem-copy-linear-0xfffe:
    - shard-dg2-set2:     [SKIP][505] ([Intel XE#1123]) -> [SKIP][506] ([Intel XE#1130])
   [505]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@xe_copy_basic@mem-copy-linear-0xfffe.html
   [506]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@xe_copy_basic@mem-copy-linear-0xfffe.html

  * igt@xe_copy_basic@mem-set-linear-0xfd:
    - shard-dg2-set2:     [SKIP][507] ([Intel XE#1130]) -> [SKIP][508] ([Intel XE#1126])
   [507]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0xfd.html
   [508]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@xe_copy_basic@mem-set-linear-0xfd.html

  * igt@xe_copy_basic@mem-set-linear-0xfffe:
    - shard-dg2-set2:     [SKIP][509] ([Intel XE#1126]) -> [SKIP][510] ([Intel XE#1130])
   [509]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@xe_copy_basic@mem-set-linear-0xfffe.html
   [510]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0xfffe.html

  * igt@xe_eudebug@basic-close:
    - shard-dg2-set2:     [SKIP][511] ([Intel XE#1130]) -> [SKIP][512] ([Intel XE#2905]) +4 other tests skip
   [511]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_eudebug@basic-close.html
   [512]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@xe_eudebug@basic-close.html

  * igt@xe_eudebug_online@resume-dss:
    - shard-dg2-set2:     [SKIP][513] ([Intel XE#2905]) -> [SKIP][514] ([Intel XE#1130]) +12 other tests skip
   [513]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@xe_eudebug_online@resume-dss.html
   [514]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@xe_eudebug_online@resume-dss.html

  * igt@xe_evict@evict-beng-large-multi-vm-cm:
    - shard-dg2-set2:     [FAIL][515] ([Intel XE#1600]) -> [SKIP][516] ([Intel XE#1130])
   [515]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@xe_evict@evict-beng-large-multi-vm-cm.html
   [516]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@xe_evict@evict-beng-large-multi-vm-cm.html

  * igt@xe_evict@evict-large-multi-vm-cm:
    - shard-bmg:          [FAIL][517] ([Intel XE#2364]) -> [DMESG-FAIL][518] ([Intel XE#3468])
   [517]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-5/igt@xe_evict@evict-large-multi-vm-cm.html
   [518]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@xe_evict@evict-large-multi-vm-cm.html

  * igt@xe_evict@evict-mixed-many-threads-large:
    - shard-dg2-set2:     [TIMEOUT][519] ([Intel XE#1473]) -> [SKIP][520] ([Intel XE#1130])
   [519]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@xe_evict@evict-mixed-many-threads-large.html
   [520]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@xe_evict@evict-mixed-many-threads-large.html

  * igt@xe_exec_fault_mode@many-basic-prefetch:
    - shard-dg2-set2:     [SKIP][521] ([Intel XE#1130]) -> [SKIP][522] ([Intel XE#288]) +14 other tests skip
   [521]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-466/igt@xe_exec_fault_mode@many-basic-prefetch.html
   [522]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@xe_exec_fault_mode@many-basic-prefetch.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch:
    - shard-dg2-set2:     [SKIP][523] ([Intel XE#288]) -> [SKIP][524] ([Intel XE#1130]) +30 other tests skip
   [523]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch.html
   [524]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence:
    - shard-dg2-set2:     [SKIP][525] ([Intel XE#2360]) -> [SKIP][526] ([Intel XE#1130])
   [525]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html
   [526]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_device_create:
    - shard-dg2-set2:     [DMESG-WARN][527] ([Intel XE#3467]) -> [SKIP][528] ([Intel XE#1130]) +3 other tests skip
   [527]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@xe_fault_injection@inject-fault-probe-function-xe_device_create.html
   [528]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@xe_fault_injection@inject-fault-probe-function-xe_device_create.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init:
    - shard-bmg:          [DMESG-WARN][529] ([Intel XE#3343]) -> [DMESG-WARN][530] ([Intel XE#3343] / [Intel XE#3468]) +1 other test dmesg-warn
   [529]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-8/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init.html
   [530]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init:
    - shard-dg2-set2:     [SKIP][531] ([Intel XE#1130]) -> [DMESG-WARN][532] ([Intel XE#3343])
   [531]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init.html
   [532]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init.html

  * igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_prepare:
    - shard-bmg:          [FAIL][533] ([Intel XE#3499]) -> [DMESG-FAIL][534] ([Intel XE#3467] / [Intel XE#3468]) +1 other test dmesg-fail
   [533]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-5/igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_prepare.html
   [534]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_prepare.html

  * igt@xe_fault_injection@vm-create-fail-xe_pt_create:
    - shard-bmg:          [DMESG-WARN][535] ([Intel XE#3467]) -> [DMESG-WARN][536] ([Intel XE#3467] / [Intel XE#3468])
   [535]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-6/igt@xe_fault_injection@vm-create-fail-xe_pt_create.html
   [536]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-1/igt@xe_fault_injection@vm-create-fail-xe_pt_create.html

  * igt@xe_live_ktest@xe_mocs:
    - shard-dg2-set2:     [SKIP][537] ([Intel XE#1192]) -> [FAIL][538] ([Intel XE#1999])
   [537]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-435/igt@xe_live_ktest@xe_mocs.html
   [538]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@xe_live_ktest@xe_mocs.html

  * igt@xe_mmap@small-bar:
    - shard-dg2-set2:     [SKIP][539] ([Intel XE#1130]) -> [SKIP][540] ([Intel XE#512])
   [539]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_mmap@small-bar.html
   [540]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@xe_mmap@small-bar.html

  * igt@xe_module_load@many-reload:
    - shard-dg2-set2:     [FAIL][541] ([Intel XE#2136]) -> [FAIL][542] ([Intel XE#3546])
   [541]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_module_load@many-reload.html
   [542]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@xe_module_load@many-reload.html

  * igt@xe_module_load@reload-no-display:
    - shard-dg2-set2:     [FAIL][543] ([Intel XE#2136]) -> [DMESG-WARN][544] ([Intel XE#3467])
   [543]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_module_load@reload-no-display.html
   [544]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-435/igt@xe_module_load@reload-no-display.html

  * igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
    - shard-dg2-set2:     [SKIP][545] ([Intel XE#2541]) -> [SKIP][546] ([Intel XE#1130]) +12 other tests skip
   [545]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html
   [546]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html

  * igt@xe_oa@whitelisted-registers-userspace-config:
    - shard-dg2-set2:     [SKIP][547] ([Intel XE#1130]) -> [SKIP][548] ([Intel XE#2541]) +4 other tests skip
   [547]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_oa@whitelisted-registers-userspace-config.html
   [548]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-463/igt@xe_oa@whitelisted-registers-userspace-config.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-dg2-set2:     [SKIP][549] ([Intel XE#1337]) -> [SKIP][550] ([Intel XE#1130])
   [549]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-436/igt@xe_pat@display-vs-wb-transient.html
   [550]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          [SKIP][551] ([Intel XE#2237] / [Intel XE#2245]) -> [SKIP][552] ([Intel XE#2245])
   [551]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-6/igt@xe_pat@pat-index-xelp.html
   [552]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-6/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pm@s2idle-vm-bind-prefetch:
    - shard-dg2-set2:     [DMESG-FAIL][553] ([Intel XE#3468]) -> [SKIP][554] ([Intel XE#1130])
   [553]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@xe_pm@s2idle-vm-bind-prefetch.html
   [554]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@xe_pm@s2idle-vm-bind-prefetch.html

  * igt@xe_pm@s2idle-vm-bind-userptr:
    - shard-dg2-set2:     [SKIP][555] ([Intel XE#1130]) -> [DMESG-WARN][556] ([Intel XE#1727] / [Intel XE#3468])
   [555]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_pm@s2idle-vm-bind-userptr.html
   [556]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@xe_pm@s2idle-vm-bind-userptr.html

  * igt@xe_pm@s3-basic-exec:
    - shard-dg2-set2:     [DMESG-WARN][557] ([Intel XE#569]) -> [SKIP][558] ([Intel XE#1130]) +1 other test skip
   [557]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@xe_pm@s3-basic-exec.html
   [558]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@xe_pm@s3-basic-exec.html

  * igt@xe_pm@s3-d3hot-basic-exec:
    - shard-bmg:          [DMESG-WARN][559] ([Intel XE#569]) -> [DMESG-WARN][560] ([Intel XE#1727] / [Intel XE#3468] / [Intel XE#569])
   [559]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-bmg-1/igt@xe_pm@s3-d3hot-basic-exec.html
   [560]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-bmg-8/igt@xe_pm@s3-d3hot-basic-exec.html
    - shard-dg2-set2:     [SKIP][561] ([Intel XE#1130]) -> [DMESG-WARN][562] ([Intel XE#3468] / [Intel XE#569])
   [561]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_pm@s3-d3hot-basic-exec.html
   [562]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@xe_pm@s3-d3hot-basic-exec.html

  * igt@xe_query@multigpu-query-oa-units:
    - shard-dg2-set2:     [SKIP][563] ([Intel XE#944]) -> [SKIP][564] ([Intel XE#1130]) +2 other tests skip
   [563]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-463/igt@xe_query@multigpu-query-oa-units.html
   [564]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@xe_query@multigpu-query-oa-units.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-dg2-set2:     [SKIP][565] ([Intel XE#1130]) -> [SKIP][566] ([Intel XE#3342])
   [565]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_sriov_flr@flr-each-isolation.html
   [566]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@xe_sriov_flr@flr-each-isolation.html

  * igt@xe_tlb@basic-tlb:
    - shard-dg2-set2:     [SKIP][567] ([Intel XE#1130]) -> [FAIL][568] ([Intel XE#2922])
   [567]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_tlb@basic-tlb.html
   [568]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-433/igt@xe_tlb@basic-tlb.html

  * igt@xe_vm@mixed-userptr-misaligned-binds-1611661312:
    - shard-dg2-set2:     [SKIP][569] ([Intel XE#1130]) -> [DMESG-WARN][570] ([Intel XE#1727])
   [569]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-434/igt@xe_vm@mixed-userptr-misaligned-binds-1611661312.html
   [570]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-436/igt@xe_vm@mixed-userptr-misaligned-binds-1611661312.html

  * igt@xe_vm@munmap-style-unbind-either-side-partial-split-page-hammer:
    - shard-dg2-set2:     [DMESG-WARN][571] ([Intel XE#1727]) -> [SKIP][572] ([Intel XE#1130]) +3 other tests skip
   [571]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-464/igt@xe_vm@munmap-style-unbind-either-side-partial-split-page-hammer.html
   [572]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-434/igt@xe_vm@munmap-style-unbind-either-side-partial-split-page-hammer.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-dg2-set2:     [ABORT][573] ([Intel XE#3075] / [Intel XE#3084]) -> [SKIP][574] ([Intel XE#1130])
   [573]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8118/shard-dg2-433/igt@xe_wedged@wedged-mode-toggle.html
   [574]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/shard-dg2-466/igt@xe_wedged@wedged-mode-toggle.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1152]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1152
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1430
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
  [Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
  [Intel XE#1616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1616
  [Intel XE#1695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1695
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1885]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1885
  [Intel XE#1999]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1999
  [Intel XE#2042]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2042
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
  [Intel XE#2141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2141
  [Intel XE#2159]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2159
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2237]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2237
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2248]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2248
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2280
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2364
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2446
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2514]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2514
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2566
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2613]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2613
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2715]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2715
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2864]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2864
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
  [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2919]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2919
  [Intel XE#2922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2922
  [Intel XE#2998]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2998
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#3070]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3070
  [Intel XE#3075]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3075
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#3084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3084
  [Intel XE#3088]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3088
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3184]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3184
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
  [Intel XE#3279]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3279
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3343
  [Intel XE#3371]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3371
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3433
  [Intel XE#3440]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3440
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#3466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3466
  [Intel XE#3467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3467
  [Intel XE#3468]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3468
  [Intel XE#3486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3486
  [Intel XE#3487]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3487
  [Intel XE#3499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3499
  [Intel XE#3521]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3521
  [Intel XE#3536]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3536
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3546]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3546
  [Intel XE#3557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3557
  [Intel XE#3559]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3559
  [Intel XE#356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/356
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
  [Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/958
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274


Build changes
-------------

  * IGT: IGT_8118 -> IGTPW_12158
  * Linux: xe-2252-f8f85a38f6c75e091805f01ceff4041ac2fdf3fd -> xe-2257-e46649e7764a9f6868ccbcba7b8b23b413303380

  IGTPW_12158: 12158
  IGT_8118: 17707095f1e5d3c30f463b43022f01c0160579b6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-2252-f8f85a38f6c75e091805f01ceff4041ac2fdf3fd: f8f85a38f6c75e091805f01ceff4041ac2fdf3fd
  xe-2257-e46649e7764a9f6868ccbcba7b8b23b413303380: e46649e7764a9f6868ccbcba7b8b23b413303380

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12158/index.html

[-- Attachment #2: Type: text/html, Size: 175673 bytes --]

Re: [PATCH i-g-t v2 1/4] lib/gppgu_shader: Add write D32 to ppgtt virtual address

[Gwan-gyeong Mun]

On 11/21/24 6:08 PM, Hajda, Andrzej wrote:
> 
> W dniu 21.11.2024 o 13:22, Gwan-gyeong Mun pisze:
>> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>
>> Create a function that adds the capabilty to write an dword size at a 
>> given
>> ppgtt address with a dword value. Use an Untyped 2D Block Array Store
>> DataPort functionality of XE2+ with A64 flat addressing to direct 
>> accessing
>> an entire ppgtt address space.
>>
>> For the write to succeed, the given ppgtt virtual address has to be 
>> bound.
>> Otherwise a store page fault will be triggered.
>>
>> v2: Fix the function name to be more clear. (Andrzej)
>>      Use lower_32_bits() / upper_32_bits() macro (Andrzej)
>>      Drop unused code
>>
>> Suggested-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
>> Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>> ---
>>   lib/gpgpu_shader.c          | 94 +++++++++++++++++++++++++++++++++++++
>>   lib/gpgpu_shader.h          |  2 +
>>   lib/iga64_generated_codes.c | 23 ++++++++-
>>   3 files changed, 118 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
>> index 4e1b8d5e9..d9da35895 100644
>> --- a/lib/gpgpu_shader.c
>> +++ b/lib/gpgpu_shader.c
>> @@ -803,3 +803,97 @@ void 
>> gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
>>       ", 0x807fffff, /* leave breakpoint exception */
>>       y_offset, value, 0x7fffff /* clear all exceptions */ );
>>   }
>> +
>> +/**
>> + * gpgpu_shader__write_a64_dword:
>> + * @shdr: shader to be modified
>> + * @ppgtt_addr: write target ppgtt virtual address
>> + * @value: dword to be written
>> + *
>> + * Write one D32 data (DW; DoubleWord) directly to the target ppgtt 
>> virtual
>> + * address (A64 Flat Address model).
>> + *
>> + * Note: for the write to succeed, the address specified by 
>> @ppgtt_addr has
>> + * to be bound. Otherwise a store page fault will be triggered.
>> + */
>> +void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, 
>> uint64_t ppgtt_addr,
>> +                   uint32_t value)
> 
> 
> Nice name, could be even gpgpu_shader__write_a64_d32, to follow spec 
> convention.
> 
Ok, will update.
> 
>> +{
>> +    uint64_t addr = CANONICAL(ppgtt_addr);
>> +    igt_assert_f((addr & 0x3) == 0, "address must be aligned to 
>> DWord!\n");
>> +
>> +    emit_iga64_code(shdr, write_a64_dword, "                \n\
>> +#if GEN_VER >= 2000                                \n\
>> +// Unyped 2D Block Store                            \n\
>> +// Instruction_Store2DBlock                            \n\
>> +// bspec: 63981                                    \n\
>> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies 
>> both        \n\
>> +//    the block parameters and the 2D Surface parameters.            \n\
>> +// src1 data payload format is selected by Data Size.                \n\
>> +// Untyped2DBLOCKAddressPayload                            \n\
>> +// bspec: 63986                                    \n\
>> +// [243:240] Array Length: 0 (length is 1)                    \n\
>> +// [239:232] Block Height: 0 (height is 1)                    \n\
>> +// [231:224] Block Width: 0xf (width is 16)                    \n\
>> +// [223:192] Block Start Y: 0                            \n\
>> +// [191:160] Block Start X: 0                            \n\
>> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 
>> bytes)            \n\
>> +// [127:96] Untyped 2D Surface Height: 0 (height is 1)                
>> \n\
>> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 
>> bytes)            \n\
>> +// [63:0] Untyped 2D Surface Base Address                    \n\
>> +// initialize register                                \n\
>> +(W)    mov (8)            r30.0<1>:uq    0x0:uq                \n\
>> +// [0:31] Untyped 2D Surface Base Address low                    \n\
>> +(W)    mov (1)            r30.0<1>:ud    ARG(0):ud            \n\
>> +// [32:63] Untyped 2D Surface Base Address high                    \n\
>> +(W)    mov (1)            r30.1<1>:ud ARG(1):ud                \n\
>> +// [95:64] Untyped 2D Surface Width: 0x3f                    \n\
>> +//       (Width minus 1 (in bytes) of the 2D surface, it represents 
>> 64)    \n\
>> +(W)    mov (1)         r30.2<1>:ud    0x3f:ud                \n\
>> +// [127:96] Untyped 2D Surface Height: 0x0                    \n\
>> +//        (Height minus 1 (in number of data elements) of            \n\
>> +//        the Untyped 2D surface, it represents 1)                \n\
>> +(W)    mov (1)         r30.3<1>:ud    0x0:ud                \n\
>> +// [159:128] Untyped 2D Surface Pitch: 0x3f                    \n\
>> +//         (Pitch minus 1 (in bytes) of the 2D surface, it represents 
>> 64)    \n\
>> +(W)    mov (1)            r30.4<1>:ud    0x3f:ud                \n\
>> +// [231:224] Block Width: 0xf (15)                        \n\
>> +//         (Specifies the width minus 1 (in number of data elements) 
>> for this    \n\
>> +//         rectangular region, it represents 16)                \n\
>> +// Block width (encoded_value + 1) must be a multiple of DW (4 
>> bytes).        \n\
>> +// [239:232] Block Height: 0                            \n\
>> +//         (Specifies the height minus 1 (in number of data elements) 
>> for    \n\
>> +//         this rectangular region, it represents 1)                \n\
>> +// [243:240] Array Length: 0                            \n\
>> +//         (Specifies Array Length minus 1 for Load2DBlockArray 
>> messages,    \n\
>> +//         must be zero for 2D Block Store messages, it represents 
>> 1)        \n\
>> +(W)    mov (1)            r30.7<1>:ud    0xf:ud                \n\
> 
> 
> Shouldn't this be 0x3:ud now, for dword ?
> 
No, r30.7 needs to set 0xf:ud.

please refer the Structure_Untyped2DBLOCKAddressPayload: bspec 63986

[31:0]    => r30.0:ud  <= [0:31] Untyped 2D Surface Base Address low
[63:32]   => r30.1:ud  <= [32:63] Untyped 2D Surface Base Address high
[95:64]   => r30.2:ud  <= [95:64] Untyped 2D Surface Width: 0x3f
[127:96]  => r30.3:ud  <= [127:96] Untyped 2D Surface Height: 0
[159:128] => r30.4:ud  <= [159:128] Untyped 2D Surface Pitch: 0x3f
[191:160] => r30.5:ud  <= [191:160] Block Start X: 0
[223:192] => r30.6:ud  <= [223:192] Block Start Y: 0
[251:224] => r30.7:ud  <= [231:224] Block Width: 0xf
                           [239:232] Block Height: 0
                           [243:240] Array Length: 0
                           ; 0xf

br,

G.G.
> Beside those details:
> 
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> 
> Regards
> Andrzej
> 
>> +// src1 data payload size                            \n\
>> +// Block Height x Block Width x Data size / GRF Register 
>> size            \n\
>> +//    => 1 x 16 x 32bit / 512bit = 1                        \n\
>> +// data payload size is 1                            \n\
>> +(W)    mov (8)            r31.0<1>:uq    0x0:uq                \n\
>> +(W)    mov (1|M0)        r31.0<1>:ud     ARG(2):ud            \n\
>> +// send.ugm Untyped 2D Block Array Store                    \n\
>> +// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc                \n\
>> +// Execution Mask restriction: SIMT1                        \n\
>> +//                                        \n\
>> +// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D 
>> Block)    \n\
>> +// bspec: 67780                                    \n\
>> +// 0x0 =>                                    \n\
>> +// [32:22] Global Y_offset: 0                            \n\
>> +// [21:12] Global X_offset: 0                            \n\
>> +//                                        \n\
>> +// Message Descriptor                                \n\
>> +// bspec: 63981                                    \n\
>> +// 0x2020407 =>                                    \n\
>> +// [30:29] Address Type: 0 (FLAT)                        \n\
>> +// [28:25] Src0 Length: 1                            \n\
>> +// [24:20] Dest Length: 0                            \n\
>> +// [19:16] Cache : 2 (L1UC_L3UC)                        \n\
>> +// [11:9] Data Size: 2 (D32)                            \n\
>> +// [5:0] Store Operation: 7                            \n\
>> +(W)    send.ugm (1)        null    r30    r31:1    0x0    
>> 0x2020407    \n\
>> +#endif                                        \n\
>> +    ", lower_32_bits(addr), upper_32_bits(addr), value);
>> +}
>> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
>> index c7c21c115..18a4c9725 100644
>> --- a/lib/gpgpu_shader.h
>> +++ b/lib/gpgpu_shader.h
>> @@ -85,6 +85,8 @@ void gpgpu_shader__write_dword(struct gpgpu_shader 
>> *shdr, uint32_t value,
>>                      uint32_t y_offset);
>>   void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, 
>> uint32_t dw, uint32_t x_offset,
>>                         uint32_t y_offset, uint32_t mask, uint32_t 
>> value);
>> +void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, 
>> uint64_t ppgtt_addr,
>> +                   uint32_t value);
>>   void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
>>   void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
>>   void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
>> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
>> index 6638be07b..e97bcf042 100644
>> --- a/lib/iga64_generated_codes.c
>> +++ b/lib/iga64_generated_codes.c
>> @@ -3,7 +3,7 @@
>>   #include "gpgpu_shader.h"
>> -#define MD5_SUM_IGA64_ASMS ec9d477415eebb7d6983395f1bcde78f
>> +#define MD5_SUM_IGA64_ASMS a1ee0173014ab4cda3090faeca1cbae1
>>   struct iga64_template const iga64_code_gpgpu_fill[] = {
>>       { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> @@ -79,6 +79,27 @@ struct iga64_template const iga64_code_gpgpu_fill[] 
>> = {
>>       }}
>>   };
>> +struct iga64_template const iga64_code_write_a64_dword[] = {
>> +    { .gen_ver = 2000, .size = 52, .code = (const uint32_t []) {
>> +        0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
>> +        0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
>> +        0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
>> +        0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
>> +        0x80000061, 0x1e354220, 0x00000000, 0x00000000,
>> +        0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
>> +        0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
>> +        0x800c0061, 0x1f054330, 0x00000000, 0x00000000,
>> +        0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
>> +        0x80032031, 0x00000000, 0xf80e1e0c, 0x00801f0c,
>> +        0x80000001, 0x00010000, 0x20000000, 0x00000000,
>> +        0x80000001, 0x00010000, 0x30000000, 0x00000000,
>> +        0x80000901, 0x00010000, 0x00000000, 0x00000000,
>> +    }},
>> +    { .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
>> +
>> +    }}
>> +};
>> +
>>   struct iga64_template const 
>> iga64_code_end_system_routine_step_if_eq[] = {
>>       { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>>           0x80000966, 0x80018220, 0x02008000, 0x00008000,

Re: [PATCH i-g-t v2 2/4] lib/gppgu_shader: Add read D32 from ppgtt virtual address

[Gwan-gyeong Mun]

On 11/21/24 6:14 PM, Hajda, Andrzej wrote:
> 
> W dniu 21.11.2024 o 13:22, Gwan-gyeong Mun pisze:
>> Create a function that adds the capabilty to read an dword size from a
>> given ppgtt address. Use an Untyped 2D Block Array Load DataPort
>> functionality of XE2+ with A64 flat addressing to direct accessing an
>> entire ppgtt address space.
>>
>> For the read to succeed, the given ppgtt virtual address has to be bound.
>> Otherwise a load page fault will be triggered.
>>
>> v2: Fix the function name to be more clear. (Christoph)
>>
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> ---
>>   lib/gpgpu_shader.c          | 94 +++++++++++++++++++++++++++++++++++++
>>   lib/gpgpu_shader.h          |  1 +
>>   lib/iga64_generated_codes.c | 21 ++++++++-
>>   3 files changed, 115 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
>> index d9da35895..147df3a3d 100644
>> --- a/lib/gpgpu_shader.c
>> +++ b/lib/gpgpu_shader.c
>> @@ -897,3 +897,97 @@ void gpgpu_shader__write_a64_dword(struct 
>> gpgpu_shader *shdr, uint64_t ppgtt_add
>>   #endif                                        \n\
>>       ", lower_32_bits(addr), upper_32_bits(addr), value);
>>   }
>> +
>> +/**
>> + * gpgpu_shader__read_a64_dword:
>> + * @shdr: shader to be modified
>> + * @ppgtt_addr: read target ppgtt virtual address
>> + *
>> + * Read one D32 data (DW; DoubleWord) directly from the target ppgtt 
>> virtual
>> + * address (A64 Flat Address model).
>> + *
>> + * Note: for the read to succeed, the address specified by 
>> @ppgtt_addr has
>> + * to be bound. Otherwise a load page fault will be triggered.
>> + */
>> +void gpgpu_shader__read_a64_dword(struct gpgpu_shader *shdr, uint64_t 
>> ppgtt_addr)
>> +{
>> +    uint64_t addr = CANONICAL(ppgtt_addr);
>> +
>> +    igt_assert_f((addr & 0x3) == 0, "address must be aligned to 
>> DWord!\n");
>> +
>> +    emit_iga64_code(shdr, read_a64_dword, "                    \n\
>> +#if GEN_VER >= 2000                                \n\
>> +// Unyped 2D Block Array Load                             \n\
>> +// Instruction_Load2DBlockArray                            \n\
>> +// bspec: 63972                                    \n\
>> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies 
>> both        \n\
>> +//    the block parameters and the 2D Surface parameters.            \n\
>> +// Untyped2DBLOCKAddressPayload                            \n\
>> +// bspec: 63986                                    \n\
>> +// [243:240] Array Length: 0 (length is 1)                    \n\
>> +// [239:232] Block Height: 0 (height is 1)                    \n\
>> +// [231:224] Block Width: 0xf (width is 16)                    \n\
>> +// [223:192] Block Start Y: 0                            \n\
>> +// [191:160] Block Start X: 0                            \n\
>> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 
>> bytes)            \n\
>> +// [127:96] Untyped 2D Surface Height: 0 (height is 1)                
>> \n\
>> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 
>> bytes)            \n\
>> +// [63:0] Untyped 2D Surface Base Address                    \n\
>> +// initialize register                                \n\
>> +(W)    mov (8)            r30.0<1>:uq    0x0:uq                \n\
>> +// [0:31] Untyped 2D Surface Base Address low                    \n\
>> +(W)    mov (1)            r30.0<1>:ud    ARG(0):ud            \n\
>> +// [32:63] Untyped 2D Surface Base Address high                    \n\
>> +(W)    mov (1)            r30.1<1>:ud ARG(1):ud                \n\
>> +// [95:64] Untyped 2D Surface Width: 0x3f                    \n\
>> +//       (Width minus 1 (in bytes) of the 2D surface, it represents 
>> 64)    \n\
>> +(W)    mov (1)         r30.2<1>:ud    0x3f:ud                \n\
>> +// [127:96] Untyped 2D Surface Height: 0x0                    \n\
>> +//        (Height minus 1 (in number of data elements) of            \n\
>> +//        the Untyped 2D surface, it represents 1)                \n\
>> +(W)    mov (1)         r30.3<1>:ud    0x0:ud                \n\
> 
> 
> No need to setting to 0 twice.
> 
will drop it.
> 
>> +// [159:128] Untyped 2D Surface Pitch: 0x3f                    \n\
>> +//         (Pitch minus 1 (in bytes) of the 2D surface, it represents 
>> 64)    \n\
>> +(W)    mov (1)            r30.4<1>:ud    0x3f:ud                \n\
>> +// [231:224] Block Width: 0xf (15)                        \n\
>> +//         (Specifies the width minus 1 (in number of data elements) 
>> for this    \n\
>> +//         rectangular region, it represents 16)                \n\
>> +// Block width (encoded_value + 1) must be a multiple of DW (4 
>> bytes).        \n\
>> +// [239:232] Block Height: 0                            \n\
>> +//         (Specifies the height minus 1 (in number of data elements) 
>> for    \n\
>> +//         this rectangular region, it represents 1)                \n\
>> +// [243:240] Array Length: 0                            \n\
>> +//         (Specifies Array Length minus 1 for Load2DBlockArray 
>> messages,    \n\
>> +//         must be zero for 2D Block Store messages, it represents 
>> 1)        \n\
>> +(W)    mov (1)            r30.7<1>:ud    0xf:ud                \n\
> 
> 
> Again maybe 0x3.
> 
> 
  As explained in the reply to the “[i-g-t,v2,1/4] lib/gppgu_shader: Add 
write D32 to ppgtt virtual address” patch, this is what r30.7 needs to 
set as 0xf:ud.

Br,
G.G.

>> +//                                        \n\
>> +// dest data payload format is selected by Data Size.                \n\
>> +// Block Height x Block Width x Data size / GRF Register 
>> size            \n\
>> +//    => 1 x 16 x 32bit / 512bit = 1                        \n\
>> +// data payload format size is 1 GRF Register.                    \n\
>> +//                                        \n\
>> +// send.ugm Untyped 2D Block Array Load                        \n\
>> +// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc                \n\
>> +// Execution Mask restriction: SIMT1                        \n\
>> +//                                        \n\
>> +// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D 
>> Block)    \n\
>> +// bspec: 67780                                    \n\
>> +// 0x0 =>                                    \n\
>> +// [32:22] Global Y_offset: 0                            \n\
>> +// [21:12] Global X_offset: 0                            \n\
>> +//                                        \n\
>> +// Message Descriptor                                \n\
>> +// bspec: 63972                                    \n\
>> +// 0x2128403 =>                                    \n\
>> +// [30:29] Address Type: 0 (FLAT)                        \n\
>> +// [28:25] Src0 Length: 1                            \n\
>> +// [24:20] Dest Length: 1                            \n\
>> +// [19:16] Cache : 2 (L1UC_L3UC) 10                        \n\
>> +// [15] Transpose Block: 1                            \n\
>> +// [11:9] Data Size: 2 (D32) 10                            \n\
>> +// [7] VNNI Transform: 0                            \n\
>> +// [5:0] Load Operation: 3 (Load 2D Block) 11                    \n\
>> +(W)    send.ugm (1)        r31    r30    null    0x0    0x2128403    \n\
>> +#endif                                        \n\
>> +    ", lower_32_bits(addr), upper_32_bits(addr));
> 
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> 
> Regards
> Andrzej
> 
>> +}
>> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
>> index 18a4c9725..07ed0fe1b 100644
>> --- a/lib/gpgpu_shader.h
>> +++ b/lib/gpgpu_shader.h
>> @@ -87,6 +87,7 @@ void gpgpu_shader__write_on_exception(struct 
>> gpgpu_shader *shdr, uint32_t dw, ui
>>                         uint32_t y_offset, uint32_t mask, uint32_t 
>> value);
>>   void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, 
>> uint64_t ppgtt_addr,
>>                      uint32_t value);
>> +void gpgpu_shader__read_a64_dword(struct gpgpu_shader *shdr, uint64_t 
>> ppgtt_addr);
>>   void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
>>   void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
>>   void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
>> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
>> index e97bcf042..721ac267f 100644
>> --- a/lib/iga64_generated_codes.c
>> +++ b/lib/iga64_generated_codes.c
>> @@ -3,7 +3,7 @@
>>   #include "gpgpu_shader.h"
>> -#define MD5_SUM_IGA64_ASMS a1ee0173014ab4cda3090faeca1cbae1
>> +#define MD5_SUM_IGA64_ASMS bdc80eeb9a11b97ff51422a39f4623f5
>>   struct iga64_template const iga64_code_gpgpu_fill[] = {
>>       { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> @@ -79,6 +79,25 @@ struct iga64_template const iga64_code_gpgpu_fill[] 
>> = {
>>       }}
>>   };
>> +struct iga64_template const iga64_code_read_a64_dword[] = {
>> +    { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> +        0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
>> +        0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
>> +        0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
>> +        0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
>> +        0x80000061, 0x1e354220, 0x00000000, 0x00000000,
>> +        0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
>> +        0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
>> +        0x80032031, 0x1f0c0000, 0xf8061e0c, 0x00a00000,
>> +        0x80000001, 0x00010000, 0x20000000, 0x00000000,
>> +        0x80000001, 0x00010000, 0x30000000, 0x00000000,
>> +        0x80000901, 0x00010000, 0x00000000, 0x00000000,
>> +    }},
>> +    { .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
>> +
>> +    }}
>> +};
>> +
>>   struct iga64_template const iga64_code_write_a64_dword[] = {
>>       { .gen_ver = 2000, .size = 52, .code = (const uint32_t []) {
>>           0x800c0061, 0x1e054330, 0x00000000, 0x00000000,

Re: [PATCH i-g-t v2 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests

[Gwan-gyeong Mun]

On 11/21/24 7:12 PM, Manszewski, Christoph wrote:
> Hi Gwan-gyeong,
> 
> On 21.11.2024 13:22, Gwan-gyeong Mun wrote:
>> Add read and write pagefault tests to xe_eudebug_online that checks if a
>> pagefault event is submitted by the KMD debugger when a pagefault occurs.
>>
>> Test that read (load instruction) and write(store instruction) attempt to
>> load or store access to unallocated memory, causing a pagefault.
>> Examine the address causing the page fault and the number of eu threads
>> causing the pagefault.
>>
>> v2: Refactor of output attention bits on pagefault event handling 
>> (Andrzej)
>>      remove / update redudant code (Andrzej, Christoph)
>>      use igt_container_of() macro (Christoph)
>>
>> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> ---
>>   tests/intel/xe_eudebug_online.c | 178 +++++++++++++++++++++++++++++++-
>>   1 file changed, 173 insertions(+), 5 deletions(-)
>>
>> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/ 
>> xe_eudebug_online.c
>> index 0ef0d8093..a70d18ee4 100644
>> --- a/tests/intel/xe_eudebug_online.c
>> +++ b/tests/intel/xe_eudebug_online.c
>> @@ -36,6 +36,8 @@
>>   #define BB_IN_VRAM            (1 << 11)
>>   #define TARGET_IN_SRAM            (1 << 12)
>>   #define TARGET_IN_VRAM            (1 << 13)
>> +#define SHADER_PAGEFAULT_READ        (1 << 14)
>> +#define SHADER_PAGEFAULT_WRITE        (1 << 15)
>>   #define TRIGGER_UFENCE_SET_BREAKPOINT    (1 << 24)
>>   #define TRIGGER_RESUME_SINGLE_WALK    (1 << 25)
>>   #define TRIGGER_RESUME_PARALLEL_WALK    (1 << 26)
>> @@ -45,6 +47,7 @@
>>   #define TRIGGER_RESUME_DSS        (1 << 30)
>>   #define TRIGGER_RESUME_ONE        (1 << 31)
>> +#define SHADER_PAGEFAULT    (SHADER_PAGEFAULT_READ | 
>> SHADER_PAGEFAULT_WRITE)
>>   #define BB_REGION_BITMASK    (BB_IN_SRAM | BB_IN_VRAM)
>>   #define TARGET_REGION_BITMASK    (TARGET_IN_SRAM | TARGET_IN_VRAM)
>> @@ -61,6 +64,8 @@
>>   #define CACHING_VALUE(n)    (CACHING_INIT_VALUE + (n))
>>   #define SHADER_CANARY 0x01010101
>> +#define BAD_CANARY 0xf1f1f1f
>> +#define BAD_OFFSET (0x12345678ull << 12)
>>   #define WALKER_X_DIM        4
>>   #define WALKER_ALIGNMENT    16
>> @@ -120,7 +125,7 @@ static struct intel_buf *create_uc_buf(int fd, int 
>> width, int height, uint64_t r
>>   static int get_number_of_threads(uint64_t flags)
>>   {
>> -    if (flags & SHADER_MIN_THREADS)
>> +    if (flags & (SHADER_MIN_THREADS | SHADER_PAGEFAULT))
>>           return 16;
>>       if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
>> @@ -179,6 +184,16 @@ static struct gpgpu_shader *get_shader(int fd, 
>> const unsigned int flags)
>>               gpgpu_shader__common_target_write_u32(shader, s_dim.y + 
>> i, CACHING_VALUE(i));
>>           gpgpu_shader__nop(shader);
>>           gpgpu_shader__breakpoint(shader);
>> +    } else if (flags & SHADER_PAGEFAULT) {
>> +        if (flags & SHADER_PAGEFAULT_READ)
>> +            gpgpu_shader__read_a64_dword(shader, BAD_OFFSET);
>> +        else
>> +            gpgpu_shader__write_a64_dword(shader, BAD_OFFSET, 
>> BAD_CANARY);
>> +
>> +        gpgpu_shader__label(shader, 0);
>> +        gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>> +        gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
>> +        gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
> 
> Now that I think about - do we need this to be a loop? Can't we just do 
> the read/write instructions? This would simplify the code and I don't 
> yet see why we need to loop within the shader. The SHADER_LOOP is used 
> for interrupt-all because we want to interrupt the workload from the 
> user/main igt thread. But here, similar to the basic-breakpoint test, we 
> just submit a workload that will halt because of the hardware/kmd 
> intervention.
> 
the pagefault tests also need this concept.

When a pagefault happened, KMD sets “Force Exception / Force External 
Halt” in TD_CTL to cause the eu threads to enter SIP mode.
In the pagefault handling process of eudebug, kmd installs a null page 
at the address where the pagefault happened and makes the halted eu 
threads resume (make unhalt).

It would be ideal if all unhalted eu threads immediately entered SIP 
mode due to the FE/FEH settings, but it may not happen immediately.
Therefore, the purpose of using a loop is to ensure that the kernel 
shader does not terminate until a pagefault event and attention event 
occur by adding an additional instruction after the instruction that 
causes the page fault.
Therefore, a loop is used to ensure that at least one eu thread must 
enter SIP mode.
The attention callback sets to exit this loop, so this code allows the 
eu thread to terminate after the sip shader is processed.

Br,
G.G.
>>       }
>>       gpgpu_shader__eot(shader);
>> @@ -217,6 +232,16 @@ static int count_set_bits(void *ptr, size_t size)
>>       return count;
>>   }
>> +static int eu_attentions_xor_count(const uint32_t *a, const uint32_t 
>> *b, uint32_t size)
>> +{
>> +    int count = 0;
>> +
>> +    for (int i = 0; i < size / 4 ; i++)
>> +        count += igt_hweight(a[i] ^ b[i]);
>> +
>> +    return count;
>> +}
>> +
>>   static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim, 
>> uint32_t value)
>>   {
>>       int count = 0;
>> @@ -636,7 +661,7 @@ static void eu_attention_resume_trigger(struct 
>> xe_eudebug_debugger *d,
>>           }
>>       }
>> -    if (d->flags & SHADER_LOOP) {
>> +    if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
> 
> If we drop the loop we can drop also this.
> 
>>           uint32_t threads = get_number_of_threads(d->flags);
>>           uint32_t val = STEERING_END_LOOP;
>> @@ -746,6 +771,44 @@ static void 
>> eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
>>               data->single_step_bitmask[i] &= ~att->bitmask[i];
>>   }
>> +static void eu_attention_resume_pagefault_trigger(struct 
>> xe_eudebug_debugger *d,
>> +                          struct drm_xe_eudebug_event *e)
>> +{
>> +    struct drm_xe_eudebug_event_eu_attention *att = 
>> igt_container_of(e, att, base);
>> +    struct online_debug_data *data = d->ptr;
>> +    uint32_t bitmask_size = att->bitmask_size;
>> +    uint8_t *bitmask;
>> +
>> +    if (data->last_eu_control_seqno > att->base.seqno)
>> +        return;
>> +
>> +    bitmask = calloc(1, att->bitmask_size);
>> +    igt_assert(bitmask);
>> +
>> +    eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
>> +               att->lrc_handle, bitmask, &bitmask_size);
>> +    igt_assert(bitmask_size == att->bitmask_size);
>> +
>> +    pthread_mutex_lock(&data->mutex);
>> +
>> +    if (d->flags & SHADER_PAGEFAULT) {
>> +        uint32_t threads = get_number_of_threads(d->flags);
>> +        uint32_t val = STEERING_END_LOOP;
>> +
>> +        igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
>> +                     data->target_offset + steering_offset(threads)),
>> +                  sizeof(uint32_t));
>> +        fsync(data->vm_fd);
>> +    }
> 
> We can also drop this when we remove the loop. Btw. why can't we just 
> use 'eu_attention_resume_trigger' instead of this whole function?
> 
>> +    pthread_mutex_unlock(&data->mutex);
>> +
>> +    data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, 
>> att->client_handle,
>> +                            att->exec_queue_handle, att->lrc_handle,
>> +                            bitmask, att->bitmask_size);
>> +
>> +    free(bitmask);
>> +}
>> +
>>   static void open_trigger(struct xe_eudebug_debugger *d,
>>                struct drm_xe_eudebug_event *e)
>>   {
>> @@ -1015,7 +1078,7 @@ static void run_online_client(struct 
>> xe_eudebug_client *c)
>>       struct intel_bb *ibb;
>>       struct intel_buf *buf;
>>       uint32_t *ptr;
>> -    int fd;
>> +    int fd, vm_flags;
>>       metadata[0] = calloc(2, sizeof(*metadata));
>>       metadata[1] = calloc(2, sizeof(*metadata));
>> @@ -1025,7 +1088,7 @@ static void run_online_client(struct 
>> xe_eudebug_client *c)
>>       fd = xe_eudebug_client_open_driver(c);
>>       /* Additional memory for steering control */
>> -    if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
>> +    if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || c- 
>> >flags & SHADER_PAGEFAULT)
>>           s_dim.y++;
>>       /* Additional memory for caching check */
>>       if ((c->flags & SHADER_CACHING_SRAM) || (c->flags & 
>> SHADER_CACHING_VRAM))
>> @@ -1045,7 +1108,11 @@ static void run_online_client(struct 
>> xe_eudebug_client *c)
>>                                  DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
>>                                  2 * sizeof(*metadata), metadata[1]);
>> -    create.vm_id = xe_eudebug_client_vm_create(c, fd, 
>> DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
>> +    vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
>> +    vm_flags |= c->flags & SHADER_PAGEFAULT ? 
>> DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
>> +
>> +    create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
>> +
>>       xe_eudebug_client_exec_queue_create(c, fd, &create);
>>       ibb = xe_bb_create_on_offset(fd, create.exec_queue_id, 
>> create.vm_id, bb_offset, bb_size,
>> @@ -1245,11 +1312,13 @@ match_attention_with_exec_queue(struct 
>> xe_eudebug_event_log *log,
>>   static void online_session_check(struct xe_eudebug_session *s, int 
>> flags)
>>   {
>>       struct drm_xe_eudebug_event_eu_attention *ea = NULL;
>> +    struct drm_xe_eudebug_event_pagefault *pf = NULL;
>>       struct drm_xe_eudebug_event *event = NULL;
>>       struct online_debug_data *data = s->client->ptr;
>>       bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
>>       int sum = 0;
>>       int bitmask_size;
>> +    int pagefault_threads = 0;
>>       xe_eudebug_session_check(s, true, XE_EUDEBUG_FILTER_EVENT_VM_BIND |
>>                         XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
>> @@ -1265,6 +1334,17 @@ static void online_session_check(struct 
>> xe_eudebug_session *s, int flags)
>>               igt_assert_eq(ea->bitmask_size, bitmask_size);
>>               sum += count_set_bits(ea->bitmask, bitmask_size);
>>               igt_assert(match_attention_with_exec_queue(s->debugger- 
>> >log, ea));
>> +        } else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
>> +            uint32_t after_offset = bitmask_size / sizeof(uint32_t);
>> +            uint32_t resolved_offset = bitmask_size / 
>> sizeof(uint32_t) * 2;
>> +            uint32_t *ptr = NULL;
>> +
>> +            pf = igt_container_of(event, pf, base);
>> +            ptr = (uint32_t *) pf->bitmask;
>> +            igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
>> +            pagefault_threads += eu_attentions_xor_count(ptr + 
>> after_offset,
>> +                                     ptr + resolved_offset,
>> +                                     bitmask_size);
>>           }
>>       }
>> @@ -1279,6 +1359,9 @@ static void online_session_check(struct 
>> xe_eudebug_session *s, int flags)
>>           igt_assert(sum > 0);
>>       else
>>           igt_assert(sum == 0);
>> +
>> +    if (flags & SHADER_PAGEFAULT)
>> +        igt_assert(pagefault_threads > 0);
>>   }
>>   static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
>> @@ -1302,6 +1385,43 @@ static void ufence_ack_set_bp_trigger(struct 
>> xe_eudebug_debugger *d,
>>       }
>>   }
>> +static void pagefault_trigger(struct xe_eudebug_debugger *d,
>> +                  struct drm_xe_eudebug_event *e)
>> +{
>> +    struct drm_xe_eudebug_event_pagefault *pf = igt_container_of(e, 
>> pf, base);
>> +    uint32_t attn_size = pf->bitmask_size / 3;
>> +    int attn_size_as_u32 = attn_size / sizeof(uint32_t);
>> +    uint32_t *ptr = (uint32_t *) pf->bitmask;
>> +    uint32_t *ptrs[3] = {ptr, ptr + attn_size_as_u32, ptr + 2 * 
>> attn_size_as_u32};
>> +    const char * const name[3] = {"before", "after", "resolved"};
>> +    int threads[3], pagefault_threads, idx;
>> +
>> +    for (idx = 0; idx < 3; idx++)
>> +        threads[idx] = count_set_bits(ptrs[idx], attn_size);
>> +
>> +    pagefault_threads = eu_attentions_xor_count(ptrs[1], ptrs[2], 
>> attn_size);
>> +
>> +    igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
>> +          "resolved=%d, pagefault=%d] "
>> +          "client[%llu], exec_queue[%llu], lrc[%llu], 
>> bitmask_size[%d], "
>> +          "pagefault_address[0x%llx]\n",
>> +          pf->base.seqno, threads[0], threads[1], threads[2],
>> +          pagefault_threads, pf->client_handle, pf->exec_queue_handle,
>> +          pf->lrc_handle, pf->bitmask_size,
>> +          pf->pagefault_address);
>> +
>> +    for (idx = 0; idx < 3; idx++) {
>> +        igt_debug("=== Attentions %s ===\n", name[idx]);
>> +
>> +        for (uint32_t i = 0; i < attn_size_as_u32; i += 2)
>> +            igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
>> +                  ptrs[idx][i], ptrs[idx][i + 1]);
>> +    }
>> +
>> +    igt_assert(pagefault_threads > 0);
>> +    igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
>> +}
>> +
>>   /**
>>    * SUBTEST: basic-breakpoint
>>    * Description:
>> @@ -1383,6 +1503,49 @@ static void test_set_breakpoint_online(int fd, 
>> struct drm_xe_engine_class_instan
>>       online_debug_data_destroy(data);
>>   }
>> +/**
>> + * SUBTEST: pagefault-read
>> + * Description:
>> + *     Check whether KMD sends pagefault event for workload in debug 
>> mode that
>> + *     triggers a read pagefault.
>> + *
>> + * SUBTEST: pagefault-write
>> + * Description:
>> + *     Check whether KMD sends pagefault event for workload in debug 
>> mode that
>> + *     triggers a write pagefault.
>> + */
>> +static void test_pagefault_online(int fd, struct 
>> drm_xe_engine_class_instance *hwe,
>> +                  int flags)
>> +{
>> +    struct xe_eudebug_session *s;
>> +    struct online_debug_data *data;
>> +
>> +    data = online_debug_data_create(hwe);
>> +    s = xe_eudebug_session_create(fd, run_online_client, flags, data);
>> +
>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>> DRM_XE_EUDEBUG_EVENT_OPEN,
>> +                    open_trigger);
>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>> DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
>> +                    exec_queue_trigger);
>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
>> +                    eu_attention_debug_trigger);
>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
>> +                    eu_attention_resume_pagefault_trigger);
>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>> DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>> DRM_XE_EUDEBUG_EVENT_METADATA,
>> +                    create_metadata_trigger);
>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>> DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
>> +                    ufence_ack_trigger);
>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>> DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
>> +                    pagefault_trigger);
> 
> Removing the loop would make it possible to reduce this to 3 triggers.
> 
> So again, I may be missing some detail that implies we need a loop in 
> the shader. But for now it looks to me like we don't.
> 
> Thanks,
> Christoph
> 
>> +
>> +    xe_eudebug_session_run(s);
>> +    online_session_check(s, s->flags);
>> +
>> +    xe_eudebug_session_destroy(s);
>> +    online_debug_data_destroy(data);
>> +}
>> +
>>   /**
>>    * SUBTEST: preempt-breakpoint
>>    * Description:
>> @@ -2344,6 +2507,11 @@ igt_main
>>       igt_subtest("breakpoint-many-sessions-tiles")
>>           test_many_sessions_on_tiles(fd, true);
>> +    test_gt_render_or_compute("pagefault-read", fd, hwe)
>> +        test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
>> +    test_gt_render_or_compute("pagefault-write", fd, hwe)
>> +        test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
>> +
>>       igt_fixture {
>>           xe_eudebug_enable(fd, was_enabled);

Re: [PATCH i-g-t v2 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests

[Manszewski, Christoph]

Hi Gwan-gyeong,

On 22.11.2024 09:21, Gwan-gyeong Mun wrote:
> 
> 
> On 11/21/24 7:12 PM, Manszewski, Christoph wrote:
>> Hi Gwan-gyeong,
>>
>> On 21.11.2024 13:22, Gwan-gyeong Mun wrote:
>>> Add read and write pagefault tests to xe_eudebug_online that checks if a
>>> pagefault event is submitted by the KMD debugger when a pagefault 
>>> occurs.
>>>
>>> Test that read (load instruction) and write(store instruction) 
>>> attempt to
>>> load or store access to unallocated memory, causing a pagefault.
>>> Examine the address causing the page fault and the number of eu threads
>>> causing the pagefault.
>>>
>>> v2: Refactor of output attention bits on pagefault event handling 
>>> (Andrzej)
>>>      remove / update redudant code (Andrzej, Christoph)
>>>      use igt_container_of() macro (Christoph)
>>>
>>> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>>> ---
>>>   tests/intel/xe_eudebug_online.c | 178 +++++++++++++++++++++++++++++++-
>>>   1 file changed, 173 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/ 
>>> xe_eudebug_online.c
>>> index 0ef0d8093..a70d18ee4 100644
>>> --- a/tests/intel/xe_eudebug_online.c
>>> +++ b/tests/intel/xe_eudebug_online.c
>>> @@ -36,6 +36,8 @@
>>>   #define BB_IN_VRAM            (1 << 11)
>>>   #define TARGET_IN_SRAM            (1 << 12)
>>>   #define TARGET_IN_VRAM            (1 << 13)
>>> +#define SHADER_PAGEFAULT_READ        (1 << 14)
>>> +#define SHADER_PAGEFAULT_WRITE        (1 << 15)
>>>   #define TRIGGER_UFENCE_SET_BREAKPOINT    (1 << 24)
>>>   #define TRIGGER_RESUME_SINGLE_WALK    (1 << 25)
>>>   #define TRIGGER_RESUME_PARALLEL_WALK    (1 << 26)
>>> @@ -45,6 +47,7 @@
>>>   #define TRIGGER_RESUME_DSS        (1 << 30)
>>>   #define TRIGGER_RESUME_ONE        (1 << 31)
>>> +#define SHADER_PAGEFAULT    (SHADER_PAGEFAULT_READ | 
>>> SHADER_PAGEFAULT_WRITE)
>>>   #define BB_REGION_BITMASK    (BB_IN_SRAM | BB_IN_VRAM)
>>>   #define TARGET_REGION_BITMASK    (TARGET_IN_SRAM | TARGET_IN_VRAM)
>>> @@ -61,6 +64,8 @@
>>>   #define CACHING_VALUE(n)    (CACHING_INIT_VALUE + (n))
>>>   #define SHADER_CANARY 0x01010101
>>> +#define BAD_CANARY 0xf1f1f1f
>>> +#define BAD_OFFSET (0x12345678ull << 12)
>>>   #define WALKER_X_DIM        4
>>>   #define WALKER_ALIGNMENT    16
>>> @@ -120,7 +125,7 @@ static struct intel_buf *create_uc_buf(int fd, 
>>> int width, int height, uint64_t r
>>>   static int get_number_of_threads(uint64_t flags)
>>>   {
>>> -    if (flags & SHADER_MIN_THREADS)
>>> +    if (flags & (SHADER_MIN_THREADS | SHADER_PAGEFAULT))
>>>           return 16;
>>>       if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
>>> @@ -179,6 +184,16 @@ static struct gpgpu_shader *get_shader(int fd, 
>>> const unsigned int flags)
>>>               gpgpu_shader__common_target_write_u32(shader, s_dim.y + 
>>> i, CACHING_VALUE(i));
>>>           gpgpu_shader__nop(shader);
>>>           gpgpu_shader__breakpoint(shader);
>>> +    } else if (flags & SHADER_PAGEFAULT) {
>>> +        if (flags & SHADER_PAGEFAULT_READ)
>>> +            gpgpu_shader__read_a64_dword(shader, BAD_OFFSET);
>>> +        else
>>> +            gpgpu_shader__write_a64_dword(shader, BAD_OFFSET, 
>>> BAD_CANARY);
>>> +
>>> +        gpgpu_shader__label(shader, 0);
>>> +        gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>>> +        gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
>>> +        gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>>
>> Now that I think about - do we need this to be a loop? Can't we just 
>> do the read/write instructions? This would simplify the code and I 
>> don't yet see why we need to loop within the shader. The SHADER_LOOP 
>> is used for interrupt-all because we want to interrupt the workload 
>> from the user/main igt thread. But here, similar to the 
>> basic-breakpoint test, we just submit a workload that will halt 
>> because of the hardware/kmd intervention.
>>
> the pagefault tests also need this concept.
> 
> When a pagefault happened, KMD sets “Force Exception / Force External 
> Halt” in TD_CTL to cause the eu threads to enter SIP mode.
> In the pagefault handling process of eudebug, kmd installs a null page 
> at the address where the pagefault happened and makes the halted eu 
> threads resume (make unhalt).
> 
> It would be ideal if all unhalted eu threads immediately entered SIP 
> mode due to the FE/FEH settings, but it may not happen immediately.
> Therefore, the purpose of using a loop is to ensure that the kernel 
> shader does not terminate until a pagefault event and attention event 
> occur by adding an additional instruction after the instruction that 
> causes the page fault.
> Therefore, a loop is used to ensure that at least one eu thread must 
> enter SIP mode.

Yeah if the count of processed instructions before the exception is not 
defined then indeed the loop has it's place here. But we still may 
reduce a little bit of code, see below.

> The attention callback sets to exit this loop, so this code allows the 
> eu thread to terminate after the sip shader is processed.
> 
> Br,
> G.G.
>>>       }
>>>       gpgpu_shader__eot(shader);
>>> @@ -217,6 +232,16 @@ static int count_set_bits(void *ptr, size_t size)
>>>       return count;
>>>   }
>>> +static int eu_attentions_xor_count(const uint32_t *a, const uint32_t 
>>> *b, uint32_t size)
>>> +{
>>> +    int count = 0;
>>> +
>>> +    for (int i = 0; i < size / 4 ; i++)
>>> +        count += igt_hweight(a[i] ^ b[i]);
>>> +
>>> +    return count;
>>> +}
>>> +
>>>   static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim, 
>>> uint32_t value)
>>>   {
>>>       int count = 0;
>>> @@ -636,7 +661,7 @@ static void eu_attention_resume_trigger(struct 
>>> xe_eudebug_debugger *d,
>>>           }
>>>       }
>>> -    if (d->flags & SHADER_LOOP) {
>>> +    if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
>>
>> If we drop the loop we can drop also this.
>>
>>>           uint32_t threads = get_number_of_threads(d->flags);
>>>           uint32_t val = STEERING_END_LOOP;
>>> @@ -746,6 +771,44 @@ static void 
>>> eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
>>>               data->single_step_bitmask[i] &= ~att->bitmask[i];
>>>   }
>>> +static void eu_attention_resume_pagefault_trigger(struct 
>>> xe_eudebug_debugger *d,
>>> +                          struct drm_xe_eudebug_event *e)
>>> +{
>>> +    struct drm_xe_eudebug_event_eu_attention *att = 
>>> igt_container_of(e, att, base);
>>> +    struct online_debug_data *data = d->ptr;
>>> +    uint32_t bitmask_size = att->bitmask_size;
>>> +    uint8_t *bitmask;
>>> +
>>> +    if (data->last_eu_control_seqno > att->base.seqno)
>>> +        return;
>>> +
>>> +    bitmask = calloc(1, att->bitmask_size);
>>> +    igt_assert(bitmask);
>>> +
>>> +    eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
>>> +               att->lrc_handle, bitmask, &bitmask_size);
>>> +    igt_assert(bitmask_size == att->bitmask_size);
>>> +
>>> +    pthread_mutex_lock(&data->mutex);
>>> +
>>> +    if (d->flags & SHADER_PAGEFAULT) {
>>> +        uint32_t threads = get_number_of_threads(d->flags);
>>> +        uint32_t val = STEERING_END_LOOP;
>>> +
>>> +        igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
>>> +                     data->target_offset + steering_offset(threads)),
>>> +                  sizeof(uint32_t));
>>> +        fsync(data->vm_fd);
>>> +    }
>>
>> We can also drop this when we remove the loop. Btw. why can't we just 
>> use 'eu_attention_resume_trigger' instead of this whole function?

We could remove the 'eu_attention_resume_trigger' like so:

```
diff --git a/tests/intel/xe_eudebug_online.c 
b/tests/intel/xe_eudebug_online.c
index a70d18ee4..c077795ee 100644
--- a/tests/intel/xe_eudebug_online.c
+++ b/tests/intel/xe_eudebug_online.c
@@ -622,7 +622,10 @@ static void eu_attention_resume_trigger(struct 
xe_eudebug_debugger *d,
  	eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
  		       att->lrc_handle, bitmask, &bitmask_size);
  	igt_assert(bitmask_size == att->bitmask_size);
-	igt_assert(memcmp(bitmask, att->bitmask, att->bitmask_size) == 0);
+
+	/* No guarantee that all pagefaulting eu threads will raise attention */
+	if (!(d->flags & SHADER_PAGEFAULT))
+		igt_assert(memcmp(bitmask, att->bitmask, att->bitmask_size) == 0);

  	pthread_mutex_lock(&data->mutex);
  	if (igt_nsec_elapsed(&data->exception_arrived) < (MAX_PREEMPT_TIMEOUT 
+ 1) * NSEC_PER_SEC &&
@@ -771,44 +774,6 @@ static void 
eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
  			data->single_step_bitmask[i] &= ~att->bitmask[i];
  }

-static void eu_attention_resume_pagefault_trigger(struct 
xe_eudebug_debugger *d,
-						  struct drm_xe_eudebug_event *e)
-{
-	struct drm_xe_eudebug_event_eu_attention *att = igt_container_of(e, 
att, base);
-	struct online_debug_data *data = d->ptr;
-	uint32_t bitmask_size = att->bitmask_size;
-	uint8_t *bitmask;
-
-	if (data->last_eu_control_seqno > att->base.seqno)
-		return;
-
-	bitmask = calloc(1, att->bitmask_size);
-	igt_assert(bitmask);
-
-	eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
-		       att->lrc_handle, bitmask, &bitmask_size);
-	igt_assert(bitmask_size == att->bitmask_size);
-
-	pthread_mutex_lock(&data->mutex);
-
-	if (d->flags & SHADER_PAGEFAULT) {
-		uint32_t threads = get_number_of_threads(d->flags);
-		uint32_t val = STEERING_END_LOOP;
-
-		igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
-				     data->target_offset + steering_offset(threads)),
-			      sizeof(uint32_t));
-		fsync(data->vm_fd);
-	}
-	pthread_mutex_unlock(&data->mutex);
-
-	data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, 
att->client_handle,
-						    att->exec_queue_handle, att->lrc_handle,
-						    bitmask, att->bitmask_size);
-
-	free(bitmask);
-}
-
  static void open_trigger(struct xe_eudebug_debugger *d,
  			 struct drm_xe_eudebug_event *e)
  {
@@ -1530,7 +1495,7 @@ static void test_pagefault_online(int fd, struct 
drm_xe_engine_class_instance *h
  	xe_eudebug_debugger_add_trigger(s->debugger, 
DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
  					eu_attention_debug_trigger);
  	xe_eudebug_debugger_add_trigger(s->debugger, 
DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
-					eu_attention_resume_pagefault_trigger);
+					eu_attention_resume_trigger);
  	xe_eudebug_debugger_add_trigger(s->debugger, DRM_XE_EUDEBUG_EVENT_VM, 
vm_open_trigger);
  	xe_eudebug_debugger_add_trigger(s->debugger, 
DRM_XE_EUDEBUG_EVENT_METADATA,
  					create_metadata_trigger);
```

Does this look reasonable? I know it adds yet another path to 
'eu_attention_resume_trigger' but you partially account for the 
pagefault shader in your current code anyway.

Thanks,
Christoph

>>
>>> +    pthread_mutex_unlock(&data->mutex);
>>> +
>>> +    data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, 
>>> att->client_handle,
>>> +                            att->exec_queue_handle, att->lrc_handle,
>>> +                            bitmask, att->bitmask_size);
>>> +
>>> +    free(bitmask);
>>> +}
>>> +
>>>   static void open_trigger(struct xe_eudebug_debugger *d,
>>>                struct drm_xe_eudebug_event *e)
>>>   {
>>> @@ -1015,7 +1078,7 @@ static void run_online_client(struct 
>>> xe_eudebug_client *c)
>>>       struct intel_bb *ibb;
>>>       struct intel_buf *buf;
>>>       uint32_t *ptr;
>>> -    int fd;
>>> +    int fd, vm_flags;
>>>       metadata[0] = calloc(2, sizeof(*metadata));
>>>       metadata[1] = calloc(2, sizeof(*metadata));
>>> @@ -1025,7 +1088,7 @@ static void run_online_client(struct 
>>> xe_eudebug_client *c)
>>>       fd = xe_eudebug_client_open_driver(c);
>>>       /* Additional memory for steering control */
>>> -    if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP)
>>> +    if (c->flags & SHADER_LOOP || c->flags & SHADER_SINGLE_STEP || 
>>> c- >flags & SHADER_PAGEFAULT)
>>>           s_dim.y++;
>>>       /* Additional memory for caching check */
>>>       if ((c->flags & SHADER_CACHING_SRAM) || (c->flags & 
>>> SHADER_CACHING_VRAM))
>>> @@ -1045,7 +1108,11 @@ static void run_online_client(struct 
>>> xe_eudebug_client *c)
>>>                                  DRM_XE_DEBUG_METADATA_PROGRAM_MODULE,
>>>                                  2 * sizeof(*metadata), metadata[1]);
>>> -    create.vm_id = xe_eudebug_client_vm_create(c, fd, 
>>> DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
>>> +    vm_flags = DRM_XE_VM_CREATE_FLAG_LR_MODE;
>>> +    vm_flags |= c->flags & SHADER_PAGEFAULT ? 
>>> DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0;
>>> +
>>> +    create.vm_id = xe_eudebug_client_vm_create(c, fd, vm_flags, 0);
>>> +
>>>       xe_eudebug_client_exec_queue_create(c, fd, &create);
>>>       ibb = xe_bb_create_on_offset(fd, create.exec_queue_id, 
>>> create.vm_id, bb_offset, bb_size,
>>> @@ -1245,11 +1312,13 @@ match_attention_with_exec_queue(struct 
>>> xe_eudebug_event_log *log,
>>>   static void online_session_check(struct xe_eudebug_session *s, int 
>>> flags)
>>>   {
>>>       struct drm_xe_eudebug_event_eu_attention *ea = NULL;
>>> +    struct drm_xe_eudebug_event_pagefault *pf = NULL;
>>>       struct drm_xe_eudebug_event *event = NULL;
>>>       struct online_debug_data *data = s->client->ptr;
>>>       bool expect_exception = flags & DISABLE_DEBUG_MODE ? false : true;
>>>       int sum = 0;
>>>       int bitmask_size;
>>> +    int pagefault_threads = 0;
>>>       xe_eudebug_session_check(s, true, 
>>> XE_EUDEBUG_FILTER_EVENT_VM_BIND |
>>>                         XE_EUDEBUG_FILTER_EVENT_VM_BIND_OP |
>>> @@ -1265,6 +1334,17 @@ static void online_session_check(struct 
>>> xe_eudebug_session *s, int flags)
>>>               igt_assert_eq(ea->bitmask_size, bitmask_size);
>>>               sum += count_set_bits(ea->bitmask, bitmask_size);
>>>               igt_assert(match_attention_with_exec_queue(s->debugger- 
>>> >log, ea));
>>> +        } else if (event->type == DRM_XE_EUDEBUG_EVENT_PAGEFAULT) {
>>> +            uint32_t after_offset = bitmask_size / sizeof(uint32_t);
>>> +            uint32_t resolved_offset = bitmask_size / 
>>> sizeof(uint32_t) * 2;
>>> +            uint32_t *ptr = NULL;
>>> +
>>> +            pf = igt_container_of(event, pf, base);
>>> +            ptr = (uint32_t *) pf->bitmask;
>>> +            igt_assert_eq(pf->bitmask_size, bitmask_size * 3);
>>> +            pagefault_threads += eu_attentions_xor_count(ptr + 
>>> after_offset,
>>> +                                     ptr + resolved_offset,
>>> +                                     bitmask_size);
>>>           }
>>>       }
>>> @@ -1279,6 +1359,9 @@ static void online_session_check(struct 
>>> xe_eudebug_session *s, int flags)
>>>           igt_assert(sum > 0);
>>>       else
>>>           igt_assert(sum == 0);
>>> +
>>> +    if (flags & SHADER_PAGEFAULT)
>>> +        igt_assert(pagefault_threads > 0);
>>>   }
>>>   static void ufence_ack_trigger(struct xe_eudebug_debugger *d,
>>> @@ -1302,6 +1385,43 @@ static void ufence_ack_set_bp_trigger(struct 
>>> xe_eudebug_debugger *d,
>>>       }
>>>   }
>>> +static void pagefault_trigger(struct xe_eudebug_debugger *d,
>>> +                  struct drm_xe_eudebug_event *e)
>>> +{
>>> +    struct drm_xe_eudebug_event_pagefault *pf = igt_container_of(e, 
>>> pf, base);
>>> +    uint32_t attn_size = pf->bitmask_size / 3;
>>> +    int attn_size_as_u32 = attn_size / sizeof(uint32_t);
>>> +    uint32_t *ptr = (uint32_t *) pf->bitmask;
>>> +    uint32_t *ptrs[3] = {ptr, ptr + attn_size_as_u32, ptr + 2 * 
>>> attn_size_as_u32};
>>> +    const char * const name[3] = {"before", "after", "resolved"};
>>> +    int threads[3], pagefault_threads, idx;
>>> +
>>> +    for (idx = 0; idx < 3; idx++)
>>> +        threads[idx] = count_set_bits(ptrs[idx], attn_size);
>>> +
>>> +    pagefault_threads = eu_attentions_xor_count(ptrs[1], ptrs[2], 
>>> attn_size);
>>> +
>>> +    igt_debug("EVENT[%llu] pagefault; threads[before=%d, after=%d, "
>>> +          "resolved=%d, pagefault=%d] "
>>> +          "client[%llu], exec_queue[%llu], lrc[%llu], 
>>> bitmask_size[%d], "
>>> +          "pagefault_address[0x%llx]\n",
>>> +          pf->base.seqno, threads[0], threads[1], threads[2],
>>> +          pagefault_threads, pf->client_handle, pf->exec_queue_handle,
>>> +          pf->lrc_handle, pf->bitmask_size,
>>> +          pf->pagefault_address);
>>> +
>>> +    for (idx = 0; idx < 3; idx++) {
>>> +        igt_debug("=== Attentions %s ===\n", name[idx]);
>>> +
>>> +        for (uint32_t i = 0; i < attn_size_as_u32; i += 2)
>>> +            igt_debug("bitmask[%d] = 0x%08x%08x\n", i / 2,
>>> +                  ptrs[idx][i], ptrs[idx][i + 1]);
>>> +    }
>>> +
>>> +    igt_assert(pagefault_threads > 0);
>>> +    igt_assert_eq_u64(pf->pagefault_address, BAD_OFFSET);
>>> +}
>>> +
>>>   /**
>>>    * SUBTEST: basic-breakpoint
>>>    * Description:
>>> @@ -1383,6 +1503,49 @@ static void test_set_breakpoint_online(int fd, 
>>> struct drm_xe_engine_class_instan
>>>       online_debug_data_destroy(data);
>>>   }
>>> +/**
>>> + * SUBTEST: pagefault-read
>>> + * Description:
>>> + *     Check whether KMD sends pagefault event for workload in debug 
>>> mode that
>>> + *     triggers a read pagefault.
>>> + *
>>> + * SUBTEST: pagefault-write
>>> + * Description:
>>> + *     Check whether KMD sends pagefault event for workload in debug 
>>> mode that
>>> + *     triggers a write pagefault.
>>> + */
>>> +static void test_pagefault_online(int fd, struct 
>>> drm_xe_engine_class_instance *hwe,
>>> +                  int flags)
>>> +{
>>> +    struct xe_eudebug_session *s;
>>> +    struct online_debug_data *data;
>>> +
>>> +    data = online_debug_data_create(hwe);
>>> +    s = xe_eudebug_session_create(fd, run_online_client, flags, data);
>>> +
>>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>>> DRM_XE_EUDEBUG_EVENT_OPEN,
>>> +                    open_trigger);
>>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>>> DRM_XE_EUDEBUG_EVENT_EXEC_QUEUE,
>>> +                    exec_queue_trigger);
>>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>>> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
>>> +                    eu_attention_debug_trigger);
>>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>>> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
>>> +                    eu_attention_resume_pagefault_trigger);
>>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>>> DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
>>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>>> DRM_XE_EUDEBUG_EVENT_METADATA,
>>> +                    create_metadata_trigger);
>>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>>> DRM_XE_EUDEBUG_EVENT_VM_BIND_UFENCE,
>>> +                    ufence_ack_trigger);
>>> +    xe_eudebug_debugger_add_trigger(s->debugger, 
>>> DRM_XE_EUDEBUG_EVENT_PAGEFAULT,
>>> +                    pagefault_trigger);
>>
>> Removing the loop would make it possible to reduce this to 3 triggers.
>>
>> So again, I may be missing some detail that implies we need a loop in 
>> the shader. But for now it looks to me like we don't.
>>
>> Thanks,
>> Christoph
>>
>>> +
>>> +    xe_eudebug_session_run(s);
>>> +    online_session_check(s, s->flags);
>>> +
>>> +    xe_eudebug_session_destroy(s);
>>> +    online_debug_data_destroy(data);
>>> +}
>>> +
>>>   /**
>>>    * SUBTEST: preempt-breakpoint
>>>    * Description:
>>> @@ -2344,6 +2507,11 @@ igt_main
>>>       igt_subtest("breakpoint-many-sessions-tiles")
>>>           test_many_sessions_on_tiles(fd, true);
>>> +    test_gt_render_or_compute("pagefault-read", fd, hwe)
>>> +        test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_READ);
>>> +    test_gt_render_or_compute("pagefault-write", fd, hwe)
>>> +        test_pagefault_online(fd, hwe, SHADER_PAGEFAULT_WRITE);
>>> +
>>>       igt_fixture {
>>>           xe_eudebug_enable(fd, was_enabled);
> 

Re: [PATCH i-g-t v2 1/4] lib/gppgu_shader: Add write D32 to ppgtt virtual address

[Hajda, Andrzej]

W dniu 22.11.2024 o 08:51, Gwan-gyeong Mun pisze:
>
>
> On 11/21/24 6:08 PM, Hajda, Andrzej wrote:
>>
>> W dniu 21.11.2024 o 13:22, Gwan-gyeong Mun pisze:
>>> From: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>>
>>> Create a function that adds the capabilty to write an dword size at 
>>> a given
>>> ppgtt address with a dword value. Use an Untyped 2D Block Array Store
>>> DataPort functionality of XE2+ with A64 flat addressing to direct 
>>> accessing
>>> an entire ppgtt address space.
>>>
>>> For the write to succeed, the given ppgtt virtual address has to be 
>>> bound.
>>> Otherwise a store page fault will be triggered.
>>>
>>> v2: Fix the function name to be more clear. (Andrzej)
>>>      Use lower_32_bits() / upper_32_bits() macro (Andrzej)
>>>      Drop unused code
>>>
>>> Suggested-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
>>> Co-developed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>>> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>> ---
>>>   lib/gpgpu_shader.c          | 94 
>>> +++++++++++++++++++++++++++++++++++++
>>>   lib/gpgpu_shader.h          |  2 +
>>>   lib/iga64_generated_codes.c | 23 ++++++++-
>>>   3 files changed, 118 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
>>> index 4e1b8d5e9..d9da35895 100644
>>> --- a/lib/gpgpu_shader.c
>>> +++ b/lib/gpgpu_shader.c
>>> @@ -803,3 +803,97 @@ void 
>>> gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
>>>       ", 0x807fffff, /* leave breakpoint exception */
>>>       y_offset, value, 0x7fffff /* clear all exceptions */ );
>>>   }
>>> +
>>> +/**
>>> + * gpgpu_shader__write_a64_dword:
>>> + * @shdr: shader to be modified
>>> + * @ppgtt_addr: write target ppgtt virtual address
>>> + * @value: dword to be written
>>> + *
>>> + * Write one D32 data (DW; DoubleWord) directly to the target ppgtt 
>>> virtual
>>> + * address (A64 Flat Address model).
>>> + *
>>> + * Note: for the write to succeed, the address specified by 
>>> @ppgtt_addr has
>>> + * to be bound. Otherwise a store page fault will be triggered.
>>> + */
>>> +void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, 
>>> uint64_t ppgtt_addr,
>>> +                   uint32_t value)
>>
>>
>> Nice name, could be even gpgpu_shader__write_a64_d32, to follow spec 
>> convention.
>>
> Ok, will update.
>>
>>> +{
>>> +    uint64_t addr = CANONICAL(ppgtt_addr);
>>> +    igt_assert_f((addr & 0x3) == 0, "address must be aligned to 
>>> DWord!\n");
>>> +
>>> +    emit_iga64_code(shdr, write_a64_dword, " \n\
>>> +#if GEN_VER >= 2000                                \n\
>>> +// Unyped 2D Block Store                            \n\
>>> +// Instruction_Store2DBlock                            \n\
>>> +// bspec: 63981                                    \n\
>>> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies 
>>> both        \n\
>>> +//    the block parameters and the 2D Surface 
>>> parameters.            \n\
>>> +// src1 data payload format is selected by Data 
>>> Size.                \n\
>>> +// Untyped2DBLOCKAddressPayload \n\
>>> +// bspec: 63986                                    \n\
>>> +// [243:240] Array Length: 0 (length is 1) \n\
>>> +// [239:232] Block Height: 0 (height is 1) \n\
>>> +// [231:224] Block Width: 0xf (width is 16)                    \n\
>>> +// [223:192] Block Start Y: 0                            \n\
>>> +// [191:160] Block Start X: 0                            \n\
>>> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 
>>> bytes)            \n\
>>> +// [127:96] Untyped 2D Surface Height: 0 (height is 
>>> 1)                \n\
>>> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 
>>> bytes)            \n\
>>> +// [63:0] Untyped 2D Surface Base Address \n\
>>> +// initialize register                                \n\
>>> +(W)    mov (8)            r30.0<1>:uq 0x0:uq                \n\
>>> +// [0:31] Untyped 2D Surface Base Address low                    \n\
>>> +(W)    mov (1)            r30.0<1>:ud ARG(0):ud            \n\
>>> +// [32:63] Untyped 2D Surface Base Address high                    \n\
>>> +(W)    mov (1)            r30.1<1>:ud ARG(1):ud                \n\
>>> +// [95:64] Untyped 2D Surface Width: 0x3f \n\
>>> +//       (Width minus 1 (in bytes) of the 2D surface, it represents 
>>> 64)    \n\
>>> +(W)    mov (1)         r30.2<1>:ud 0x3f:ud                \n\
>>> +// [127:96] Untyped 2D Surface Height: 0x0 \n\
>>> +//        (Height minus 1 (in number of data elements) 
>>> of            \n\
>>> +//        the Untyped 2D surface, it represents 1)                \n\
>>> +(W)    mov (1)         r30.3<1>:ud 0x0:ud                \n\
>>> +// [159:128] Untyped 2D Surface Pitch: 0x3f                    \n\
>>> +//         (Pitch minus 1 (in bytes) of the 2D surface, it 
>>> represents 64)    \n\
>>> +(W)    mov (1)            r30.4<1>:ud 0x3f:ud                \n\
>>> +// [231:224] Block Width: 0xf (15)                        \n\
>>> +//         (Specifies the width minus 1 (in number of data 
>>> elements) for this    \n\
>>> +//         rectangular region, it represents 16)                \n\
>>> +// Block width (encoded_value + 1) must be a multiple of DW (4 
>>> bytes).        \n\
>>> +// [239:232] Block Height: 0                            \n\
>>> +//         (Specifies the height minus 1 (in number of data 
>>> elements) for    \n\
>>> +//         this rectangular region, it represents 1)                
>>> \n\
>>> +// [243:240] Array Length: 0                            \n\
>>> +//         (Specifies Array Length minus 1 for Load2DBlockArray 
>>> messages,    \n\
>>> +//         must be zero for 2D Block Store messages, it represents 
>>> 1)        \n\
>>> +(W)    mov (1)            r30.7<1>:ud 0xf:ud                \n\
>>
>>
>> Shouldn't this be 0x3:ud now, for dword ?
>>
> No, r30.7 needs to set 0xf:ud.


0xf mean block width is 16 bytes, it means 4 dwords, in the description 
you says one d32,

to source register r31 you enter also d32, and zeroes the rest.

So what is going here? Writing one dword, or 4dwords (one provided, and 
the rest 0) ?


Regards

Andrzej


>
> please refer the Structure_Untyped2DBLOCKAddressPayload: bspec 63986
>
> [31:0]    => r30.0:ud  <= [0:31] Untyped 2D Surface Base Address low
> [63:32]   => r30.1:ud  <= [32:63] Untyped 2D Surface Base Address high
> [95:64]   => r30.2:ud  <= [95:64] Untyped 2D Surface Width: 0x3f
> [127:96]  => r30.3:ud  <= [127:96] Untyped 2D Surface Height: 0
> [159:128] => r30.4:ud  <= [159:128] Untyped 2D Surface Pitch: 0x3f
> [191:160] => r30.5:ud  <= [191:160] Block Start X: 0
> [223:192] => r30.6:ud  <= [223:192] Block Start Y: 0
> [251:224] => r30.7:ud  <= [231:224] Block Width: 0xf
>                           [239:232] Block Height: 0
>                           [243:240] Array Length: 0
>                           ; 0xf
>
> br,
>
> G.G.
>> Beside those details:
>>
>> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
>>
>> Regards
>> Andrzej
>>
>>> +// src1 data payload size                            \n\
>>> +// Block Height x Block Width x Data size / GRF Register 
>>> size            \n\
>>> +//    => 1 x 16 x 32bit / 512bit = 1                        \n\
>>> +// data payload size is 1                            \n\
>>> +(W)    mov (8)            r31.0<1>:uq 0x0:uq                \n\
>>> +(W)    mov (1|M0)        r31.0<1>:ud ARG(2):ud            \n\
>>> +// send.ugm Untyped 2D Block Array Store \n\
>>> +// Format: send.ugm (1) dst src0 src1 ExtMsg MsgDesc                
>>> \n\
>>> +// Execution Mask restriction: SIMT1 \n\
>>> +//                                        \n\
>>> +// Extended Message Descriptor (Dataport Extended Descriptor Imm 2D 
>>> Block)    \n\
>>> +// bspec: 67780                                    \n\
>>> +// 0x0 =>                                    \n\
>>> +// [32:22] Global Y_offset: 0                            \n\
>>> +// [21:12] Global X_offset: 0                            \n\
>>> +//                                        \n\
>>> +// Message Descriptor                                \n\
>>> +// bspec: 63981                                    \n\
>>> +// 0x2020407 =>                                    \n\
>>> +// [30:29] Address Type: 0 (FLAT)                        \n\
>>> +// [28:25] Src0 Length: 1                            \n\
>>> +// [24:20] Dest Length: 0                            \n\
>>> +// [19:16] Cache : 2 (L1UC_L3UC)                        \n\
>>> +// [11:9] Data Size: 2 (D32)                            \n\
>>> +// [5:0] Store Operation: 7                            \n\
>>> +(W)    send.ugm (1)        null    r30    r31:1    0x0 0x2020407    
>>> \n\
>>> +#endif                                        \n\
>>> +    ", lower_32_bits(addr), upper_32_bits(addr), value);
>>> +}
>>> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
>>> index c7c21c115..18a4c9725 100644
>>> --- a/lib/gpgpu_shader.h
>>> +++ b/lib/gpgpu_shader.h
>>> @@ -85,6 +85,8 @@ void gpgpu_shader__write_dword(struct gpgpu_shader 
>>> *shdr, uint32_t value,
>>>                      uint32_t y_offset);
>>>   void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, 
>>> uint32_t dw, uint32_t x_offset,
>>>                         uint32_t y_offset, uint32_t mask, uint32_t 
>>> value);
>>> +void gpgpu_shader__write_a64_dword(struct gpgpu_shader *shdr, 
>>> uint64_t ppgtt_addr,
>>> +                   uint32_t value);
>>>   void gpgpu_shader__label(struct gpgpu_shader *shdr, int label_id);
>>>   void gpgpu_shader__jump(struct gpgpu_shader *shdr, int label_id);
>>>   void gpgpu_shader__jump_neq(struct gpgpu_shader *shdr, int label_id,
>>> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
>>> index 6638be07b..e97bcf042 100644
>>> --- a/lib/iga64_generated_codes.c
>>> +++ b/lib/iga64_generated_codes.c
>>> @@ -3,7 +3,7 @@
>>>   #include "gpgpu_shader.h"
>>> -#define MD5_SUM_IGA64_ASMS ec9d477415eebb7d6983395f1bcde78f
>>> +#define MD5_SUM_IGA64_ASMS a1ee0173014ab4cda3090faeca1cbae1
>>>   struct iga64_template const iga64_code_gpgpu_fill[] = {
>>>       { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>>> @@ -79,6 +79,27 @@ struct iga64_template const 
>>> iga64_code_gpgpu_fill[] = {
>>>       }}
>>>   };
>>> +struct iga64_template const iga64_code_write_a64_dword[] = {
>>> +    { .gen_ver = 2000, .size = 52, .code = (const uint32_t []) {
>>> +        0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
>>> +        0x80000061, 0x1e054220, 0x00000000, 0xc0ded000,
>>> +        0x80000061, 0x1e154220, 0x00000000, 0xc0ded001,
>>> +        0x80000061, 0x1e254220, 0x00000000, 0x0000003f,
>>> +        0x80000061, 0x1e354220, 0x00000000, 0x00000000,
>>> +        0x80000061, 0x1e454220, 0x00000000, 0x0000003f,
>>> +        0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
>>> +        0x800c0061, 0x1f054330, 0x00000000, 0x00000000,
>>> +        0x80000061, 0x1f054220, 0x00000000, 0xc0ded002,
>>> +        0x80032031, 0x00000000, 0xf80e1e0c, 0x00801f0c,
>>> +        0x80000001, 0x00010000, 0x20000000, 0x00000000,
>>> +        0x80000001, 0x00010000, 0x30000000, 0x00000000,
>>> +        0x80000901, 0x00010000, 0x00000000, 0x00000000,
>>> +    }},
>>> +    { .gen_ver = 0, .size = 0, .code = (const uint32_t []) {
>>> +
>>> +    }}
>>> +};
>>> +
>>>   struct iga64_template const 
>>> iga64_code_end_system_routine_step_if_eq[] = {
>>>       { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>>>           0x80000966, 0x80018220, 0x02008000, 0x00008000,
>

Re: [PATCH i-g-t v2 1/4] lib/gppgu_shader: Add write D32 to ppgtt virtual address

[Gwan-gyeong Mun]

On 11/22/24 12:47 PM, Hajda, Andrzej wrote:
> 
>>>> +{
>>>> +    uint64_t addr = CANONICAL(ppgtt_addr);
>>>> +    igt_assert_f((addr & 0x3) == 0, "address must be aligned to 
>>>> DWord!\n");
>>>> +
>>>> +    emit_iga64_code(shdr, write_a64_dword, " \n\
>>>> +#if GEN_VER >= 2000                                \n\
>>>> +// Unyped 2D Block Store                            \n\
>>>> +// Instruction_Store2DBlock                            \n\
>>>> +// bspec: 63981                                    \n\
>>>> +// src0 address payload (Untyped2DBLOCKAddressPayload) specifies 
>>>> both        \n\
>>>> +//    the block parameters and the 2D Surface 
>>>> parameters.            \n\
>>>> +// src1 data payload format is selected by Data 
>>>> Size.                \n\
>>>> +// Untyped2DBLOCKAddressPayload \n\
>>>> +// bspec: 63986                                    \n\
>>>> +// [243:240] Array Length: 0 (length is 1) \n\
>>>> +// [239:232] Block Height: 0 (height is 1) \n\
>>>> +// [231:224] Block Width: 0xf (width is 16)                    \n\
>>>> +// [223:192] Block Start Y: 0                            \n\
>>>> +// [191:160] Block Start X: 0                            \n\
>>>> +// [159:128] Untyped 2D Surface Pitch: 0x3f (pitch is 64 
>>>> bytes)            \n\
>>>> +// [127:96] Untyped 2D Surface Height: 0 (height is 
>>>> 1)                \n\
>>>> +// [95:64] Untyped 2D Surface Width: 0x3f (width is 64 
>>>> bytes)            \n\
>>>> +// [63:0] Untyped 2D Surface Base Address \n\
>>>> +// initialize register                                \n\
>>>> +(W)    mov (8)            r30.0<1>:uq 0x0:uq                \n\
>>>> +// [0:31] Untyped 2D Surface Base Address low                    \n\
>>>> +(W)    mov (1)            r30.0<1>:ud ARG(0):ud            \n\
>>>> +// [32:63] Untyped 2D Surface Base Address high                    \n\
>>>> +(W)    mov (1)            r30.1<1>:ud ARG(1):ud                \n\
>>>> +// [95:64] Untyped 2D Surface Width: 0x3f \n\
>>>> +//       (Width minus 1 (in bytes) of the 2D surface, it represents 
>>>> 64)    \n\
>>>> +(W)    mov (1)         r30.2<1>:ud 0x3f:ud                \n\
>>>> +// [127:96] Untyped 2D Surface Height: 0x0 \n\
>>>> +//        (Height minus 1 (in number of data elements) 
>>>> of            \n\
>>>> +//        the Untyped 2D surface, it represents 1)                \n\
>>>> +(W)    mov (1)         r30.3<1>:ud 0x0:ud                \n\
>>>> +// [159:128] Untyped 2D Surface Pitch: 0x3f                    \n\
>>>> +//         (Pitch minus 1 (in bytes) of the 2D surface, it 
>>>> represents 64)    \n\
>>>> +(W)    mov (1)            r30.4<1>:ud 0x3f:ud                \n\
>>>> +// [231:224] Block Width: 0xf (15)                        \n\
>>>> +//         (Specifies the width minus 1 (in number of data 
>>>> elements) for this    \n\
>>>> +//         rectangular region, it represents 16)                \n\
>>>> +// Block width (encoded_value + 1) must be a multiple of DW (4 
>>>> bytes).        \n\
>>>> +// [239:232] Block Height: 0                            \n\
>>>> +//         (Specifies the height minus 1 (in number of data 
>>>> elements) for    \n\
>>>> +//         this rectangular region, it represents 1) \n\
>>>> +// [243:240] Array Length: 0                            \n\
>>>> +//         (Specifies Array Length minus 1 for Load2DBlockArray 
>>>> messages,    \n\
>>>> +//         must be zero for 2D Block Store messages, it represents 
>>>> 1)        \n\
>>>> +(W)    mov (1)            r30.7<1>:ud 0xf:ud                \n\
>>>
>>>
>>> Shouldn't this be 0x3:ud now, for dword ?
>>>
>> No, r30.7 needs to set 0xf:ud.
> 
> 
> 0xf mean block width is 16 bytes, it means 4 dwords, in the description 
> you says one d32,
> 
> to source register r31 you enter also d32, and zeroes the rest.
> 
> So what is going here? Writing one dword, or 4dwords (one provided, and 
> the rest 0) ?
> 
Good catch.
Yes it should be changed to use 1 dword from 4dwords as you commented.
I'll update both read and write functions.

Thanks!

G.G.

Re: [PATCH i-g-t v2 4/4] tests/intel/xe_eudebug_online: Add read/write pagefault online tests

[Gwan-gyeong Mun]

On 11/22/24 11:55 AM, Manszewski, Christoph wrote:
> Hi Gwan-gyeong,
> 
> On 22.11.2024 09:21, Gwan-gyeong Mun wrote:
>>
>>
>> On 11/21/24 7:12 PM, Manszewski, Christoph wrote:
>>> Hi Gwan-gyeong,
>>>
>>> On 21.11.2024 13:22, Gwan-gyeong Mun wrote:
>>>> Add read and write pagefault tests to xe_eudebug_online that checks 
>>>> if a
>>>> pagefault event is submitted by the KMD debugger when a pagefault 
>>>> occurs.
>>>>
>>>> Test that read (load instruction) and write(store instruction) 
>>>> attempt to
>>>> load or store access to unallocated memory, causing a pagefault.
>>>> Examine the address causing the page fault and the number of eu threads
>>>> causing the pagefault.
>>>>
>>>> v2: Refactor of output attention bits on pagefault event handling 
>>>> (Andrzej)
>>>>      remove / update redudant code (Andrzej, Christoph)
>>>>      use igt_container_of() macro (Christoph)
>>>>
>>>> Co-developed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>>>> ---
>>>>   tests/intel/xe_eudebug_online.c | 178 ++++++++++++++++++++++++++++ 
>>>> +++-
>>>>   1 file changed, 173 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/ 
>>>> xe_eudebug_online.c
>>>> index 0ef0d8093..a70d18ee4 100644
>>>> --- a/tests/intel/xe_eudebug_online.c
>>>> +++ b/tests/intel/xe_eudebug_online.c
>>>> @@ -36,6 +36,8 @@
>>>>   #define BB_IN_VRAM            (1 << 11)
>>>>   #define TARGET_IN_SRAM            (1 << 12)
>>>>   #define TARGET_IN_VRAM            (1 << 13)
>>>> +#define SHADER_PAGEFAULT_READ        (1 << 14)
>>>> +#define SHADER_PAGEFAULT_WRITE        (1 << 15)
>>>>   #define TRIGGER_UFENCE_SET_BREAKPOINT    (1 << 24)
>>>>   #define TRIGGER_RESUME_SINGLE_WALK    (1 << 25)
>>>>   #define TRIGGER_RESUME_PARALLEL_WALK    (1 << 26)
>>>> @@ -45,6 +47,7 @@
>>>>   #define TRIGGER_RESUME_DSS        (1 << 30)
>>>>   #define TRIGGER_RESUME_ONE        (1 << 31)
>>>> +#define SHADER_PAGEFAULT    (SHADER_PAGEFAULT_READ | 
>>>> SHADER_PAGEFAULT_WRITE)
>>>>   #define BB_REGION_BITMASK    (BB_IN_SRAM | BB_IN_VRAM)
>>>>   #define TARGET_REGION_BITMASK    (TARGET_IN_SRAM | TARGET_IN_VRAM)
>>>> @@ -61,6 +64,8 @@
>>>>   #define CACHING_VALUE(n)    (CACHING_INIT_VALUE + (n))
>>>>   #define SHADER_CANARY 0x01010101
>>>> +#define BAD_CANARY 0xf1f1f1f
>>>> +#define BAD_OFFSET (0x12345678ull << 12)
>>>>   #define WALKER_X_DIM        4
>>>>   #define WALKER_ALIGNMENT    16
>>>> @@ -120,7 +125,7 @@ static struct intel_buf *create_uc_buf(int fd, 
>>>> int width, int height, uint64_t r
>>>>   static int get_number_of_threads(uint64_t flags)
>>>>   {
>>>> -    if (flags & SHADER_MIN_THREADS)
>>>> +    if (flags & (SHADER_MIN_THREADS | SHADER_PAGEFAULT))
>>>>           return 16;
>>>>       if (flags & (TRIGGER_RESUME_ONE | TRIGGER_RESUME_SINGLE_WALK |
>>>> @@ -179,6 +184,16 @@ static struct gpgpu_shader *get_shader(int fd, 
>>>> const unsigned int flags)
>>>>               gpgpu_shader__common_target_write_u32(shader, s_dim.y 
>>>> + i, CACHING_VALUE(i));
>>>>           gpgpu_shader__nop(shader);
>>>>           gpgpu_shader__breakpoint(shader);
>>>> +    } else if (flags & SHADER_PAGEFAULT) {
>>>> +        if (flags & SHADER_PAGEFAULT_READ)
>>>> +            gpgpu_shader__read_a64_dword(shader, BAD_OFFSET);
>>>> +        else
>>>> +            gpgpu_shader__write_a64_dword(shader, BAD_OFFSET, 
>>>> BAD_CANARY);
>>>> +
>>>> +        gpgpu_shader__label(shader, 0);
>>>> +        gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>>>> +        gpgpu_shader__jump_neq(shader, 0, w_dim.y, STEERING_END_LOOP);
>>>> +        gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>>>
>>> Now that I think about - do we need this to be a loop? Can't we just 
>>> do the read/write instructions? This would simplify the code and I 
>>> don't yet see why we need to loop within the shader. The SHADER_LOOP 
>>> is used for interrupt-all because we want to interrupt the workload 
>>> from the user/main igt thread. But here, similar to the basic- 
>>> breakpoint test, we just submit a workload that will halt because of 
>>> the hardware/kmd intervention.
>>>
>> the pagefault tests also need this concept.
>>
>> When a pagefault happened, KMD sets “Force Exception / Force External 
>> Halt” in TD_CTL to cause the eu threads to enter SIP mode.
>> In the pagefault handling process of eudebug, kmd installs a null page 
>> at the address where the pagefault happened and makes the halted eu 
>> threads resume (make unhalt).
>>
>> It would be ideal if all unhalted eu threads immediately entered SIP 
>> mode due to the FE/FEH settings, but it may not happen immediately.
>> Therefore, the purpose of using a loop is to ensure that the kernel 
>> shader does not terminate until a pagefault event and attention event 
>> occur by adding an additional instruction after the instruction that 
>> causes the page fault.
>> Therefore, a loop is used to ensure that at least one eu thread must 
>> enter SIP mode.
> 
> Yeah if the count of processed instructions before the exception is not 
> defined then indeed the loop has it's place here. But we still may 
> reduce a little bit of code, see below.
> 
>> The attention callback sets to exit this loop, so this code allows the 
>> eu thread to terminate after the sip shader is processed.
>>
>> Br,
>> G.G.
>>>>       }
>>>>       gpgpu_shader__eot(shader);
>>>> @@ -217,6 +232,16 @@ static int count_set_bits(void *ptr, size_t size)
>>>>       return count;
>>>>   }
>>>> +static int eu_attentions_xor_count(const uint32_t *a, const 
>>>> uint32_t *b, uint32_t size)
>>>> +{
>>>> +    int count = 0;
>>>> +
>>>> +    for (int i = 0; i < size / 4 ; i++)
>>>> +        count += igt_hweight(a[i] ^ b[i]);
>>>> +
>>>> +    return count;
>>>> +}
>>>> +
>>>>   static int count_canaries_eq(uint32_t *ptr, struct dim_t w_dim, 
>>>> uint32_t value)
>>>>   {
>>>>       int count = 0;
>>>> @@ -636,7 +661,7 @@ static void eu_attention_resume_trigger(struct 
>>>> xe_eudebug_debugger *d,
>>>>           }
>>>>       }
>>>> -    if (d->flags & SHADER_LOOP) {
>>>> +    if (d->flags & (SHADER_LOOP | SHADER_PAGEFAULT)) {
>>>
>>> If we drop the loop we can drop also this.
>>>
>>>>           uint32_t threads = get_number_of_threads(d->flags);
>>>>           uint32_t val = STEERING_END_LOOP;
>>>> @@ -746,6 +771,44 @@ static void 
>>>> eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
>>>>               data->single_step_bitmask[i] &= ~att->bitmask[i];
>>>>   }
>>>> +static void eu_attention_resume_pagefault_trigger(struct 
>>>> xe_eudebug_debugger *d,
>>>> +                          struct drm_xe_eudebug_event *e)
>>>> +{
>>>> +    struct drm_xe_eudebug_event_eu_attention *att = 
>>>> igt_container_of(e, att, base);
>>>> +    struct online_debug_data *data = d->ptr;
>>>> +    uint32_t bitmask_size = att->bitmask_size;
>>>> +    uint8_t *bitmask;
>>>> +
>>>> +    if (data->last_eu_control_seqno > att->base.seqno)
>>>> +        return;
>>>> +
>>>> +    bitmask = calloc(1, att->bitmask_size);
>>>> +    igt_assert(bitmask);
>>>> +
>>>> +    eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
>>>> +               att->lrc_handle, bitmask, &bitmask_size);
>>>> +    igt_assert(bitmask_size == att->bitmask_size);
>>>> +
>>>> +    pthread_mutex_lock(&data->mutex);
>>>> +
>>>> +    if (d->flags & SHADER_PAGEFAULT) {
>>>> +        uint32_t threads = get_number_of_threads(d->flags);
>>>> +        uint32_t val = STEERING_END_LOOP;
>>>> +
>>>> +        igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
>>>> +                     data->target_offset + steering_offset(threads)),
>>>> +                  sizeof(uint32_t));
>>>> +        fsync(data->vm_fd);
>>>> +    }
>>>
>>> We can also drop this when we remove the loop. Btw. why can't we just 
>>> use 'eu_attention_resume_trigger' instead of this whole function?
> 
> We could remove the 'eu_attention_resume_trigger' like so:
> 
> ```
> diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/ 
> xe_eudebug_online.c
> index a70d18ee4..c077795ee 100644
> --- a/tests/intel/xe_eudebug_online.c
> +++ b/tests/intel/xe_eudebug_online.c
> @@ -622,7 +622,10 @@ static void eu_attention_resume_trigger(struct 
> xe_eudebug_debugger *d,
>       eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
>                  att->lrc_handle, bitmask, &bitmask_size);
>       igt_assert(bitmask_size == att->bitmask_size);
> -    igt_assert(memcmp(bitmask, att->bitmask, att->bitmask_size) == 0);
> +
> +    /* No guarantee that all pagefaulting eu threads will raise 
> attention */
> +    if (!(d->flags & SHADER_PAGEFAULT))
> +        igt_assert(memcmp(bitmask, att->bitmask, att->bitmask_size) == 0);
> 
>       pthread_mutex_lock(&data->mutex);
>       if (igt_nsec_elapsed(&data->exception_arrived) < 
> (MAX_PREEMPT_TIMEOUT + 1) * NSEC_PER_SEC &&
> @@ -771,44 +774,6 @@ static void 
> eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
>               data->single_step_bitmask[i] &= ~att->bitmask[i];
>   }
> 
> -static void eu_attention_resume_pagefault_trigger(struct 
> xe_eudebug_debugger *d,
> -                          struct drm_xe_eudebug_event *e)
> -{
> -    struct drm_xe_eudebug_event_eu_attention *att = igt_container_of(e, 
> att, base);
> -    struct online_debug_data *data = d->ptr;
> -    uint32_t bitmask_size = att->bitmask_size;
> -    uint8_t *bitmask;
> -
> -    if (data->last_eu_control_seqno > att->base.seqno)
> -        return;
> -
> -    bitmask = calloc(1, att->bitmask_size);
> -    igt_assert(bitmask);
> -
> -    eu_ctl_stopped(d->fd, att->client_handle, att->exec_queue_handle,
> -               att->lrc_handle, bitmask, &bitmask_size);
> -    igt_assert(bitmask_size == att->bitmask_size);
> -
> -    pthread_mutex_lock(&data->mutex);
> -
> -    if (d->flags & SHADER_PAGEFAULT) {
> -        uint32_t threads = get_number_of_threads(d->flags);
> -        uint32_t val = STEERING_END_LOOP;
> -
> -        igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
> -                     data->target_offset + steering_offset(threads)),
> -                  sizeof(uint32_t));
> -        fsync(data->vm_fd);
> -    }
> -    pthread_mutex_unlock(&data->mutex);
> -
> -    data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, 
> att->client_handle,
> -                            att->exec_queue_handle, att->lrc_handle,
> -                            bitmask, att->bitmask_size);
> -
> -    free(bitmask);
> -}
> -
>   static void open_trigger(struct xe_eudebug_debugger *d,
>                struct drm_xe_eudebug_event *e)
>   {
> @@ -1530,7 +1495,7 @@ static void test_pagefault_online(int fd, struct 
> drm_xe_engine_class_instance *h
>       xe_eudebug_debugger_add_trigger(s->debugger, 
> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
>                       eu_attention_debug_trigger);
>       xe_eudebug_debugger_add_trigger(s->debugger, 
> DRM_XE_EUDEBUG_EVENT_EU_ATTENTION,
> -                    eu_attention_resume_pagefault_trigger);
> +                    eu_attention_resume_trigger);
>       xe_eudebug_debugger_add_trigger(s->debugger, 
> DRM_XE_EUDEBUG_EVENT_VM, vm_open_trigger);
>       xe_eudebug_debugger_add_trigger(s->debugger, 
> DRM_XE_EUDEBUG_EVENT_METADATA,
>                       create_metadata_trigger);
> ```
> 
> Does this look reasonable? I know it adds yet another path to 
> 'eu_attention_resume_trigger' but you partially account for the 
> pagefault shader in your current code anyway.
> 
Yes, right, I added a separate callback (for readability) because I 
didn't need the non-pagefault scenario checking routine of the attention 
callback.
In order to keep the code additions in this patch as small as possible, 
I'll integrate to handle pagefault scenario in 
eu_attention_resume_trigger() callback, as you suggested.

Thanks,
G.G.

> Thanks,
> Christoph
>