[PATCH v2 00/19] Multi Queue feature validation support

[PATCH v2 00/19] Multi Queue feature validation support

[Niranjana Vishwanathapura]

Multi Queue is a new mode of execution supported by the compute and
blitter copy command streamers (CCS and BCS, respectively). It is an
enhancement of the existing hardware architecture and leverages the
same submission model. It enables support for efficient, parallel
execution of multiple queues within a single context.

Add validation support for multi-queue feature.

This requires XeKMD multi-queue support posted here,
https://patchwork.freedesktop.org/series/156865/

Changes in v2:
- Update xe_exec_queue_property@invalid-property test
- Use macro instead of hardcoding
- Use proper macro and variable names
- Remove simulation related code
- Ensure virtual test runs with single engine instance

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>

Nakshtra Goyal (1):
  tests/intel/xe_exec_multi_queue: Add fault mode test

Niranjana Vishwanathapura (16):
  drm-uapi/xe: Sync with Multi-Queue uapi
  tests/intel/xe_exec_multi_queue: Add xe_exec_multi_queue test
  tests/intel/xe_exec_multi_queue: Validate exec submissions
  tests/intel/xe_exec_multi_queue: Validate queue priority setting
  tests/intel/xe_exec_multi_queue: Add close-fd tests
  tests/intel/xe_exec_multi_queue: Add multiple placement test
  tests/intel/xe_exec_multi_queue: Add preempt mode test
  lib/xe: Add exec_queue set_property ioctl support
  tests/intel/xe_exec_multi_queue: Add dynamic priority test
  tests/intel/xe_exec_multi_queue: Add userptr invalidation tests
  lib/xe/xe_spin: Add switch point for preemptible spinner
  tests/intel/xe_exec_multi_queue: Add priority test
  tests/intel/xe_exec_multi_queue: Add submission sanity test
  tests/intel/xe_exec_multi_queue: Sanity test KEEP_ACTIVE flag
  tests/intel/xe_exec_multi_queue: Keep group active in exec-sanity
  tests/intel/xe_exec_queue_property: Update invalid-property test

Nishit Sharma (1):
  lib/xe: Add multi-queue helper routines

Priyanka Dandamudi (1):
  tests/intel/xe_exec_multi_queue: Add multi queues with SMEM

 include/drm-uapi/xe_drm.h            |   40 +
 include/intel_gpu_commands.h         |    1 +
 lib/xe/xe_ioctl.c                    |   27 +
 lib/xe/xe_ioctl.h                    |    4 +
 lib/xe/xe_query.c                    |   22 +
 lib/xe/xe_query.h                    |    8 +
 lib/xe/xe_spin.c                     |   41 +
 lib/xe/xe_spin.h                     |    3 +
 tests/intel/xe_exec_multi_queue.c    | 1128 ++++++++++++++++++++++++++
 tests/intel/xe_exec_queue_property.c |    2 +-
 tests/meson.build                    |    1 +
 11 files changed, 1276 insertions(+), 1 deletion(-)
 create mode 100644 tests/intel/xe_exec_multi_queue.c

-- 
2.43.0

[PATCH v2 01/19] drm-uapi/xe: Sync with Multi-Queue uapi

[Niranjana Vishwanathapura]

Sync kernel header to get Multi-Queue uapi definitions.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 include/drm-uapi/xe_drm.h | 40 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 89ab54935..d1cb08dc7 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -106,6 +106,7 @@ extern "C" {
 #define DRM_XE_OBSERVATION		0x0b
 #define DRM_XE_MADVISE			0x0c
 #define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS	0x0d
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY	0x0e
 
 /* Must be kept compact -- no holes */
 
@@ -123,6 +124,7 @@ extern "C" {
 #define DRM_IOCTL_XE_OBSERVATION		DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param)
 #define DRM_IOCTL_XE_MADVISE			DRM_IOW(DRM_COMMAND_BASE + DRM_XE_MADVISE, struct drm_xe_madvise)
 #define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS	DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr)
+#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY	DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
 
 /**
  * DOC: Xe IOCTL Extensions
@@ -1233,6 +1235,18 @@ struct drm_xe_vm_bind {
  *    Given that going into a power-saving state kills PXP HWDRM sessions,
  *    runtime PM will be blocked while queues of this type are alive.
  *    All PXP queues will be killed if a PXP invalidation event occurs.
+ *  - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP - Create a multi-queue group
+ *    or add secondary queues to a multi-queue group.
+ *    If the extension's 'value' field has %DRM_XE_MULTI_GROUP_CREATE flag set,
+ *    then a new multi-queue group is created with this queue as the primary queue
+ *    (Q0). Otherwise, the queue gets added to the multi-queue group whose primary
+ *    queue id is specified in the 'value' field.
+ *    If the extension's 'value' field has %DRM_XE_MULTI_GROUP_KEEP_ACTIVE flag
+ *    set, then the multi-queue group is kept active after the primary queue is
+ *    destroyed.
+ *
+ *  - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set the queue
+ *    priority within the multi-queue group.
  *
  * The example below shows how to use @drm_xe_exec_queue_create to create
  * a simple exec_queue (no parallel submission) of class
@@ -1273,6 +1287,10 @@ struct drm_xe_exec_queue_create {
 #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY		0
 #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE		1
 #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE		2
+#define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP		3
+#define     DRM_XE_MULTI_GROUP_CREATE				(1ull << 63)
+#define     DRM_XE_MULTI_GROUP_KEEP_ACTIVE			(1ull << 62)
+#define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY	4
 	/** @extensions: Pointer to the first extension struct, if any */
 	__u64 extensions;
 
@@ -2254,6 +2272,28 @@ struct drm_xe_vm_query_mem_range_attr {
 
 };
 
+/**
+ * struct drm_xe_exec_queue_set_property - exec queue set property
+ *
+ * Sets execution queue properties dynamically.
+ */
+struct drm_xe_exec_queue_set_property {
+	/** @extensions: Pointer to the first extension struct, if any */
+	__u64 extensions;
+
+	/** @exec_queue_id: Exec queue ID */
+	__u32 exec_queue_id;
+
+	/** @property: property to set */
+	__u32 property;
+
+	/** @value: property value */
+	__u64 value;
+
+	/** @reserved: Reserved */
+	__u64 reserved[2];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.43.0

Re: [PATCH v2 01/19] drm-uapi/xe: Sync with Multi-Queue uapi

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Sync kernel header to get Multi-Queue uapi definitions.
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> ---
>  include/drm-uapi/xe_drm.h | 40
> +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
> index 89ab54935..d1cb08dc7 100644
> --- a/include/drm-uapi/xe_drm.h
> +++ b/include/drm-uapi/xe_drm.h
> @@ -106,6 +106,7 @@ extern "C" {
>  #define DRM_XE_OBSERVATION             0x0b
>  #define DRM_XE_MADVISE                 0x0c
>  #define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS        0x0d
> +#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0e
>  
>  /* Must be kept compact -- no holes */
>  
> @@ -123,6 +124,7 @@ extern "C" {
>  #define
> DRM_IOCTL_XE_OBSERVATION               DRM_IOW(DRM_COMMAND_BASE +
> DRM_XE_OBSERVATION, struct drm_xe_observation_param)
>  #define
> DRM_IOCTL_XE_MADVISE                   DRM_IOW(DRM_COMMAND_BASE +
> DRM_XE_MADVISE, struct drm_xe_madvise)
>  #define
> DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS  DRM_IOWR(DRM_COMMAND_BASE +
> DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct
> drm_xe_vm_query_mem_range_attr)
> +#define
> DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY   DRM_IOW(DRM_COMMAND_BASE +
> DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct
> drm_xe_exec_queue_set_property)
>  
>  /**
>   * DOC: Xe IOCTL Extensions
> @@ -1233,6 +1235,18 @@ struct drm_xe_vm_bind {
>   *    Given that going into a power-saving state kills PXP HWDRM
> sessions,
>   *    runtime PM will be blocked while queues of this type are
> alive.
>   *    All PXP queues will be killed if a PXP invalidation event
> occurs.
> + *  - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP - Create a multi-
> queue group
> + *    or add secondary queues to a multi-queue group.
> + *    If the extension's 'value' field has
> %DRM_XE_MULTI_GROUP_CREATE flag set,
> + *    then a new multi-queue group is created with this queue as the
> primary queue
> + *    (Q0). Otherwise, the queue gets added to the multi-queue group
> whose primary
> + *    queue id is specified in the 'value' field.

Missing documentation, although compared to the ones below this is much
less interesting:

+ *    All the other non-relevant bits of extension's 'value' field
while adding the
+ *    primary or the secondary queues of the group must be set to 0.

> + *    If the extension's 'value' field has
> %DRM_XE_MULTI_GROUP_KEEP_ACTIVE flag
> + *    set, then the multi-queue group is kept active after the
> primary queue is
> + *    destroyed.
> + *
> + *  - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set the
> queue
> + *    priority within the multi-queue group.

I see a little more detail in the kernel patch here:

+ *    priority within the multi-queue group. Current valid priority
values are 0–2
+ *    (default is 1), with higher values indicating higher priority.

Why not include this documentation here?

>   *
>   * The example below shows how to use @drm_xe_exec_queue_create to
> create
>   * a simple exec_queue (no parallel submission) of class
> @@ -1273,6 +1287,10 @@ struct drm_xe_exec_queue_create {
>  #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY              0
>  #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE             1
>  #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE              2
> +#define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP           3
> +#define     DRM_XE_MULTI_GROUP_CREATE                          (1ull
> << 63)
> +#define     DRM_XE_MULTI_GROUP_KEEP_ACTIVE                     (1ull
> << 62)
> +#define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY  4
>         /** @extensions: Pointer to the first extension struct, if
> any */
>         __u64 extensions;
>  
> @@ -2254,6 +2272,28 @@ struct drm_xe_vm_query_mem_range_attr {
>  
>  };
>  
> +/**
> + * struct drm_xe_exec_queue_set_property - exec queue set property
> + *
> + * Sets execution queue properties dynamically.

Why not include the bit about the multi queue property being the only
one here?

+/**
+ * struct drm_xe_exec_queue_set_property - exec queue set property
+ *
+ * Sets execution queue properties dynamically.
+ * Currently only %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY
+ * property can be dynamically set.
+ */

Anyway these aren't function. From my perspective it's more nice to
have to align with the kernel. An IGT developer (and UMD dev) can and
should look at the documentation in the kernel itself anyway. For
consistency though it would be nice to keep this the same.

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

Thanks,
Stuart


> + */
> +struct drm_xe_exec_queue_set_property {
> +       /** @extensions: Pointer to the first extension struct, if
> any */
> +       __u64 extensions;
> +
> +       /** @exec_queue_id: Exec queue ID */
> +       __u32 exec_queue_id;
> +
> +       /** @property: property to set */
> +       __u32 property;
> +
> +       /** @value: property value */
> +       __u64 value;
> +
> +       /** @reserved: Reserved */
> +       __u64 reserved[2];
> +};
> +
>  #if defined(__cplusplus)
>  }
>  #endif

Re: [PATCH v2 01/19] drm-uapi/xe: Sync with Multi-Queue uapi

[Niranjana Vishwanathapura]

On Thu, Dec 04, 2025 at 11:19:47AM -0800, Summers, Stuart wrote:
>On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
>> Sync kernel header to get Multi-Queue uapi definitions.
>>
>> Signed-off-by: Niranjana Vishwanathapura
>> <niranjana.vishwanathapura@intel.com>
>> ---
>>  include/drm-uapi/xe_drm.h | 40
>> +++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 40 insertions(+)
>>
>> diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
>> index 89ab54935..d1cb08dc7 100644
>> --- a/include/drm-uapi/xe_drm.h
>> +++ b/include/drm-uapi/xe_drm.h
>> @@ -106,6 +106,7 @@ extern "C" {
>>  #define DRM_XE_OBSERVATION             0x0b
>>  #define DRM_XE_MADVISE                 0x0c
>>  #define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS        0x0d
>> +#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0e
>>  
>>  /* Must be kept compact -- no holes */
>>  
>> @@ -123,6 +124,7 @@ extern "C" {
>>  #define
>> DRM_IOCTL_XE_OBSERVATION               DRM_IOW(DRM_COMMAND_BASE +
>> DRM_XE_OBSERVATION, struct drm_xe_observation_param)
>>  #define
>> DRM_IOCTL_XE_MADVISE                   DRM_IOW(DRM_COMMAND_BASE +
>> DRM_XE_MADVISE, struct drm_xe_madvise)
>>  #define
>> DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS  DRM_IOWR(DRM_COMMAND_BASE +
>> DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct
>> drm_xe_vm_query_mem_range_attr)
>> +#define
>> DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY   DRM_IOW(DRM_COMMAND_BASE +
>> DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct
>> drm_xe_exec_queue_set_property)
>>  
>>  /**
>>   * DOC: Xe IOCTL Extensions
>> @@ -1233,6 +1235,18 @@ struct drm_xe_vm_bind {
>>   *    Given that going into a power-saving state kills PXP HWDRM
>> sessions,
>>   *    runtime PM will be blocked while queues of this type are
>> alive.
>>   *    All PXP queues will be killed if a PXP invalidation event
>> occurs.
>> + *  - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP - Create a multi-
>> queue group
>> + *    or add secondary queues to a multi-queue group.
>> + *    If the extension's 'value' field has
>> %DRM_XE_MULTI_GROUP_CREATE flag set,
>> + *    then a new multi-queue group is created with this queue as the
>> primary queue
>> + *    (Q0). Otherwise, the queue gets added to the multi-queue group
>> whose primary
>> + *    queue id is specified in the 'value' field.
>
>Missing documentation, although compared to the ones below this is much
>less interesting:
>
>+ *    All the other non-relevant bits of extension's 'value' field
>while adding the
>+ *    primary or the secondary queues of the group must be set to 0.
>
>> + *    If the extension's 'value' field has
>> %DRM_XE_MULTI_GROUP_KEEP_ACTIVE flag
>> + *    set, then the multi-queue group is kept active after the
>> primary queue is
>> + *    destroyed.
>> + *
>> + *  - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set the
>> queue
>> + *    priority within the multi-queue group.
>
>I see a little more detail in the kernel patch here:
>
>+ *    priority within the multi-queue group. Current valid priority
>values are 0–2
>+ *    (default is 1), with higher values indicating higher priority.
>
>Why not include this documentation here?
>

The updates to uapi documentation on kernel side was done as part of
review comment fix, which I forgot to import it here. Will import
them. I applies to below comments also.

Niranjana

>>   *
>>   * The example below shows how to use @drm_xe_exec_queue_create to
>> create
>>   * a simple exec_queue (no parallel submission) of class
>> @@ -1273,6 +1287,10 @@ struct drm_xe_exec_queue_create {
>>  #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY              0
>>  #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE             1
>>  #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE              2
>> +#define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP           3
>> +#define     DRM_XE_MULTI_GROUP_CREATE                          (1ull
>> << 63)
>> +#define     DRM_XE_MULTI_GROUP_KEEP_ACTIVE                     (1ull
>> << 62)
>> +#define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY  4
>>         /** @extensions: Pointer to the first extension struct, if
>> any */
>>         __u64 extensions;
>>  
>> @@ -2254,6 +2272,28 @@ struct drm_xe_vm_query_mem_range_attr {
>>  
>>  };
>>  
>> +/**
>> + * struct drm_xe_exec_queue_set_property - exec queue set property
>> + *
>> + * Sets execution queue properties dynamically.
>
>Why not include the bit about the multi queue property being the only
>one here?
>
>+/**
>+ * struct drm_xe_exec_queue_set_property - exec queue set property
>+ *
>+ * Sets execution queue properties dynamically.
>+ * Currently only %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY
>+ * property can be dynamically set.
>+ */
>
>Anyway these aren't function. From my perspective it's more nice to
>have to align with the kernel. An IGT developer (and UMD dev) can and
>should look at the documentation in the kernel itself anyway. For
>consistency though it would be nice to keep this the same.
>
>Reviewed-by: Stuart Summers <stuart.summers@intel.com>
>
>Thanks,
>Stuart
>
>
>> + */
>> +struct drm_xe_exec_queue_set_property {
>> +       /** @extensions: Pointer to the first extension struct, if
>> any */
>> +       __u64 extensions;
>> +
>> +       /** @exec_queue_id: Exec queue ID */
>> +       __u32 exec_queue_id;
>> +
>> +       /** @property: property to set */
>> +       __u32 property;
>> +
>> +       /** @value: property value */
>> +       __u64 value;
>> +
>> +       /** @reserved: Reserved */
>> +       __u64 reserved[2];
>> +};
>> +
>>  #if defined(__cplusplus)
>>  }
>>  #endif
>

Re: [PATCH v2 01/19] drm-uapi/xe: Sync with Multi-Queue uapi

[Summers, Stuart]

On Thu, 2025-12-04 at 12:58 -0800, Niranjana Vishwanathapura wrote:
> On Thu, Dec 04, 2025 at 11:19:47AM -0800, Summers, Stuart wrote:
> > On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> > > Sync kernel header to get Multi-Queue uapi definitions.
> > > 
> > > Signed-off-by: Niranjana Vishwanathapura
> > > <niranjana.vishwanathapura@intel.com>
> > > ---
> > >  include/drm-uapi/xe_drm.h | 40
> > > +++++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 40 insertions(+)
> > > 
> > > diff --git a/include/drm-uapi/xe_drm.h b/include/drm-
> > > uapi/xe_drm.h
> > > index 89ab54935..d1cb08dc7 100644
> > > --- a/include/drm-uapi/xe_drm.h
> > > +++ b/include/drm-uapi/xe_drm.h
> > > @@ -106,6 +106,7 @@ extern "C" {
> > >  #define DRM_XE_OBSERVATION             0x0b
> > >  #define DRM_XE_MADVISE                 0x0c
> > >  #define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS        0x0d
> > > +#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0e
> > >  
> > >  /* Must be kept compact -- no holes */
> > >  
> > > @@ -123,6 +124,7 @@ extern "C" {
> > >  #define
> > > DRM_IOCTL_XE_OBSERVATION               DRM_IOW(DRM_COMMAND_BASE +
> > > DRM_XE_OBSERVATION, struct drm_xe_observation_param)
> > >  #define
> > > DRM_IOCTL_XE_MADVISE                   DRM_IOW(DRM_COMMAND_BASE +
> > > DRM_XE_MADVISE, struct drm_xe_madvise)
> > >  #define
> > > DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS  DRM_IOWR(DRM_COMMAND_BASE
> > > +
> > > DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct
> > > drm_xe_vm_query_mem_range_attr)
> > > +#define
> > > DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY   DRM_IOW(DRM_COMMAND_BASE +
> > > DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct
> > > drm_xe_exec_queue_set_property)
> > >  
> > >  /**
> > >   * DOC: Xe IOCTL Extensions
> > > @@ -1233,6 +1235,18 @@ struct drm_xe_vm_bind {
> > >   *    Given that going into a power-saving state kills PXP HWDRM
> > > sessions,
> > >   *    runtime PM will be blocked while queues of this type are
> > > alive.
> > >   *    All PXP queues will be killed if a PXP invalidation event
> > > occurs.
> > > + *  - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP - Create a
> > > multi-
> > > queue group
> > > + *    or add secondary queues to a multi-queue group.
> > > + *    If the extension's 'value' field has
> > > %DRM_XE_MULTI_GROUP_CREATE flag set,
> > > + *    then a new multi-queue group is created with this queue as
> > > the
> > > primary queue
> > > + *    (Q0). Otherwise, the queue gets added to the multi-queue
> > > group
> > > whose primary
> > > + *    queue id is specified in the 'value' field.
> > 
> > Missing documentation, although compared to the ones below this is
> > much
> > less interesting:
> > 
> > + *    All the other non-relevant bits of extension's 'value' field
> > while adding the
> > + *    primary or the secondary queues of the group must be set to
> > 0.
> > 
> > > + *    If the extension's 'value' field has
> > > %DRM_XE_MULTI_GROUP_KEEP_ACTIVE flag
> > > + *    set, then the multi-queue group is kept active after the
> > > primary queue is
> > > + *    destroyed.
> > > + *
> > > + *  - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set
> > > the
> > > queue
> > > + *    priority within the multi-queue group.
> > 
> > I see a little more detail in the kernel patch here:
> > 
> > + *    priority within the multi-queue group. Current valid
> > priority
> > values are 0–2
> > + *    (default is 1), with higher values indicating higher
> > priority.
> > 
> > Why not include this documentation here?
> > 
> 
> The updates to uapi documentation on kernel side was done as part of
> review comment fix, which I forgot to import it here. Will import
> them. I applies to below comments also.

Makes sense and sounds great. Thanks!

-Stuart

> 
> Niranjana
> 
> > >   *
> > >   * The example below shows how to use @drm_xe_exec_queue_create
> > > to
> > > create
> > >   * a simple exec_queue (no parallel submission) of class
> > > @@ -1273,6 +1287,10 @@ struct drm_xe_exec_queue_create {
> > >  #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY              0
> > >  #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE             1
> > >  #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE              2
> > > +#define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP           3
> > > +#define    
> > > DRM_XE_MULTI_GROUP_CREATE                          (1ull
> > > << 63)
> > > +#define    
> > > DRM_XE_MULTI_GROUP_KEEP_ACTIVE                     (1ull
> > > << 62)
> > > +#define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY  4
> > >         /** @extensions: Pointer to the first extension struct,
> > > if
> > > any */
> > >         __u64 extensions;
> > >  
> > > @@ -2254,6 +2272,28 @@ struct drm_xe_vm_query_mem_range_attr {
> > >  
> > >  };
> > >  
> > > +/**
> > > + * struct drm_xe_exec_queue_set_property - exec queue set
> > > property
> > > + *
> > > + * Sets execution queue properties dynamically.
> > 
> > Why not include the bit about the multi queue property being the
> > only
> > one here?
> > 
> > +/**
> > + * struct drm_xe_exec_queue_set_property - exec queue set property
> > + *
> > + * Sets execution queue properties dynamically.
> > + * Currently only
> > %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY
> > + * property can be dynamically set.
> > + */
> > 
> > Anyway these aren't function. From my perspective it's more nice to
> > have to align with the kernel. An IGT developer (and UMD dev) can
> > and
> > should look at the documentation in the kernel itself anyway. For
> > consistency though it would be nice to keep this the same.
> > 
> > Reviewed-by: Stuart Summers <stuart.summers@intel.com>
> > 
> > Thanks,
> > Stuart
> > 
> > 
> > > + */
> > > +struct drm_xe_exec_queue_set_property {
> > > +       /** @extensions: Pointer to the first extension struct,
> > > if
> > > any */
> > > +       __u64 extensions;
> > > +
> > > +       /** @exec_queue_id: Exec queue ID */
> > > +       __u32 exec_queue_id;
> > > +
> > > +       /** @property: property to set */
> > > +       __u32 property;
> > > +
> > > +       /** @value: property value */
> > > +       __u64 value;
> > > +
> > > +       /** @reserved: Reserved */
> > > +       __u64 reserved[2];
> > > +};
> > > +
> > >  #if defined(__cplusplus)
> > >  }
> > >  #endif
> > 

[PATCH v2 02/19] lib/xe: Add multi-queue helper routines

[Niranjana Vishwanathapura]

From: Nishit Sharma <nishit.sharma@intel.com>

Add xe_engine_class_supports_multi_queue() function to determine if an
engine class supports multi-queue operations.
Add xe_for_each_multi_queue_engine() helper macro for iterating over
engines that support multi-queue.

Signed-off-by: Nishit Sharma <nishit.sharma@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 lib/xe/xe_query.c | 22 ++++++++++++++++++++++
 lib/xe/xe_query.h |  8 ++++++++
 2 files changed, 30 insertions(+)

diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 53af86a99..8a67db6a9 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -264,6 +264,28 @@ static uint32_t __mem_default_alignment(struct drm_xe_query_mem_regions *mem_reg
 	return alignment;
 }
 
+/**
+ * xe_engine_class_supports_multi_queue:
+ * @engine_class: engine class
+ *
+ * Returns true if multi queue supported by engine class or false.
+ */
+bool xe_engine_class_supports_multi_queue(uint32_t engine_class)
+{
+	switch (engine_class) {
+		case DRM_XE_ENGINE_CLASS_COPY:
+		case DRM_XE_ENGINE_CLASS_COMPUTE:
+			return true;
+		case DRM_XE_ENGINE_CLASS_RENDER:
+		case DRM_XE_ENGINE_CLASS_VIDEO_DECODE:
+		case DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE:
+			return false;
+		default:
+			igt_warn("Engine class 0x%x unknown\n", engine_class);
+			return false;
+	}
+}
+
 /**
  * xe_engine_class_string:
  * @engine_class: engine class
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index 6a97d384a..43db89617 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -94,6 +94,13 @@ struct xe_device {
 	for (uint64_t igt_unique(__i) = 0; igt_unique(__i) < igt_fls(__memreg); igt_unique(__i)++) \
 		for_if(__r = (__memreg & (1ull << igt_unique(__i))))
 
+#define xe_for_each_multi_queue_engine(__fd, __hwe)	\
+	xe_for_each_engine(__fd, __hwe)			\
+		for_if(xe_engine_class_supports_multi_queue((__hwe)->engine_class))
+#define xe_for_each_multi_queue_engine_class(__class)			\
+	xe_for_each_engine_class(__class)				\
+		for_if(xe_engine_class_supports_multi_queue(__class))
+
 #define XE_IS_CLASS_SYSMEM(__region) ((__region)->mem_class == DRM_XE_MEM_REGION_CLASS_SYSMEM)
 #define XE_IS_CLASS_VRAM(__region) ((__region)->mem_class == DRM_XE_MEM_REGION_CLASS_VRAM)
 
@@ -131,6 +138,7 @@ uint32_t xe_get_default_alignment(int fd);
 uint32_t xe_va_bits(int fd);
 uint16_t xe_dev_id(int fd);
 int xe_supports_faults(int fd);
+bool xe_engine_class_supports_multi_queue(uint32_t engine_class);
 const char *xe_engine_class_string(uint32_t engine_class);
 const char *xe_engine_class_short_string(uint32_t engine_class);
 bool xe_has_engine_class(int fd, uint16_t engine_class);
-- 
2.43.0

Re: [PATCH v2 02/19] lib/xe: Add multi-queue helper routines

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> From: Nishit Sharma <nishit.sharma@intel.com>
> 
> Add xe_engine_class_supports_multi_queue() function to determine if
> an
> engine class supports multi-queue operations.
> Add xe_for_each_multi_queue_engine() helper macro for iterating over
> engines that support multi-queue.
> 
> Signed-off-by: Nishit Sharma <nishit.sharma@intel.com>
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> ---
>  lib/xe/xe_query.c | 22 ++++++++++++++++++++++
>  lib/xe/xe_query.h |  8 ++++++++
>  2 files changed, 30 insertions(+)
> 
> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> index 53af86a99..8a67db6a9 100644
> --- a/lib/xe/xe_query.c
> +++ b/lib/xe/xe_query.c
> @@ -264,6 +264,28 @@ static uint32_t __mem_default_alignment(struct
> drm_xe_query_mem_regions *mem_reg
>         return alignment;
>  }
>  
> +/**
> + * xe_engine_class_supports_multi_queue:
> + * @engine_class: engine class
> + *
> + * Returns true if multi queue supported by engine class or false.
> + */
> +bool xe_engine_class_supports_multi_queue(uint32_t engine_class)
> +{
> +       switch (engine_class) {
> +               case DRM_XE_ENGINE_CLASS_COPY:
> +               case DRM_XE_ENGINE_CLASS_COMPUTE:
> +                       return true;
> +               case DRM_XE_ENGINE_CLASS_RENDER:
> +               case DRM_XE_ENGINE_CLASS_VIDEO_DECODE:
> +               case DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE:
> +                       return false;

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> +               default:
> +                       igt_warn("Engine class 0x%x unknown\n",
> engine_class);
> +                       return false;
> +       }
> +}
> +
>  /**
>   * xe_engine_class_string:
>   * @engine_class: engine class
> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> index 6a97d384a..43db89617 100644
> --- a/lib/xe/xe_query.h
> +++ b/lib/xe/xe_query.h
> @@ -94,6 +94,13 @@ struct xe_device {
>         for (uint64_t igt_unique(__i) = 0; igt_unique(__i) <
> igt_fls(__memreg); igt_unique(__i)++) \
>                 for_if(__r = (__memreg & (1ull << igt_unique(__i))))
>  
> +#define xe_for_each_multi_queue_engine(__fd, __hwe)    \
> +       xe_for_each_engine(__fd, __hwe)                 \
> +               for_if(xe_engine_class_supports_multi_queue((__hwe)-
> >engine_class))
> +#define
> xe_for_each_multi_queue_engine_class(__class)                  \
> +       xe_for_each_engine_class(__class)                            
>    \
> +               for_if(xe_engine_class_supports_multi_queue(__class))
> +
>  #define XE_IS_CLASS_SYSMEM(__region) ((__region)->mem_class ==
> DRM_XE_MEM_REGION_CLASS_SYSMEM)
>  #define XE_IS_CLASS_VRAM(__region) ((__region)->mem_class ==
> DRM_XE_MEM_REGION_CLASS_VRAM)
>  
> @@ -131,6 +138,7 @@ uint32_t xe_get_default_alignment(int fd);
>  uint32_t xe_va_bits(int fd);
>  uint16_t xe_dev_id(int fd);
>  int xe_supports_faults(int fd);
> +bool xe_engine_class_supports_multi_queue(uint32_t engine_class);
>  const char *xe_engine_class_string(uint32_t engine_class);
>  const char *xe_engine_class_short_string(uint32_t engine_class);
>  bool xe_has_engine_class(int fd, uint16_t engine_class);

[PATCH v2 03/19] tests/intel/xe_exec_multi_queue: Add xe_exec_multi_queue test

[Niranjana Vishwanathapura]

Add sanity test for the multi queue feature.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 163 ++++++++++++++++++++++++++++++
 tests/meson.build                 |   1 +
 2 files changed, 164 insertions(+)
 create mode 100644 tests/intel/xe_exec_multi_queue.c

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
new file mode 100644
index 000000000..03b920dc8
--- /dev/null
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+/**
+ * TEST: Basic tests for exec functionality with multi-queue feature
+ * Category: Hardware building block
+ * Mega feature: General Core features
+ * Sub-category: CMD submission
+ * Functionality: multi-queue
+ */
+
+#include "igt.h"
+#include "xe_drm.h"
+
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_N_EXEC_QUEUES	64
+
+#define MAX_INSTANCE 9
+
+#define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE)
+
+static void
+__test_sanity(int fd, int gt, int class)
+{
+	uint32_t exec_queues[MAX_N_EXEC_QUEUES];
+	struct drm_xe_ext_set_property multi_queue = {
+		.base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+		.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
+		.value = DRM_XE_MULTI_GROUP_CREATE,
+	};
+	uint64_t invalid_flag = 0, ext = to_user_pointer(&multi_queue);
+	struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+	struct drm_xe_engine_class_instance *hwe;
+	uint32_t vm, vm2, val;
+	int i, n = 0;
+
+	xe_for_each_engine(fd, hwe) {
+		if (hwe->engine_class != class || hwe->gt_id != gt)
+			continue;
+
+		eci[n++] = *hwe;
+	}
+
+	if (!n)
+		return;
+
+	vm = xe_vm_create(fd, 0, 0);
+
+	/* Invalid flags */
+	while (!invalid_flag)
+		invalid_flag = (1ull << (rand() % 63)) & ~XE_MULTI_GROUP_VALID_FLAGS;
+	multi_queue.value |= invalid_flag;
+	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -EINVAL);
+	multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
+
+	/* Q0 can't be a regular queue */
+	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, 0);
+	multi_queue.value = exec_queues[0];
+	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -EINVAL);
+	xe_exec_queue_destroy(fd, exec_queues[0]);
+
+	/* Multi-Queue can't be a parallel queue */
+	multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
+	if (n > 1)
+		igt_assert_eq(__xe_exec_queue_create(fd, vm, 2, 1, eci, ext, &val), -EINVAL);
+
+	/* Specifying multiple MULTI_GROUP property is invalid */
+	multi_queue.base.next_extension = to_user_pointer(&multi_queue);
+	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -EINVAL);
+
+	/* Adding queues to group after primary is destroyed is invalid */
+	multi_queue.base.next_extension = 0;
+	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
+	xe_exec_queue_destroy(fd, exec_queues[0]);
+	multi_queue.value = exec_queues[0];
+	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -ENOENT);
+
+	multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
+	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
+
+	/* Upper 32 bits must be 0 while adding secondary queues */
+	multi_queue.value = exec_queues[0] | (1ull << (32 + (rand() % 32)));
+	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -EINVAL);
+
+	/* Invalid Q0 */
+	multi_queue.value = exec_queues[0] + 1;
+	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -ENOENT);
+
+	/* Queues in a queue group must share the same address space (vm) */
+	multi_queue.value = exec_queues[0];
+	vm2 = xe_vm_create(fd, 0, 0);
+	igt_assert_eq(__xe_exec_queue_create(fd, vm2, 1, 1, eci, ext, &val), -EINVAL);
+	xe_vm_destroy(fd, vm2);
+
+	/* Secondary queues must map to same engine instances as primary queue */
+	if (n > 1)
+		igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n, eci, ext, &val), -EINVAL);
+
+	for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
+		exec_queues[i] = xe_exec_queue_create(fd, vm, eci, ext);
+
+	/* Queue group limit check */
+	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -EINVAL);
+
+	/* Secondary queues can't be replaced once successfully created */
+	xe_exec_queue_destroy(fd, exec_queues[1]);
+	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -EINVAL);
+
+	/* Primary queue can be destroyed before all secondary queues are destroyed */
+	xe_exec_queue_destroy(fd, exec_queues[0]);
+
+	for (i = 2; i < MAX_N_EXEC_QUEUES; i++)
+		xe_exec_queue_destroy(fd, exec_queues[i]);
+
+	/* Validate with multiple num_placements */
+	if (n > 1) {
+		multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
+		multi_queue.base.next_extension = 0;
+		igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n, eci, ext, &exec_queues[0]), 0);
+
+		multi_queue.value = exec_queues[0];
+		for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
+			igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n, eci, ext, &exec_queues[i]), 0);
+
+		for (i = 0; i < MAX_N_EXEC_QUEUES; i++)
+			xe_exec_queue_destroy(fd, exec_queues[i]);
+	}
+
+	xe_vm_destroy(fd, vm);
+}
+
+/**
+ * SUBTEST: sanity
+ * Description: Run sanity test
+ * Test category: functionality test
+ */
+static void
+test_sanity(int fd, int gt, int class)
+{
+	__test_sanity(fd, gt, class);
+}
+
+igt_main
+{
+	int fd, gt, class;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_XE);
+		igt_require(intel_graphics_ver(intel_get_drm_devid(fd)) >= IP_VER(35, 0));
+	}
+
+	igt_subtest_f("sanity")
+		xe_for_each_gt(fd, gt)
+			xe_for_each_multi_queue_engine_class(class)
+				test_sanity(fd, gt, class);
+
+	igt_fixture
+		drm_close_driver(fd);
+}
diff --git a/tests/meson.build b/tests/meson.build
index ecc0f4c7f..58d223937 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -297,6 +297,7 @@ intel_xe_progs = [
 	'xe_exec_compute_mode',
 	'xe_exec_fault_mode',
 	'xe_exec_mix_modes',
+	'xe_exec_multi_queue',
 	'xe_exec_queue_property',
 	'xe_exec_reset',
 	'xe_exec_sip',
-- 
2.43.0

Re: [PATCH v2 03/19] tests/intel/xe_exec_multi_queue: Add xe_exec_multi_queue test

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Add sanity test for the multi queue feature.
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> Reviewed-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  tests/intel/xe_exec_multi_queue.c | 163
> ++++++++++++++++++++++++++++++
>  tests/meson.build                 |   1 +
>  2 files changed, 164 insertions(+)
>  create mode 100644 tests/intel/xe_exec_multi_queue.c
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> new file mode 100644
> index 000000000..03b920dc8
> --- /dev/null
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -0,0 +1,163 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +/**
> + * TEST: Basic tests for exec functionality with multi-queue feature
> + * Category: Hardware building block
> + * Mega feature: General Core features
> + * Sub-category: CMD submission
> + * Functionality: multi-queue
> + */
> +
> +#include "igt.h"
> +#include "xe_drm.h"
> +
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_N_EXEC_QUEUES      64
> +
> +#define MAX_INSTANCE 9
> +
> +#define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE)
> +
> +static void
> +__test_sanity(int fd, int gt, int class)
> +{
> +       uint32_t exec_queues[MAX_N_EXEC_QUEUES];
> +       struct drm_xe_ext_set_property multi_queue = {
> +               .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +               .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
> +               .value = DRM_XE_MULTI_GROUP_CREATE,
> +       };
> +       uint64_t invalid_flag = 0, ext =
> to_user_pointer(&multi_queue);
> +       struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> +       struct drm_xe_engine_class_instance *hwe;
> +       uint32_t vm, vm2, val;
> +       int i, n = 0;
> +
> +       xe_for_each_engine(fd, hwe) {
> +               if (hwe->engine_class != class || hwe->gt_id != gt)
> +                       continue;
> +
> +               eci[n++] = *hwe;
> +       }
> +
> +       if (!n)
> +               return;
> +
> +       vm = xe_vm_create(fd, 0, 0);
> +
> +       /* Invalid flags */
> +       while (!invalid_flag)
> +               invalid_flag = (1ull << (rand() % 63)) &
> ~XE_MULTI_GROUP_VALID_FLAGS;
> +       multi_queue.value |= invalid_flag;
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -EINVAL);
> +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> +
> +       /* Q0 can't be a regular queue */
> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, 0);
> +       multi_queue.value = exec_queues[0];
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -EINVAL);
> +       xe_exec_queue_destroy(fd, exec_queues[0]);
> +
> +       /* Multi-Queue can't be a parallel queue */
> +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> +       if (n > 1)
> +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 2, 1,
> eci, ext, &val), -EINVAL);
> +
> +       /* Specifying multiple MULTI_GROUP property is invalid */
> +       multi_queue.base.next_extension =
> to_user_pointer(&multi_queue);
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -EINVAL);
> +
> +       /* Adding queues to group after primary is destroyed is
> invalid */
> +       multi_queue.base.next_extension = 0;
> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> +       xe_exec_queue_destroy(fd, exec_queues[0]);
> +       multi_queue.value = exec_queues[0];
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -ENOENT);
> +
> +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> +
> +       /* Upper 32 bits must be 0 while adding secondary queues */
> +       multi_queue.value = exec_queues[0] | (1ull << (32 + (rand() %
> 32)));
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -EINVAL);
> +
> +       /* Invalid Q0 */
> +       multi_queue.value = exec_queues[0] + 1;
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -ENOENT);
> +
> +       /* Queues in a queue group must share the same address space
> (vm) */
> +       multi_queue.value = exec_queues[0];
> +       vm2 = xe_vm_create(fd, 0, 0);
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm2, 1, 1, eci, ext,
> &val), -EINVAL);
> +       xe_vm_destroy(fd, vm2);
> +
> +       /* Secondary queues must map to same engine instances as
> primary queue */
> +       if (n > 1)
> +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n,
> eci, ext, &val), -EINVAL);
> +
> +       for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
> +               exec_queues[i] = xe_exec_queue_create(fd, vm, eci,
> ext);
> +
> +       /* Queue group limit check */
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -EINVAL);
> +
> +       /* Secondary queues can't be replaced once successfully
> created */
> +       xe_exec_queue_destroy(fd, exec_queues[1]);
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -EINVAL);
> +
> +       /* Primary queue can be destroyed before all secondary queues
> are destroyed */
> +       xe_exec_queue_destroy(fd, exec_queues[0]);
> +
> +       for (i = 2; i < MAX_N_EXEC_QUEUES; i++)
> +               xe_exec_queue_destroy(fd, exec_queues[i]);
> +
> +       /* Validate with multiple num_placements */
> +       if (n > 1) {
> +               multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> +               multi_queue.base.next_extension = 0;
> +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n,
> eci, ext, &exec_queues[0]), 0);

This is the logical mask we're passing to GuC right? The expectation
here is that GuC will see that these are part of the same multi queue
group and make sure they go to the same instance right? If so, it would
be nice to have a comment somewhere, either here or in the driver
indicating this.

Is there any requirement (or should there be) that the num_placements
be the same between the primary and secondary queue? If not, we can go
with what you have here. If so though, maybe we want to add a case
where the "n" we pass below is different from the one we pass for the
primary queue above.

Thanks,
Stuart

> +
> +               multi_queue.value = exec_queues[0];
> +               for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
> +                       igt_assert_eq(__xe_exec_queue_create(fd, vm,
> 1, n, eci, ext, &exec_queues[i]), 0);
> +
> +               for (i = 0; i < MAX_N_EXEC_QUEUES; i++)
> +                       xe_exec_queue_destroy(fd, exec_queues[i]);
> +       }
> +
> +       xe_vm_destroy(fd, vm);
> +}
> +
> +/**
> + * SUBTEST: sanity
> + * Description: Run sanity test
> + * Test category: functionality test
> + */
> +static void
> +test_sanity(int fd, int gt, int class)
> +{
> +       __test_sanity(fd, gt, class);
> +}
> +
> +igt_main
> +{
> +       int fd, gt, class;
> +
> +       igt_fixture {
> +               fd = drm_open_driver(DRIVER_XE);
> +               igt_require(intel_graphics_ver(intel_get_drm_devid(fd
> )) >= IP_VER(35, 0));
> +       }
> +
> +       igt_subtest_f("sanity")
> +               xe_for_each_gt(fd, gt)
> +                       xe_for_each_multi_queue_engine_class(class)
> +                               test_sanity(fd, gt, class);
> +
> +       igt_fixture
> +               drm_close_driver(fd);
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index ecc0f4c7f..58d223937 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -297,6 +297,7 @@ intel_xe_progs = [
>         'xe_exec_compute_mode',
>         'xe_exec_fault_mode',
>         'xe_exec_mix_modes',
> +       'xe_exec_multi_queue',
>         'xe_exec_queue_property',
>         'xe_exec_reset',
>         'xe_exec_sip',

Re: [PATCH v2 03/19] tests/intel/xe_exec_multi_queue: Add xe_exec_multi_queue test

[Niranjana Vishwanathapura]

On Thu, Dec 04, 2025 at 12:02:32PM -0800, Summers, Stuart wrote:
>On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
>> Add sanity test for the multi queue feature.
>>
>> Signed-off-by: Niranjana Vishwanathapura
>> <niranjana.vishwanathapura@intel.com>
>> Reviewed-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>> ---
>>  tests/intel/xe_exec_multi_queue.c | 163
>> ++++++++++++++++++++++++++++++
>>  tests/meson.build                 |   1 +
>>  2 files changed, 164 insertions(+)
>>  create mode 100644 tests/intel/xe_exec_multi_queue.c
>>
>> diff --git a/tests/intel/xe_exec_multi_queue.c
>> b/tests/intel/xe_exec_multi_queue.c
>> new file mode 100644
>> index 000000000..03b920dc8
>> --- /dev/null
>> +++ b/tests/intel/xe_exec_multi_queue.c
>> @@ -0,0 +1,163 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2025 Intel Corporation
>> + */
>> +
>> +/**
>> + * TEST: Basic tests for exec functionality with multi-queue feature
>> + * Category: Hardware building block
>> + * Mega feature: General Core features
>> + * Sub-category: CMD submission
>> + * Functionality: multi-queue
>> + */
>> +
>> +#include "igt.h"
>> +#include "xe_drm.h"
>> +
>> +#include "xe/xe_ioctl.h"
>> +#include "xe/xe_query.h"
>> +
>> +#define MAX_N_EXEC_QUEUES      64
>> +
>> +#define MAX_INSTANCE 9
>> +
>> +#define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE)
>> +
>> +static void
>> +__test_sanity(int fd, int gt, int class)
>> +{
>> +       uint32_t exec_queues[MAX_N_EXEC_QUEUES];
>> +       struct drm_xe_ext_set_property multi_queue = {
>> +               .base.name =
>> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
>> +               .property =
>> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
>> +               .value = DRM_XE_MULTI_GROUP_CREATE,
>> +       };
>> +       uint64_t invalid_flag = 0, ext =
>> to_user_pointer(&multi_queue);
>> +       struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
>> +       struct drm_xe_engine_class_instance *hwe;
>> +       uint32_t vm, vm2, val;
>> +       int i, n = 0;
>> +
>> +       xe_for_each_engine(fd, hwe) {
>> +               if (hwe->engine_class != class || hwe->gt_id != gt)
>> +                       continue;
>> +
>> +               eci[n++] = *hwe;
>> +       }
>> +
>> +       if (!n)
>> +               return;
>> +
>> +       vm = xe_vm_create(fd, 0, 0);
>> +
>> +       /* Invalid flags */
>> +       while (!invalid_flag)
>> +               invalid_flag = (1ull << (rand() % 63)) &
>> ~XE_MULTI_GROUP_VALID_FLAGS;
>> +       multi_queue.value |= invalid_flag;
>> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
>> &val), -EINVAL);
>> +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
>> +
>> +       /* Q0 can't be a regular queue */
>> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, 0);
>> +       multi_queue.value = exec_queues[0];
>> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
>> &val), -EINVAL);
>> +       xe_exec_queue_destroy(fd, exec_queues[0]);
>> +
>> +       /* Multi-Queue can't be a parallel queue */
>> +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
>> +       if (n > 1)
>> +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 2, 1,
>> eci, ext, &val), -EINVAL);
>> +
>> +       /* Specifying multiple MULTI_GROUP property is invalid */
>> +       multi_queue.base.next_extension =
>> to_user_pointer(&multi_queue);
>> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
>> &val), -EINVAL);
>> +
>> +       /* Adding queues to group after primary is destroyed is
>> invalid */
>> +       multi_queue.base.next_extension = 0;
>> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
>> +       xe_exec_queue_destroy(fd, exec_queues[0]);
>> +       multi_queue.value = exec_queues[0];
>> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
>> &val), -ENOENT);
>> +
>> +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
>> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
>> +
>> +       /* Upper 32 bits must be 0 while adding secondary queues */
>> +       multi_queue.value = exec_queues[0] | (1ull << (32 + (rand() %
>> 32)));
>> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
>> &val), -EINVAL);
>> +
>> +       /* Invalid Q0 */
>> +       multi_queue.value = exec_queues[0] + 1;
>> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
>> &val), -ENOENT);
>> +
>> +       /* Queues in a queue group must share the same address space
>> (vm) */
>> +       multi_queue.value = exec_queues[0];
>> +       vm2 = xe_vm_create(fd, 0, 0);
>> +       igt_assert_eq(__xe_exec_queue_create(fd, vm2, 1, 1, eci, ext,
>> &val), -EINVAL);
>> +       xe_vm_destroy(fd, vm2);
>> +
>> +       /* Secondary queues must map to same engine instances as
>> primary queue */
>> +       if (n > 1)
>> +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n,
>> eci, ext, &val), -EINVAL);
>> +
>> +       for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
>> +               exec_queues[i] = xe_exec_queue_create(fd, vm, eci,
>> ext);
>> +
>> +       /* Queue group limit check */
>> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
>> &val), -EINVAL);
>> +
>> +       /* Secondary queues can't be replaced once successfully
>> created */
>> +       xe_exec_queue_destroy(fd, exec_queues[1]);
>> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
>> &val), -EINVAL);
>> +
>> +       /* Primary queue can be destroyed before all secondary queues
>> are destroyed */
>> +       xe_exec_queue_destroy(fd, exec_queues[0]);
>> +
>> +       for (i = 2; i < MAX_N_EXEC_QUEUES; i++)
>> +               xe_exec_queue_destroy(fd, exec_queues[i]);
>> +
>> +       /* Validate with multiple num_placements */
>> +       if (n > 1) {
>> +               multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
>> +               multi_queue.base.next_extension = 0;
>> +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n,
>> eci, ext, &exec_queues[0]), 0);
>
>This is the logical mask we're passing to GuC right? The expectation
>here is that GuC will see that these are part of the same multi queue
>group and make sure they go to the same instance right? If so, it would
>be nice to have a comment somewhere, either here or in the driver
>indicating this.
>

It is not multi-queue specific. Yah, it is for guc to choose an engine
instance (from the placements specified) for a context (regular or a
multi-queue context). Just adding this sanity here to ensure multi-queue
doesn't break if num_placements are used.

>Is there any requirement (or should there be) that the num_placements
>be the same between the primary and secondary queue? If not, we can go
>with what you have here. If so though, maybe we want to add a case
>where the "n" we pass below is different from the one we pass for the
>primary queue above.

That test is already added few lines above. Look for,

         /* Secondary queues must map to same engine instances as primary queue */
         if (n > 1)
                 igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n, eci, ext, &val), -EINVAL);

Niranjana

>
>Thanks,
>Stuart
>
>> +
>> +               multi_queue.value = exec_queues[0];
>> +               for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
>> +                       igt_assert_eq(__xe_exec_queue_create(fd, vm,
>> 1, n, eci, ext, &exec_queues[i]), 0);
>> +
>> +               for (i = 0; i < MAX_N_EXEC_QUEUES; i++)
>> +                       xe_exec_queue_destroy(fd, exec_queues[i]);
>> +       }
>> +
>> +       xe_vm_destroy(fd, vm);
>> +}
>> +
>> +/**
>> + * SUBTEST: sanity
>> + * Description: Run sanity test
>> + * Test category: functionality test
>> + */
>> +static void
>> +test_sanity(int fd, int gt, int class)
>> +{
>> +       __test_sanity(fd, gt, class);
>> +}
>> +
>> +igt_main
>> +{
>> +       int fd, gt, class;
>> +
>> +       igt_fixture {
>> +               fd = drm_open_driver(DRIVER_XE);
>> +               igt_require(intel_graphics_ver(intel_get_drm_devid(fd
>> )) >= IP_VER(35, 0));
>> +       }
>> +
>> +       igt_subtest_f("sanity")
>> +               xe_for_each_gt(fd, gt)
>> +                       xe_for_each_multi_queue_engine_class(class)
>> +                               test_sanity(fd, gt, class);
>> +
>> +       igt_fixture
>> +               drm_close_driver(fd);
>> +}
>> diff --git a/tests/meson.build b/tests/meson.build
>> index ecc0f4c7f..58d223937 100644
>> --- a/tests/meson.build
>> +++ b/tests/meson.build
>> @@ -297,6 +297,7 @@ intel_xe_progs = [
>>         'xe_exec_compute_mode',
>>         'xe_exec_fault_mode',
>>         'xe_exec_mix_modes',
>> +       'xe_exec_multi_queue',
>>         'xe_exec_queue_property',
>>         'xe_exec_reset',
>>         'xe_exec_sip',
>

Re: [PATCH v2 03/19] tests/intel/xe_exec_multi_queue: Add xe_exec_multi_queue test

[Summers, Stuart]

On Thu, 2025-12-04 at 17:34 -0800, Niranjana Vishwanathapura wrote:
> On Thu, Dec 04, 2025 at 12:02:32PM -0800, Summers, Stuart wrote:
> > On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> > > Add sanity test for the multi queue feature.
> > > 
> > > Signed-off-by: Niranjana Vishwanathapura
> > > <niranjana.vishwanathapura@intel.com>
> > > Reviewed-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > > ---
> > >  tests/intel/xe_exec_multi_queue.c | 163
> > > ++++++++++++++++++++++++++++++
> > >  tests/meson.build                 |   1 +
> > >  2 files changed, 164 insertions(+)
> > >  create mode 100644 tests/intel/xe_exec_multi_queue.c
> > > 
> > > diff --git a/tests/intel/xe_exec_multi_queue.c
> > > b/tests/intel/xe_exec_multi_queue.c
> > > new file mode 100644
> > > index 000000000..03b920dc8
> > > --- /dev/null
> > > +++ b/tests/intel/xe_exec_multi_queue.c
> > > @@ -0,0 +1,163 @@
> > > +// SPDX-License-Identifier: MIT
> > > +/*
> > > + * Copyright © 2025 Intel Corporation
> > > + */
> > > +
> > > +/**
> > > + * TEST: Basic tests for exec functionality with multi-queue
> > > feature
> > > + * Category: Hardware building block
> > > + * Mega feature: General Core features
> > > + * Sub-category: CMD submission
> > > + * Functionality: multi-queue
> > > + */
> > > +
> > > +#include "igt.h"
> > > +#include "xe_drm.h"
> > > +
> > > +#include "xe/xe_ioctl.h"
> > > +#include "xe/xe_query.h"
> > > +
> > > +#define MAX_N_EXEC_QUEUES      64
> > > +
> > > +#define MAX_INSTANCE 9
> > > +
> > > +#define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE)
> > > +
> > > +static void
> > > +__test_sanity(int fd, int gt, int class)
> > > +{
> > > +       uint32_t exec_queues[MAX_N_EXEC_QUEUES];
> > > +       struct drm_xe_ext_set_property multi_queue = {
> > > +               .base.name =
> > > DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> > > +               .property =
> > > DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
> > > +               .value = DRM_XE_MULTI_GROUP_CREATE,
> > > +       };
> > > +       uint64_t invalid_flag = 0, ext =
> > > to_user_pointer(&multi_queue);
> > > +       struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> > > +       struct drm_xe_engine_class_instance *hwe;
> > > +       uint32_t vm, vm2, val;
> > > +       int i, n = 0;
> > > +
> > > +       xe_for_each_engine(fd, hwe) {
> > > +               if (hwe->engine_class != class || hwe->gt_id !=
> > > gt)
> > > +                       continue;
> > > +
> > > +               eci[n++] = *hwe;
> > > +       }
> > > +
> > > +       if (!n)
> > > +               return;
> > > +
> > > +       vm = xe_vm_create(fd, 0, 0);
> > > +
> > > +       /* Invalid flags */
> > > +       while (!invalid_flag)
> > > +               invalid_flag = (1ull << (rand() % 63)) &
> > > ~XE_MULTI_GROUP_VALID_FLAGS;
> > > +       multi_queue.value |= invalid_flag;
> > > +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci,
> > > ext,
> > > &val), -EINVAL);
> > > +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> > > +
> > > +       /* Q0 can't be a regular queue */
> > > +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, 0);
> > > +       multi_queue.value = exec_queues[0];
> > > +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci,
> > > ext,
> > > &val), -EINVAL);
> > > +       xe_exec_queue_destroy(fd, exec_queues[0]);
> > > +
> > > +       /* Multi-Queue can't be a parallel queue */
> > > +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> > > +       if (n > 1)
> > > +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 2,
> > > 1,
> > > eci, ext, &val), -EINVAL);
> > > +
> > > +       /* Specifying multiple MULTI_GROUP property is invalid */
> > > +       multi_queue.base.next_extension =
> > > to_user_pointer(&multi_queue);
> > > +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci,
> > > ext,
> > > &val), -EINVAL);
> > > +
> > > +       /* Adding queues to group after primary is destroyed is
> > > invalid */
> > > +       multi_queue.base.next_extension = 0;
> > > +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> > > +       xe_exec_queue_destroy(fd, exec_queues[0]);
> > > +       multi_queue.value = exec_queues[0];
> > > +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci,
> > > ext,
> > > &val), -ENOENT);
> > > +
> > > +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> > > +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> > > +
> > > +       /* Upper 32 bits must be 0 while adding secondary queues
> > > */
> > > +       multi_queue.value = exec_queues[0] | (1ull << (32 +
> > > (rand() %
> > > 32)));
> > > +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci,
> > > ext,
> > > &val), -EINVAL);
> > > +
> > > +       /* Invalid Q0 */
> > > +       multi_queue.value = exec_queues[0] + 1;
> > > +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci,
> > > ext,
> > > &val), -ENOENT);
> > > +
> > > +       /* Queues in a queue group must share the same address
> > > space
> > > (vm) */
> > > +       multi_queue.value = exec_queues[0];
> > > +       vm2 = xe_vm_create(fd, 0, 0);
> > > +       igt_assert_eq(__xe_exec_queue_create(fd, vm2, 1, 1, eci,
> > > ext,
> > > &val), -EINVAL);
> > > +       xe_vm_destroy(fd, vm2);
> > > +
> > > +       /* Secondary queues must map to same engine instances as
> > > primary queue */
> > > +       if (n > 1)
> > > +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 1,
> > > n,
> > > eci, ext, &val), -EINVAL);
> > > +
> > > +       for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
> > > +               exec_queues[i] = xe_exec_queue_create(fd, vm,
> > > eci,
> > > ext);
> > > +
> > > +       /* Queue group limit check */
> > > +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci,
> > > ext,
> > > &val), -EINVAL);
> > > +
> > > +       /* Secondary queues can't be replaced once successfully
> > > created */
> > > +       xe_exec_queue_destroy(fd, exec_queues[1]);
> > > +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci,
> > > ext,
> > > &val), -EINVAL);
> > > +
> > > +       /* Primary queue can be destroyed before all secondary
> > > queues
> > > are destroyed */
> > > +       xe_exec_queue_destroy(fd, exec_queues[0]);
> > > +
> > > +       for (i = 2; i < MAX_N_EXEC_QUEUES; i++)
> > > +               xe_exec_queue_destroy(fd, exec_queues[i]);
> > > +
> > > +       /* Validate with multiple num_placements */
> > > +       if (n > 1) {
> > > +               multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> > > +               multi_queue.base.next_extension = 0;
> > > +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 1,
> > > n,
> > > eci, ext, &exec_queues[0]), 0);
> > 
> > This is the logical mask we're passing to GuC right? The
> > expectation
> > here is that GuC will see that these are part of the same multi
> > queue
> > group and make sure they go to the same instance right? If so, it
> > would
> > be nice to have a comment somewhere, either here or in the driver
> > indicating this.
> > 
> 
> It is not multi-queue specific. Yah, it is for guc to choose an
> engine
> instance (from the placements specified) for a context (regular or a
> multi-queue context). Just adding this sanity here to ensure multi-
> queue
> doesn't break if num_placements are used.

Makes sense then.

> 
> > Is there any requirement (or should there be) that the
> > num_placements
> > be the same between the primary and secondary queue? If not, we can
> > go
> > with what you have here. If so though, maybe we want to add a case
> > where the "n" we pass below is different from the one we pass for
> > the
> > primary queue above.
> 
> That test is already added few lines above. Look for,
> 
>          /* Secondary queues must map to same engine instances as
> primary queue */
>          if (n > 1)
>                  igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n,
> eci, ext, &val), -EINVAL);

Ah you're right and thanks.

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> 
> Niranjana
> 
> > 
> > Thanks,
> > Stuart
> > 
> > > +
> > > +               multi_queue.value = exec_queues[0];
> > > +               for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
> > > +                       igt_assert_eq(__xe_exec_queue_create(fd,
> > > vm,
> > > 1, n, eci, ext, &exec_queues[i]), 0);
> > > +
> > > +               for (i = 0; i < MAX_N_EXEC_QUEUES; i++)
> > > +                       xe_exec_queue_destroy(fd,
> > > exec_queues[i]);
> > > +       }
> > > +
> > > +       xe_vm_destroy(fd, vm);
> > > +}
> > > +
> > > +/**
> > > + * SUBTEST: sanity
> > > + * Description: Run sanity test
> > > + * Test category: functionality test
> > > + */
> > > +static void
> > > +test_sanity(int fd, int gt, int class)
> > > +{
> > > +       __test_sanity(fd, gt, class);
> > > +}
> > > +
> > > +igt_main
> > > +{
> > > +       int fd, gt, class;
> > > +
> > > +       igt_fixture {
> > > +               fd = drm_open_driver(DRIVER_XE);
> > > +               igt_require(intel_graphics_ver(intel_get_drm_devi
> > > d(fd
> > > )) >= IP_VER(35, 0));
> > > +       }
> > > +
> > > +       igt_subtest_f("sanity")
> > > +               xe_for_each_gt(fd, gt)
> > > +                       xe_for_each_multi_queue_engine_class(clas
> > > s)
> > > +                               test_sanity(fd, gt, class);
> > > +
> > > +       igt_fixture
> > > +               drm_close_driver(fd);
> > > +}
> > > diff --git a/tests/meson.build b/tests/meson.build
> > > index ecc0f4c7f..58d223937 100644
> > > --- a/tests/meson.build
> > > +++ b/tests/meson.build
> > > @@ -297,6 +297,7 @@ intel_xe_progs = [
> > >         'xe_exec_compute_mode',
> > >         'xe_exec_fault_mode',
> > >         'xe_exec_mix_modes',
> > > +       'xe_exec_multi_queue',
> > >         'xe_exec_queue_property',
> > >         'xe_exec_reset',
> > >         'xe_exec_sip',
> > 

[PATCH v2 04/19] tests/intel/xe_exec_multi_queue: Validate exec submissions

[Niranjana Vishwanathapura]

Validate multi queue feature with different queue group size
and with execbuf submissions.

v2: Use BASE_ADDRESS macro for address (Sai)

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 199 ++++++++++++++++++++++++++++++
 1 file changed, 199 insertions(+)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index 03b920dc8..977b4e7a0 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -13,16 +13,21 @@
 
 #include "igt.h"
 #include "xe_drm.h"
+#include "lib/igt_syncobj.h"
 
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 
 #define MAX_N_EXEC_QUEUES	64
 
+#define USERPTR			(0x1 << 0)
+
 #define MAX_INSTANCE 9
 
 #define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE)
 
+#define BASE_ADDRESS	0x1a0000
+
 static void
 __test_sanity(int fd, int gt, int class)
 {
@@ -144,8 +149,175 @@ test_sanity(int fd, int gt, int class)
 	__test_sanity(fd, gt, class);
 }
 
+static void
+test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
+		 int n_exec_queues, int n_execs, unsigned int flags)
+{
+	struct drm_xe_sync sync[2] = {
+		{ .flags = DRM_XE_SYNC_TYPE_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+		{ .flags = DRM_XE_SYNC_TYPE_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL, },
+	};
+
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 2,
+		.syncs = to_user_pointer(sync),
+	};
+	uint32_t vm;
+	uint64_t addr = BASE_ADDRESS;
+	uint32_t exec_queues[MAX_N_EXEC_QUEUES];
+	uint32_t syncobjs[MAX_N_EXEC_QUEUES];
+	uint32_t bind_syncobj;
+	size_t bo_size;
+	uint32_t bo = 0;
+	struct {
+		uint32_t batch[16];
+		uint64_t pad;
+		uint32_t data;
+	} *data;
+	int i, b;
+
+	igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
+	vm = xe_vm_create(fd, 0, 0);
+	bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
+
+	if (flags & USERPTR) {
+		data = aligned_alloc(xe_get_default_alignment(fd), bo_size);
+		igt_assert(data);
+
+		memset(data, 0, bo_size);
+	} else {
+		bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
+				  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+		data = xe_bo_map(fd, bo, bo_size);
+	}
+
+	for (i = 0; i < n_exec_queues; i++) {
+		struct drm_xe_ext_set_property multi_queue = {
+			.base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+			.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
+		};
+		uint64_t ext = to_user_pointer(&multi_queue);
+
+		multi_queue.value = i ? exec_queues[0] : DRM_XE_MULTI_GROUP_CREATE;
+		igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, num_placement, eci,
+						     ext, &exec_queues[i]), 0);
+
+		syncobjs[i] = syncobj_create(fd, 0);
+	};
+
+	bind_syncobj = syncobj_create(fd, 0);
+	sync[0].handle = bind_syncobj;
+	if (bo)
+		xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1);
+	else
+		xe_vm_bind_userptr_async(fd, vm, 0, to_user_pointer(data),
+					 addr, bo_size, sync, 1);
+
+	for (i = 0; i < n_execs; i++) {
+		uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
+		uint64_t batch_addr = addr + batch_offset;
+		uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
+		uint64_t sdi_addr = addr + sdi_offset;
+		int e = i % n_exec_queues;
+
+		b = 0;
+		data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+		data[i].batch[b++] = sdi_addr;
+		data[i].batch[b++] = sdi_addr >> 32;
+		data[i].batch[b++] = 0xc0ffee;
+		data[i].batch[b++] = MI_BATCH_BUFFER_END;
+		igt_assert(b <= ARRAY_SIZE(data[i].batch));
+
+		sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
+		sync[0].handle = bind_syncobj;
+		sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+		sync[1].handle = syncobjs[e];
+
+		exec.exec_queue_id = exec_queues[e];
+		exec.address = batch_addr;
+		if (e != i)
+			syncobj_reset(fd, &syncobjs[e], 1);
+
+		xe_exec(fd, &exec);
+	}
+
+	for (i = 0; i < n_exec_queues && i < n_execs; i++)
+		igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0, NULL));
+
+	igt_assert(syncobj_wait(fd, &bind_syncobj, 1, INT64_MAX, 0, NULL));
+	sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
+	syncobj_reset(fd, &sync[0].handle, 1);
+	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
+	igt_assert(syncobj_wait(fd, &sync[0].handle, 1,	INT64_MAX, 0, NULL));
+
+	for (i = 0; i < n_execs; i++)
+		igt_assert_eq(data[i].data, 0xc0ffee);
+
+	for (i = 0; i < n_exec_queues; i++) {
+		syncobj_destroy(fd, syncobjs[i]);
+		xe_exec_queue_destroy(fd, exec_queues[i]);
+	}
+
+	if (bo) {
+		munmap(data, bo_size);
+		gem_close(fd, bo);
+	} else {
+		free(data);
+	}
+
+	syncobj_destroy(fd, bind_syncobj);
+	xe_vm_destroy(fd, vm);
+}
+
+/**
+ * SUBTEST: one-queue-%s
+ * Description: Run %arg[1] test with one exec queue
+ * Test category: functionality test
+ *
+ * SUBTEST: two-queues-%s
+ * Description: Run %arg[1] test with two exec queues
+ * Test category: functionality test
+ *
+ * SUBTEST: many-queues-%s
+ * Description: Run %arg[1] test with many exec queues
+ * Test category: stress test
+ *
+ * SUBTEST: max-queues-%s
+ * Description: Run %arg[1] test with max exec queues
+ * Test category: stress test
+ *
+ * SUBTEST: many-execs-%s
+ * Description: Run %arg[1] test with many exec submissions per exec queue
+ * Test category: functionality test
+ *
+ * SUBTEST: few-execs-%s
+ * Description: Run %arg[1] test with exec submissions only on few exec queues
+ * Test category: functionality test
+ *
+ * arg[1]:
+ *
+ * @basic:					basic
+ * @userptr:					userptr
+ */
+static void
+test_exec(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
+	  int n_exec_queues, int n_execs, unsigned int flags)
+{
+	test_legacy_mode(fd, eci, num_placement, n_exec_queues, n_execs, flags);
+}
+
 igt_main
 {
+	struct drm_xe_engine_class_instance *hwe;
+	const struct section {
+		const char *name;
+		unsigned int flags;
+	} sections[] = {
+		{ "basic", 0 },
+		{ "userptr", USERPTR },
+		{ NULL },
+	};
 	int fd, gt, class;
 
 	igt_fixture {
@@ -158,6 +330,33 @@ igt_main
 			xe_for_each_multi_queue_engine_class(class)
 				test_sanity(fd, gt, class);
 
+	for (const struct section *s = sections; s->name; s++) {
+		igt_subtest_f("one-queue-%s", s->name)
+			xe_for_each_multi_queue_engine(fd, hwe)
+				test_exec(fd, hwe, 1, 1, 1, s->flags);
+
+		igt_subtest_f("two-queues-%s", s->name)
+			xe_for_each_multi_queue_engine(fd, hwe)
+				test_exec(fd, hwe, 1, 2, 2, s->flags);
+
+		igt_subtest_f("many-queues-%s", s->name)
+			xe_for_each_multi_queue_engine(fd, hwe)
+				test_exec(fd, hwe, 1, 16, 16, s->flags);
+
+		igt_subtest_f("max-queues-%s", s->name)
+			xe_for_each_multi_queue_engine(fd, hwe)
+				test_exec(fd, hwe, 1, MAX_N_EXEC_QUEUES,
+					  MAX_N_EXEC_QUEUES, s->flags);
+
+		igt_subtest_f("many-execs-%s", s->name)
+			xe_for_each_multi_queue_engine(fd, hwe)
+				test_exec(fd, hwe, 1, 16, 64, s->flags);
+
+		igt_subtest_f("few-execs-%s", s->name)
+			xe_for_each_multi_queue_engine(fd, hwe)
+				test_exec(fd, hwe, 1, 16, 8, s->flags);
+	}
+
 	igt_fixture
 		drm_close_driver(fd);
 }
-- 
2.43.0

RE: [PATCH v2 04/19] tests/intel/xe_exec_multi_queue: Validate exec submissions

[Ch, Sai Gowtham]

>-----Original Message-----
>From: Vishwanathapura, Niranjana <niranjana.vishwanathapura@intel.com>
>Sent: Friday, November 21, 2025 9:27 AM
>To: igt-dev@lists.freedesktop.org
>Cc: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>; Dandamudi, Priyanka
><priyanka.dandamudi@intel.com>; kamil.konieczny@linux.intel.com
>Subject: [PATCH v2 04/19] tests/intel/xe_exec_multi_queue: Validate exec
>submissions
>
>Validate multi queue feature with different queue group size and with execbuf
>submissions.
>
>v2: Use BASE_ADDRESS macro for address (Sai)
>
>Signed-off-by: Niranjana Vishwanathapura
><niranjana.vishwanathapura@intel.com>
Looks good to me.
Reviewed-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>---
> tests/intel/xe_exec_multi_queue.c | 199 ++++++++++++++++++++++++++++++
> 1 file changed, 199 insertions(+)
>
>diff --git a/tests/intel/xe_exec_multi_queue.c
>b/tests/intel/xe_exec_multi_queue.c
>index 03b920dc8..977b4e7a0 100644
>--- a/tests/intel/xe_exec_multi_queue.c
>+++ b/tests/intel/xe_exec_multi_queue.c
>@@ -13,16 +13,21 @@
>
> #include "igt.h"
> #include "xe_drm.h"
>+#include "lib/igt_syncobj.h"
>
> #include "xe/xe_ioctl.h"
> #include "xe/xe_query.h"
>
> #define MAX_N_EXEC_QUEUES	64
>
>+#define USERPTR			(0x1 << 0)
>+
> #define MAX_INSTANCE 9
>
> #define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE)
>
>+#define BASE_ADDRESS	0x1a0000
>+
> static void
> __test_sanity(int fd, int gt, int class)  { @@ -144,8 +149,175 @@ test_sanity(int
>fd, int gt, int class)
> 	__test_sanity(fd, gt, class);
> }
>
>+static void
>+test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int
>num_placement,
>+		 int n_exec_queues, int n_execs, unsigned int flags) {
>+	struct drm_xe_sync sync[2] = {
>+		{ .flags = DRM_XE_SYNC_TYPE_SYNCOBJ |
>DRM_XE_SYNC_FLAG_SIGNAL, },
>+		{ .flags = DRM_XE_SYNC_TYPE_SYNCOBJ |
>DRM_XE_SYNC_FLAG_SIGNAL, },
>+	};
>+
>+	struct drm_xe_exec exec = {
>+		.num_batch_buffer = 1,
>+		.num_syncs = 2,
>+		.syncs = to_user_pointer(sync),
>+	};
>+	uint32_t vm;
>+	uint64_t addr = BASE_ADDRESS;
>+	uint32_t exec_queues[MAX_N_EXEC_QUEUES];
>+	uint32_t syncobjs[MAX_N_EXEC_QUEUES];
>+	uint32_t bind_syncobj;
>+	size_t bo_size;
>+	uint32_t bo = 0;
>+	struct {
>+		uint32_t batch[16];
>+		uint64_t pad;
>+		uint32_t data;
>+	} *data;
>+	int i, b;
>+
>+	igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
>+	vm = xe_vm_create(fd, 0, 0);
>+	bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
>+
>+	if (flags & USERPTR) {
>+		data = aligned_alloc(xe_get_default_alignment(fd), bo_size);
>+		igt_assert(data);
>+
>+		memset(data, 0, bo_size);
>+	} else {
>+		bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd,
>eci[0].gt_id),
>+
>DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>+		data = xe_bo_map(fd, bo, bo_size);
>+	}
>+
>+	for (i = 0; i < n_exec_queues; i++) {
>+		struct drm_xe_ext_set_property multi_queue = {
>+			.base.name =
>DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
>+			.property =
>DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
>+		};
>+		uint64_t ext = to_user_pointer(&multi_queue);
>+
>+		multi_queue.value = i ? exec_queues[0] :
>DRM_XE_MULTI_GROUP_CREATE;
>+		igt_assert_eq(__xe_exec_queue_create(fd, vm, 1,
>num_placement, eci,
>+						     ext, &exec_queues[i]), 0);
>+
>+		syncobjs[i] = syncobj_create(fd, 0);
>+	};
>+
>+	bind_syncobj = syncobj_create(fd, 0);
>+	sync[0].handle = bind_syncobj;
>+	if (bo)
>+		xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, sync, 1);
>+	else
>+		xe_vm_bind_userptr_async(fd, vm, 0, to_user_pointer(data),
>+					 addr, bo_size, sync, 1);
>+
>+	for (i = 0; i < n_execs; i++) {
>+		uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
>+		uint64_t batch_addr = addr + batch_offset;
>+		uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
>+		uint64_t sdi_addr = addr + sdi_offset;
>+		int e = i % n_exec_queues;
>+
>+		b = 0;
>+		data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
>+		data[i].batch[b++] = sdi_addr;
>+		data[i].batch[b++] = sdi_addr >> 32;
>+		data[i].batch[b++] = 0xc0ffee;
>+		data[i].batch[b++] = MI_BATCH_BUFFER_END;
>+		igt_assert(b <= ARRAY_SIZE(data[i].batch));
>+
>+		sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
>+		sync[0].handle = bind_syncobj;
>+		sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>+		sync[1].handle = syncobjs[e];
>+
>+		exec.exec_queue_id = exec_queues[e];
>+		exec.address = batch_addr;
>+		if (e != i)
>+			syncobj_reset(fd, &syncobjs[e], 1);
>+
>+		xe_exec(fd, &exec);
>+	}
>+
>+	for (i = 0; i < n_exec_queues && i < n_execs; i++)
>+		igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0,
>NULL));
>+
>+	igt_assert(syncobj_wait(fd, &bind_syncobj, 1, INT64_MAX, 0, NULL));
>+	sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
>+	syncobj_reset(fd, &sync[0].handle, 1);
>+	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
>+	igt_assert(syncobj_wait(fd, &sync[0].handle, 1,	INT64_MAX, 0, NULL));
>+
>+	for (i = 0; i < n_execs; i++)
>+		igt_assert_eq(data[i].data, 0xc0ffee);
>+
>+	for (i = 0; i < n_exec_queues; i++) {
>+		syncobj_destroy(fd, syncobjs[i]);
>+		xe_exec_queue_destroy(fd, exec_queues[i]);
>+	}
>+
>+	if (bo) {
>+		munmap(data, bo_size);
>+		gem_close(fd, bo);
>+	} else {
>+		free(data);
>+	}
>+
>+	syncobj_destroy(fd, bind_syncobj);
>+	xe_vm_destroy(fd, vm);
>+}
>+
>+/**
>+ * SUBTEST: one-queue-%s
>+ * Description: Run %arg[1] test with one exec queue
>+ * Test category: functionality test
>+ *
>+ * SUBTEST: two-queues-%s
>+ * Description: Run %arg[1] test with two exec queues
>+ * Test category: functionality test
>+ *
>+ * SUBTEST: many-queues-%s
>+ * Description: Run %arg[1] test with many exec queues
>+ * Test category: stress test
>+ *
>+ * SUBTEST: max-queues-%s
>+ * Description: Run %arg[1] test with max exec queues
>+ * Test category: stress test
>+ *
>+ * SUBTEST: many-execs-%s
>+ * Description: Run %arg[1] test with many exec submissions per exec
>+queue
>+ * Test category: functionality test
>+ *
>+ * SUBTEST: few-execs-%s
>+ * Description: Run %arg[1] test with exec submissions only on few exec
>+queues
>+ * Test category: functionality test
>+ *
>+ * arg[1]:
>+ *
>+ * @basic:					basic
>+ * @userptr:					userptr
>+ */
>+static void
>+test_exec(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
>+	  int n_exec_queues, int n_execs, unsigned int flags) {
>+	test_legacy_mode(fd, eci, num_placement, n_exec_queues, n_execs,
>+flags); }
>+
> igt_main
> {
>+	struct drm_xe_engine_class_instance *hwe;
>+	const struct section {
>+		const char *name;
>+		unsigned int flags;
>+	} sections[] = {
>+		{ "basic", 0 },
>+		{ "userptr", USERPTR },
>+		{ NULL },
>+	};
> 	int fd, gt, class;
>
> 	igt_fixture {
>@@ -158,6 +330,33 @@ igt_main
> 			xe_for_each_multi_queue_engine_class(class)
> 				test_sanity(fd, gt, class);
>
>+	for (const struct section *s = sections; s->name; s++) {
>+		igt_subtest_f("one-queue-%s", s->name)
>+			xe_for_each_multi_queue_engine(fd, hwe)
>+				test_exec(fd, hwe, 1, 1, 1, s->flags);
>+
>+		igt_subtest_f("two-queues-%s", s->name)
>+			xe_for_each_multi_queue_engine(fd, hwe)
>+				test_exec(fd, hwe, 1, 2, 2, s->flags);
>+
>+		igt_subtest_f("many-queues-%s", s->name)
>+			xe_for_each_multi_queue_engine(fd, hwe)
>+				test_exec(fd, hwe, 1, 16, 16, s->flags);
>+
>+		igt_subtest_f("max-queues-%s", s->name)
>+			xe_for_each_multi_queue_engine(fd, hwe)
>+				test_exec(fd, hwe, 1, MAX_N_EXEC_QUEUES,
>+					  MAX_N_EXEC_QUEUES, s->flags);
>+
>+		igt_subtest_f("many-execs-%s", s->name)
>+			xe_for_each_multi_queue_engine(fd, hwe)
>+				test_exec(fd, hwe, 1, 16, 64, s->flags);
>+
>+		igt_subtest_f("few-execs-%s", s->name)
>+			xe_for_each_multi_queue_engine(fd, hwe)
>+				test_exec(fd, hwe, 1, 16, 8, s->flags);
>+	}
>+
> 	igt_fixture
> 		drm_close_driver(fd);
> }
>--
>2.43.0

Re: [PATCH v2 04/19] tests/intel/xe_exec_multi_queue: Validate exec submissions

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Validate multi queue feature with different queue group size
> and with execbuf submissions.
> 
> v2: Use BASE_ADDRESS macro for address (Sai)
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> ---
>  tests/intel/xe_exec_multi_queue.c | 199
> ++++++++++++++++++++++++++++++
>  1 file changed, 199 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index 03b920dc8..977b4e7a0 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -13,16 +13,21 @@
>  
>  #include "igt.h"
>  #include "xe_drm.h"
> +#include "lib/igt_syncobj.h"
>  
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  
>  #define MAX_N_EXEC_QUEUES      64
>  
> +#define USERPTR                        (0x1 << 0)
> +
>  #define MAX_INSTANCE 9
>  
>  #define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE)
>  
> +#define BASE_ADDRESS   0x1a0000
> +
>  static void
>  __test_sanity(int fd, int gt, int class)
>  {
> @@ -144,8 +149,175 @@ test_sanity(int fd, int gt, int class)
>         __test_sanity(fd, gt, class);
>  }
>  
> +static void
> +test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
> int num_placement,
> +                int n_exec_queues, int n_execs, unsigned int flags)
> +{
> +       struct drm_xe_sync sync[2] = {
> +               { .flags = DRM_XE_SYNC_TYPE_SYNCOBJ |
> DRM_XE_SYNC_FLAG_SIGNAL, },
> +               { .flags = DRM_XE_SYNC_TYPE_SYNCOBJ |
> DRM_XE_SYNC_FLAG_SIGNAL, },
> +       };
> +
> +       struct drm_xe_exec exec = {
> +               .num_batch_buffer = 1,
> +               .num_syncs = 2,
> +               .syncs = to_user_pointer(sync),
> +       };
> +       uint32_t vm;
> +       uint64_t addr = BASE_ADDRESS;
> +       uint32_t exec_queues[MAX_N_EXEC_QUEUES];
> +       uint32_t syncobjs[MAX_N_EXEC_QUEUES];
> +       uint32_t bind_syncobj;
> +       size_t bo_size;
> +       uint32_t bo = 0;
> +       struct {
> +               uint32_t batch[16];
> +               uint64_t pad;
> +               uint32_t data;
> +       } *data;
> +       int i, b;
> +
> +       igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
> +       vm = xe_vm_create(fd, 0, 0);
> +       bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
> +
> +       if (flags & USERPTR) {
> +               data = aligned_alloc(xe_get_default_alignment(fd),
> bo_size);
> +               igt_assert(data);
> +
> +               memset(data, 0, bo_size);
> +       } else {
> +               bo = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> +                                
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +               data = xe_bo_map(fd, bo, bo_size);
> +       }
> +
> +       for (i = 0; i < n_exec_queues; i++) {
> +               struct drm_xe_ext_set_property multi_queue = {
> +                       .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +                       .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
> +               };
> +               uint64_t ext = to_user_pointer(&multi_queue);
> +
> +               multi_queue.value = i ? exec_queues[0] :
> DRM_XE_MULTI_GROUP_CREATE;
> +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 1,
> num_placement, eci,
> +                                                    ext,
> &exec_queues[i]), 0);
> +
> +               syncobjs[i] = syncobj_create(fd, 0);
> +       };
> +
> +       bind_syncobj = syncobj_create(fd, 0);
> +       sync[0].handle = bind_syncobj;
> +       if (bo)
> +               xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size,
> sync, 1);
> +       else
> +               xe_vm_bind_userptr_async(fd, vm, 0,
> to_user_pointer(data),
> +                                        addr, bo_size, sync, 1);
> +
> +       for (i = 0; i < n_execs; i++) {
> +               uint64_t batch_offset = (char *)&data[i].batch -
> (char *)data;
> +               uint64_t batch_addr = addr + batch_offset;
> +               uint64_t sdi_offset = (char *)&data[i].data - (char
> *)data;
> +               uint64_t sdi_addr = addr + sdi_offset;
> +               int e = i % n_exec_queues;
> +
> +               b = 0;
> +               data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> +               data[i].batch[b++] = sdi_addr;
> +               data[i].batch[b++] = sdi_addr >> 32;
> +               data[i].batch[b++] = 0xc0ffee;
> +               data[i].batch[b++] = MI_BATCH_BUFFER_END;
> +               igt_assert(b <= ARRAY_SIZE(data[i].batch));
> +
> +               sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> +               sync[0].handle = bind_syncobj;
> +               sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> +               sync[1].handle = syncobjs[e];
> +
> +               exec.exec_queue_id = exec_queues[e];
> +               exec.address = batch_addr;
> +               if (e != i)
> +                       syncobj_reset(fd, &syncobjs[e], 1);
> +
> +               xe_exec(fd, &exec);
> +       }
> +
> +       for (i = 0; i < n_exec_queues && i < n_execs; i++)
> +               igt_assert(syncobj_wait(fd, &syncobjs[i], 1,
> INT64_MAX, 0, NULL));
> +
> +       igt_assert(syncobj_wait(fd, &bind_syncobj, 1, INT64_MAX, 0,
> NULL));
> +       sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> +       syncobj_reset(fd, &sync[0].handle, 1);
> +       xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
> +       igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0,
> NULL));
> +
> +       for (i = 0; i < n_execs; i++)
> +               igt_assert_eq(data[i].data, 0xc0ffee);
> +
> +       for (i = 0; i < n_exec_queues; i++) {
> +               syncobj_destroy(fd, syncobjs[i]);
> +               xe_exec_queue_destroy(fd, exec_queues[i]);
> +       }
> +
> +       if (bo) {
> +               munmap(data, bo_size);
> +               gem_close(fd, bo);
> +       } else {
> +               free(data);
> +       }
> +
> +       syncobj_destroy(fd, bind_syncobj);
> +       xe_vm_destroy(fd, vm);
> +}
> +
> +/**
> + * SUBTEST: one-queue-%s
> + * Description: Run %arg[1] test with one exec queue
> + * Test category: functionality test
> + *
> + * SUBTEST: two-queues-%s
> + * Description: Run %arg[1] test with two exec queues
> + * Test category: functionality test
> + *
> + * SUBTEST: many-queues-%s
> + * Description: Run %arg[1] test with many exec queues
> + * Test category: stress test
> + *
> + * SUBTEST: max-queues-%s
> + * Description: Run %arg[1] test with max exec queues
> + * Test category: stress test
> + *
> + * SUBTEST: many-execs-%s
> + * Description: Run %arg[1] test with many exec submissions per exec
> queue
> + * Test category: functionality test
> + *
> + * SUBTEST: few-execs-%s
> + * Description: Run %arg[1] test with exec submissions only on few
> exec queues
> + * Test category: functionality test
> + *
> + * arg[1]:
> + *
> + * @basic:                                     basic
> + * @userptr:                                   userptr
> + */
> +static void
> +test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement,
> +         int n_exec_queues, int n_execs, unsigned int flags)
> +{
> +       test_legacy_mode(fd, eci, num_placement, n_exec_queues,
> n_execs, flags);
> +}
> +
>  igt_main
>  {
> +       struct drm_xe_engine_class_instance *hwe;
> +       const struct section {
> +               const char *name;
> +               unsigned int flags;
> +       } sections[] = {
> +               { "basic", 0 },
> +               { "userptr", USERPTR },
> +               { NULL },
> +       };
>         int fd, gt, class;
>  
>         igt_fixture {
> @@ -158,6 +330,33 @@ igt_main
>                         xe_for_each_multi_queue_engine_class(class)
>                                 test_sanity(fd, gt, class);
>  
> +       for (const struct section *s = sections; s->name; s++) {
> +               igt_subtest_f("one-queue-%s", s->name)
> +                       xe_for_each_multi_queue_engine(fd, hwe)
> +                               test_exec(fd, hwe, 1, 1, 1, s-
> >flags);
> +
> +               igt_subtest_f("two-queues-%s", s->name)
> +                       xe_for_each_multi_queue_engine(fd, hwe)
> +                               test_exec(fd, hwe, 1, 2, 2, s-
> >flags);
> +
> +               igt_subtest_f("many-queues-%s", s->name)
> +                       xe_for_each_multi_queue_engine(fd, hwe)
> +                               test_exec(fd, hwe, 1, 16, 16, s-
> >flags);
> +
> +               igt_subtest_f("max-queues-%s", s->name)
> +                       xe_for_each_multi_queue_engine(fd, hwe)
> +                               test_exec(fd, hwe, 1,
> MAX_N_EXEC_QUEUES,
> +                                         MAX_N_EXEC_QUEUES, s-
> >flags);
> +
> +               igt_subtest_f("many-execs-%s", s->name)
> +                       xe_for_each_multi_queue_engine(fd, hwe)
> +                               test_exec(fd, hwe, 1, 16, 64, s-
> >flags);
> +
> +               igt_subtest_f("few-execs-%s", s->name)
> +                       xe_for_each_multi_queue_engine(fd, hwe)
> +                               test_exec(fd, hwe, 1, 16, 8, s-
> >flags);
> +       }
> +
>         igt_fixture
>                 drm_close_driver(fd);
>  }

[PATCH v2 05/19] tests/intel/xe_exec_multi_queue: Validate queue priority setting

[Niranjana Vishwanathapura]

Validate setting priority of queues within the multi queue
group.

v2: Add and use XE_EXEC_QUEUE_NUM_PRIORITIES (priyanka)

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 67 +++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index 977b4e7a0..3bbcf7975 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -18,9 +18,15 @@
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 
+#define XE_EXEC_QUEUE_PRIORITY_LOW	0
+#define XE_EXEC_QUEUE_PRIORITY_NORMAL	1
+#define XE_EXEC_QUEUE_PRIORITY_HIGH	2
+#define XE_EXEC_QUEUE_NUM_PRIORITIES	3
+
 #define MAX_N_EXEC_QUEUES	64
 
 #define USERPTR			(0x1 << 0)
+#define PRIORITY		(0x1 << 1)
 
 #define MAX_INSTANCE 9
 
@@ -37,6 +43,15 @@ __test_sanity(int fd, int gt, int class)
 		.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
 		.value = DRM_XE_MULTI_GROUP_CREATE,
 	};
+	struct drm_xe_ext_set_property mq_priority = {
+		.base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+		.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
+	};
+	struct drm_xe_ext_set_property priority = {
+		.base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+		.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY,
+		.value = XE_EXEC_QUEUE_PRIORITY_NORMAL,
+	};
 	uint64_t invalid_flag = 0, ext = to_user_pointer(&multi_queue);
 	struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
 	struct drm_xe_engine_class_instance *hwe;
@@ -77,6 +92,11 @@ __test_sanity(int fd, int gt, int class)
 	multi_queue.base.next_extension = to_user_pointer(&multi_queue);
 	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -EINVAL);
 
+	/* Setting other queue properties are valid for Q0 */
+	multi_queue.base.next_extension = to_user_pointer(&priority);
+	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
+	xe_exec_queue_destroy(fd, exec_queues[0]);
+
 	/* Adding queues to group after primary is destroyed is invalid */
 	multi_queue.base.next_extension = 0;
 	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
@@ -105,6 +125,11 @@ __test_sanity(int fd, int gt, int class)
 	if (n > 1)
 		igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n, eci, ext, &val), -EINVAL);
 
+	/* Setting properties (other than MULTI_QUEUE_PRIORITY) is invalid for secondary queues */
+	multi_queue.base.next_extension = to_user_pointer(&priority);
+	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -EINVAL);
+
+	multi_queue.base.next_extension = 0;
 	for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
 		exec_queues[i] = xe_exec_queue_create(fd, vm, eci, ext);
 
@@ -135,6 +160,37 @@ __test_sanity(int fd, int gt, int class)
 			xe_exec_queue_destroy(fd, exec_queues[i]);
 	}
 
+	/* MQ priority is not valid for regular queues */
+	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci,
+					     to_user_pointer(&mq_priority), &val), -EINVAL);
+
+	/* MQ priority validation */
+	multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
+	multi_queue.base.next_extension = to_user_pointer(&mq_priority);
+	mq_priority.value = XE_EXEC_QUEUE_NUM_PRIORITIES;
+	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -EINVAL);
+
+	mq_priority.value = XE_EXEC_QUEUE_PRIORITY_HIGH;
+	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
+	multi_queue.value = exec_queues[0];
+	exec_queues[1] = xe_exec_queue_create(fd, vm, eci, ext);
+	xe_exec_queue_destroy(fd, exec_queues[1]);
+	xe_exec_queue_destroy(fd, exec_queues[0]);
+
+	igt_fork(child, 1) {
+		igt_drop_root();
+
+		/* Tests MULTI_QUEUE_PRIORITY property by dropping root permissions */
+		multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
+		mq_priority.value = XE_EXEC_QUEUE_PRIORITY_HIGH;
+		exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
+		multi_queue.value = exec_queues[0];
+		exec_queues[1] = xe_exec_queue_create(fd, vm, eci, ext);
+		xe_exec_queue_destroy(fd, exec_queues[1]);
+		xe_exec_queue_destroy(fd, exec_queues[0]);
+	}
+	igt_waitchildren();
+
 	xe_vm_destroy(fd, vm);
 }
 
@@ -197,8 +253,17 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
 			.base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
 			.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
 		};
+		struct drm_xe_ext_set_property mq_priority = {
+			.base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+			.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
+		};
 		uint64_t ext = to_user_pointer(&multi_queue);
 
+		if (flags & PRIORITY) {
+			multi_queue.base.next_extension = to_user_pointer(&mq_priority);
+			mq_priority.value = XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2);
+		}
+
 		multi_queue.value = i ? exec_queues[0] : DRM_XE_MULTI_GROUP_CREATE;
 		igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, num_placement, eci,
 						     ext, &exec_queues[i]), 0);
@@ -299,6 +364,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
  *
  * @basic:					basic
  * @userptr:					userptr
+ * @priority:					priority
  */
 static void
 test_exec(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
@@ -316,6 +382,7 @@ igt_main
 	} sections[] = {
 		{ "basic", 0 },
 		{ "userptr", USERPTR },
+		{ "priority", PRIORITY },
 		{ NULL },
 	};
 	int fd, gt, class;
-- 
2.43.0

RE: [PATCH v2 05/19] tests/intel/xe_exec_multi_queue: Validate queue priority setting

[Dandamudi, Priyanka]

> -----Original Message-----
> From: Vishwanathapura, Niranjana <niranjana.vishwanathapura@intel.com>
> Sent: 21 November 2025 09:27 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>; kamil.konieczny@linux.intel.com
> Subject: [PATCH v2 05/19] tests/intel/xe_exec_multi_queue: Validate queue
> priority setting
> 
> Validate setting priority of queues within the multi queue group.
> 
> v2: Add and use XE_EXEC_QUEUE_NUM_PRIORITIES (priyanka)
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> ---
>  tests/intel/xe_exec_multi_queue.c | 67
> +++++++++++++++++++++++++++++++
>  1 file changed, 67 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index 977b4e7a0..3bbcf7975 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -18,9 +18,15 @@
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
> 
> +#define XE_EXEC_QUEUE_PRIORITY_LOW	0
> +#define XE_EXEC_QUEUE_PRIORITY_NORMAL	1
> +#define XE_EXEC_QUEUE_PRIORITY_HIGH	2
> +#define XE_EXEC_QUEUE_NUM_PRIORITIES	3
> +
>  #define MAX_N_EXEC_QUEUES	64
> 
>  #define USERPTR			(0x1 << 0)
> +#define PRIORITY		(0x1 << 1)
> 
>  #define MAX_INSTANCE 9
> 
> @@ -37,6 +43,15 @@ __test_sanity(int fd, int gt, int class)
>  		.property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
>  		.value = DRM_XE_MULTI_GROUP_CREATE,
>  	};
> +	struct drm_xe_ext_set_property mq_priority = {
> +		.base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +		.property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> +	};
> +	struct drm_xe_ext_set_property priority = {
> +		.base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +		.property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY,
> +		.value = XE_EXEC_QUEUE_PRIORITY_NORMAL,
> +	};
>  	uint64_t invalid_flag = 0, ext = to_user_pointer(&multi_queue);
>  	struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
>  	struct drm_xe_engine_class_instance *hwe; @@ -77,6 +92,11 @@
> __test_sanity(int fd, int gt, int class)
>  	multi_queue.base.next_extension = to_user_pointer(&multi_queue);
>  	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -
> EINVAL);
> 
> +	/* Setting other queue properties are valid for Q0 */
> +	multi_queue.base.next_extension = to_user_pointer(&priority);
> +	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> +	xe_exec_queue_destroy(fd, exec_queues[0]);
> +
>  	/* Adding queues to group after primary is destroyed is invalid */
>  	multi_queue.base.next_extension = 0;
>  	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext); @@ -105,6
> +125,11 @@ __test_sanity(int fd, int gt, int class)
>  	if (n > 1)
>  		igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n, eci, ext,
> &val), -EINVAL);
> 
> +	/* Setting properties (other than MULTI_QUEUE_PRIORITY) is invalid
> for secondary queues */
> +	multi_queue.base.next_extension = to_user_pointer(&priority);
> +	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val),
> +-EINVAL);
> +
> +	multi_queue.base.next_extension = 0;
>  	for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
>  		exec_queues[i] = xe_exec_queue_create(fd, vm, eci, ext);
> 
> @@ -135,6 +160,37 @@ __test_sanity(int fd, int gt, int class)
>  			xe_exec_queue_destroy(fd, exec_queues[i]);
>  	}
> 
> +	/* MQ priority is not valid for regular queues */
> +	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci,
> +					     to_user_pointer(&mq_priority),
> &val), -EINVAL);
> +
> +	/* MQ priority validation */
> +	multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> +	multi_queue.base.next_extension = to_user_pointer(&mq_priority);
> +	mq_priority.value = XE_EXEC_QUEUE_NUM_PRIORITIES;
> +	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val),
> +-EINVAL);
> +
> +	mq_priority.value = XE_EXEC_QUEUE_PRIORITY_HIGH;
> +	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> +	multi_queue.value = exec_queues[0];
> +	exec_queues[1] = xe_exec_queue_create(fd, vm, eci, ext);
> +	xe_exec_queue_destroy(fd, exec_queues[1]);
> +	xe_exec_queue_destroy(fd, exec_queues[0]);
> +
> +	igt_fork(child, 1) {
> +		igt_drop_root();
> +
> +		/* Tests MULTI_QUEUE_PRIORITY property by dropping root
> permissions */
> +		multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> +		mq_priority.value = XE_EXEC_QUEUE_PRIORITY_HIGH;
> +		exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> +		multi_queue.value = exec_queues[0];
> +		exec_queues[1] = xe_exec_queue_create(fd, vm, eci, ext);
> +		xe_exec_queue_destroy(fd, exec_queues[1]);
> +		xe_exec_queue_destroy(fd, exec_queues[0]);
> +	}
> +	igt_waitchildren();
> +
>  	xe_vm_destroy(fd, vm);
>  }
> 
> @@ -197,8 +253,17 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>  			.base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
>  			.property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
>  		};
> +		struct drm_xe_ext_set_property mq_priority = {
> +			.base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +			.property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> +		};
>  		uint64_t ext = to_user_pointer(&multi_queue);
> 
> +		if (flags & PRIORITY) {
> +			multi_queue.base.next_extension =
> to_user_pointer(&mq_priority);
> +			mq_priority.value =
> XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2);
> +		}
> +
>  		multi_queue.value = i ? exec_queues[0] :
> DRM_XE_MULTI_GROUP_CREATE;
>  		igt_assert_eq(__xe_exec_queue_create(fd, vm, 1,
> num_placement, eci,
>  						     ext, &exec_queues[i]), 0);
> @@ -299,6 +364,7 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>   *
>   * @basic:					basic
>   * @userptr:					userptr
> + * @priority:					priority
>   */
>  static void
>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement, @@ -316,6 +382,7 @@ igt_main
>  	} sections[] = {
>  		{ "basic", 0 },
>  		{ "userptr", USERPTR },
> +		{ "priority", PRIORITY },
>  		{ NULL },
>  	};
>  	int fd, gt, class;
LGTM,
Reviewed-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> --
> 2.43.0

Re: [PATCH v2 05/19] tests/intel/xe_exec_multi_queue: Validate queue priority setting

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Validate setting priority of queues within the multi queue
> group.
> 
> v2: Add and use XE_EXEC_QUEUE_NUM_PRIORITIES (priyanka)
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> ---
>  tests/intel/xe_exec_multi_queue.c | 67
> +++++++++++++++++++++++++++++++
>  1 file changed, 67 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index 977b4e7a0..3bbcf7975 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -18,9 +18,15 @@
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
>  
> +#define XE_EXEC_QUEUE_PRIORITY_LOW     0
> +#define XE_EXEC_QUEUE_PRIORITY_NORMAL  1
> +#define XE_EXEC_QUEUE_PRIORITY_HIGH    2
> +#define XE_EXEC_QUEUE_NUM_PRIORITIES   3
> +
>  #define MAX_N_EXEC_QUEUES      64
>  
>  #define USERPTR                        (0x1 << 0)
> +#define PRIORITY               (0x1 << 1)
>  
>  #define MAX_INSTANCE 9
>  
> @@ -37,6 +43,15 @@ __test_sanity(int fd, int gt, int class)
>                 .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
>                 .value = DRM_XE_MULTI_GROUP_CREATE,
>         };
> +       struct drm_xe_ext_set_property mq_priority = {
> +               .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +               .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> +       };
> +       struct drm_xe_ext_set_property priority = {
> +               .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +               .property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY,
> +               .value = XE_EXEC_QUEUE_PRIORITY_NORMAL,
> +       };
>         uint64_t invalid_flag = 0, ext =
> to_user_pointer(&multi_queue);
>         struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
>         struct drm_xe_engine_class_instance *hwe;
> @@ -77,6 +92,11 @@ __test_sanity(int fd, int gt, int class)
>         multi_queue.base.next_extension =
> to_user_pointer(&multi_queue);
>         igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -EINVAL);
>  
> +       /* Setting other queue properties are valid for Q0 */
> +       multi_queue.base.next_extension = to_user_pointer(&priority);
> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> +       xe_exec_queue_destroy(fd, exec_queues[0]);
> +
>         /* Adding queues to group after primary is destroyed is
> invalid */
>         multi_queue.base.next_extension = 0;
>         exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> @@ -105,6 +125,11 @@ __test_sanity(int fd, int gt, int class)
>         if (n > 1)
>                 igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, n,
> eci, ext, &val), -EINVAL);
>  
> +       /* Setting properties (other than MULTI_QUEUE_PRIORITY) is
> invalid for secondary queues */
> +       multi_queue.base.next_extension = to_user_pointer(&priority);
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -EINVAL);
> +
> +       multi_queue.base.next_extension = 0;
>         for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
>                 exec_queues[i] = xe_exec_queue_create(fd, vm, eci,
> ext);
>  
> @@ -135,6 +160,37 @@ __test_sanity(int fd, int gt, int class)
>                         xe_exec_queue_destroy(fd, exec_queues[i]);
>         }
>  
> +       /* MQ priority is not valid for regular queues */
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci,
> +                                           
> to_user_pointer(&mq_priority), &val), -EINVAL);
> +
> +       /* MQ priority validation */
> +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> +       multi_queue.base.next_extension =
> to_user_pointer(&mq_priority);
> +       mq_priority.value = XE_EXEC_QUEUE_NUM_PRIORITIES;
> +       igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -EINVAL);
> +
> +       mq_priority.value = XE_EXEC_QUEUE_PRIORITY_HIGH;
> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> +       multi_queue.value = exec_queues[0];
> +       exec_queues[1] = xe_exec_queue_create(fd, vm, eci, ext);
> +       xe_exec_queue_destroy(fd, exec_queues[1]);
> +       xe_exec_queue_destroy(fd, exec_queues[0]);
> +
> +       igt_fork(child, 1) {
> +               igt_drop_root();
> +
> +               /* Tests MULTI_QUEUE_PRIORITY property by dropping
> root permissions */
> +               multi_queue.value = DRM_XE_MULTI_GROUP_CREATE;
> +               mq_priority.value = XE_EXEC_QUEUE_PRIORITY_HIGH;
> +               exec_queues[0] = xe_exec_queue_create(fd, vm, eci,
> ext);
> +               multi_queue.value = exec_queues[0];
> +               exec_queues[1] = xe_exec_queue_create(fd, vm, eci,
> ext);
> +               xe_exec_queue_destroy(fd, exec_queues[1]);
> +               xe_exec_queue_destroy(fd, exec_queues[0]);
> +       }
> +       igt_waitchildren();
> +
>         xe_vm_destroy(fd, vm);
>  }
>  
> @@ -197,8 +253,17 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>                         .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
>                         .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
>                 };
> +               struct drm_xe_ext_set_property mq_priority = {
> +                       .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +                       .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> +               };
>                 uint64_t ext = to_user_pointer(&multi_queue);
>  
> +               if (flags & PRIORITY) {
> +                       multi_queue.base.next_extension =
> to_user_pointer(&mq_priority);
> +                       mq_priority.value =
> XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2);
> +               }
> +
>                 multi_queue.value = i ? exec_queues[0] :
> DRM_XE_MULTI_GROUP_CREATE;
>                 igt_assert_eq(__xe_exec_queue_create(fd, vm, 1,
> num_placement, eci,
>                                                      ext,
> &exec_queues[i]), 0);
> @@ -299,6 +364,7 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>   *
>   * @basic:                                     basic
>   * @userptr:                                   userptr
> + * @priority:                                  priority
>   */
>  static void
>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement,
> @@ -316,6 +382,7 @@ igt_main
>         } sections[] = {
>                 { "basic", 0 },
>                 { "userptr", USERPTR },
> +               { "priority", PRIORITY },
>                 { NULL },
>         };
>         int fd, gt, class;

[PATCH v2 06/19] tests/intel/xe_exec_multi_queue: Add close-fd tests

[Niranjana Vishwanathapura]

Validate closing the file handle without destroying exec queues.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index 3bbcf7975..df60835d6 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -27,6 +27,7 @@
 
 #define USERPTR			(0x1 << 0)
 #define PRIORITY		(0x1 << 1)
+#define CLOSE_FD		(0x1 << 2)
 
 #define MAX_INSTANCE 9
 
@@ -233,6 +234,9 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
 	} *data;
 	int i, b;
 
+	if (flags & CLOSE_FD)
+		fd = drm_open_driver(DRIVER_XE);
+
 	igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
 	vm = xe_vm_create(fd, 0, 0);
 	bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
@@ -321,7 +325,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
 
 	for (i = 0; i < n_exec_queues; i++) {
 		syncobj_destroy(fd, syncobjs[i]);
-		xe_exec_queue_destroy(fd, exec_queues[i]);
+		if (!(flags & CLOSE_FD))
+			xe_exec_queue_destroy(fd, exec_queues[i]);
 	}
 
 	if (bo) {
@@ -332,7 +337,11 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
 	}
 
 	syncobj_destroy(fd, bind_syncobj);
-	xe_vm_destroy(fd, vm);
+
+	if (!(flags & CLOSE_FD))
+		xe_vm_destroy(fd, vm);
+	else
+		drm_close_driver(fd);
 }
 
 /**
@@ -365,6 +374,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
  * @basic:					basic
  * @userptr:					userptr
  * @priority:					priority
+ * @close-fd:					close fd without destroying exec queues
  */
 static void
 test_exec(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
@@ -383,6 +393,7 @@ igt_main
 		{ "basic", 0 },
 		{ "userptr", USERPTR },
 		{ "priority", PRIORITY },
+		{ "close-fd", CLOSE_FD },
 		{ NULL },
 	};
 	int fd, gt, class;
-- 
2.43.0

RE: [PATCH v2 06/19] tests/intel/xe_exec_multi_queue: Add close-fd tests

[Goyal, Nakshtra]

> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of
> Niranjana Vishwanathapura
> Sent: 21 November 2025 09:27
> To: igt-dev@lists.freedesktop.org
> Cc: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>; kamil.konieczny@linux.intel.com
> Subject: [PATCH v2 06/19] tests/intel/xe_exec_multi_queue: Add close-fd tests
> 
> Validate closing the file handle without destroying exec queues.
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
Looks good to me
Reviewed-by: Nakshtra Goyal <nakshtra.goyal@intel.com>

> ---
>  tests/intel/xe_exec_multi_queue.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index 3bbcf7975..df60835d6 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -27,6 +27,7 @@
> 
>  #define USERPTR			(0x1 << 0)
>  #define PRIORITY		(0x1 << 1)
> +#define CLOSE_FD		(0x1 << 2)
> 
>  #define MAX_INSTANCE 9
> 
> @@ -233,6 +234,9 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>  	} *data;
>  	int i, b;
> 
> +	if (flags & CLOSE_FD)
> +		fd = drm_open_driver(DRIVER_XE);
> +
>  	igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
>  	vm = xe_vm_create(fd, 0, 0);
>  	bo_size = xe_bb_size(fd, sizeof(*data) * n_execs); @@ -321,7 +325,8
> @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int
> num_place
> 
>  	for (i = 0; i < n_exec_queues; i++) {
>  		syncobj_destroy(fd, syncobjs[i]);
> -		xe_exec_queue_destroy(fd, exec_queues[i]);
> +		if (!(flags & CLOSE_FD))
> +			xe_exec_queue_destroy(fd, exec_queues[i]);
>  	}
> 
>  	if (bo) {
> @@ -332,7 +337,11 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>  	}
> 
>  	syncobj_destroy(fd, bind_syncobj);
> -	xe_vm_destroy(fd, vm);
> +
> +	if (!(flags & CLOSE_FD))
> +		xe_vm_destroy(fd, vm);
> +	else
> +		drm_close_driver(fd);
>  }
> 
>  /**
> @@ -365,6 +374,7 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>   * @basic:					basic
>   * @userptr:					userptr
>   * @priority:					priority
> + * @close-fd:					close fd without destroying
> exec queues
>   */
>  static void
>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement, @@ -383,6 +393,7 @@ igt_main
>  		{ "basic", 0 },
>  		{ "userptr", USERPTR },
>  		{ "priority", PRIORITY },
> +		{ "close-fd", CLOSE_FD },
>  		{ NULL },
>  	};
>  	int fd, gt, class;
> --
> 2.43.0

Re: [PATCH v2 06/19] tests/intel/xe_exec_multi_queue: Add close-fd tests

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Validate closing the file handle without destroying exec queues.
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> ---
>  tests/intel/xe_exec_multi_queue.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index 3bbcf7975..df60835d6 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -27,6 +27,7 @@
>  
>  #define USERPTR                        (0x1 << 0)
>  #define PRIORITY               (0x1 << 1)
> +#define CLOSE_FD               (0x1 << 2)
>  
>  #define MAX_INSTANCE 9
>  
> @@ -233,6 +234,9 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>         } *data;
>         int i, b;
>  
> +       if (flags & CLOSE_FD)
> +               fd = drm_open_driver(DRIVER_XE);
> +
>         igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
>         vm = xe_vm_create(fd, 0, 0);
>         bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
> @@ -321,7 +325,8 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>  
>         for (i = 0; i < n_exec_queues; i++) {
>                 syncobj_destroy(fd, syncobjs[i]);
> -               xe_exec_queue_destroy(fd, exec_queues[i]);
> +               if (!(flags & CLOSE_FD))
> +                       xe_exec_queue_destroy(fd, exec_queues[i]);
>         }
>  
>         if (bo) {
> @@ -332,7 +337,11 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>         }
>  
>         syncobj_destroy(fd, bind_syncobj);
> -       xe_vm_destroy(fd, vm);
> +
> +       if (!(flags & CLOSE_FD))
> +               xe_vm_destroy(fd, vm);
> +       else
> +               drm_close_driver(fd);
>  }
>  
>  /**
> @@ -365,6 +374,7 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>   * @basic:                                     basic
>   * @userptr:                                   userptr
>   * @priority:                                  priority
> + * @close-fd:                                  close fd without
> destroying exec queues
>   */
>  static void
>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement,
> @@ -383,6 +393,7 @@ igt_main
>                 { "basic", 0 },
>                 { "userptr", USERPTR },
>                 { "priority", PRIORITY },
> +               { "close-fd", CLOSE_FD },
>                 { NULL },
>         };
>         int fd, gt, class;

[PATCH v2 07/19] tests/intel/xe_exec_multi_queue: Add multiple placement test

[Niranjana Vishwanathapura]

Validate using virtual exec queues with multiple placements.

v2: Run test even with single engine instance

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index df60835d6..fdaaf78c4 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -383,6 +383,29 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
 	test_legacy_mode(fd, eci, num_placement, n_exec_queues, n_execs, flags);
 }
 
+/**
+ * SUBTEST: virtual
+ * Description: Validate virtual queues with multiple placements
+ * Test category: functionality test
+ */
+static void
+test_exec_virtual(int fd, int gt, int class)
+{
+	struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+	struct drm_xe_engine_class_instance *hwe;
+	int n = 0;
+
+	xe_for_each_engine(fd, hwe) {
+		if (hwe->engine_class != class || hwe->gt_id != gt)
+			continue;
+
+		eci[n++] = *hwe;
+	}
+	igt_assert(n);
+
+	test_exec(fd, eci, n, n, n, 0);
+}
+
 igt_main
 {
 	struct drm_xe_engine_class_instance *hwe;
@@ -408,6 +431,11 @@ igt_main
 			xe_for_each_multi_queue_engine_class(class)
 				test_sanity(fd, gt, class);
 
+	igt_subtest_f("virtual")
+		xe_for_each_gt(fd, gt)
+			xe_for_each_multi_queue_engine_class(class)
+				test_exec_virtual(fd, gt, class);
+
 	for (const struct section *s = sections; s->name; s++) {
 		igt_subtest_f("one-queue-%s", s->name)
 			xe_for_each_multi_queue_engine(fd, hwe)
-- 
2.43.0

RE: [PATCH v2 07/19] tests/intel/xe_exec_multi_queue: Add multiple placement test

[Dandamudi, Priyanka]

> -----Original Message-----
> From: Vishwanathapura, Niranjana <niranjana.vishwanathapura@intel.com>
> Sent: 21 November 2025 09:27 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>; kamil.konieczny@linux.intel.com
> Subject: [PATCH v2 07/19] tests/intel/xe_exec_multi_queue: Add multiple
> placement test
> 
> Validate using virtual exec queues with multiple placements.
> 
> v2: Run test even with single engine instance
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> ---
>  tests/intel/xe_exec_multi_queue.c | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index df60835d6..fdaaf78c4 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -383,6 +383,29 @@ test_exec(int fd, struct
> drm_xe_engine_class_instance *eci, int num_placement,
>  	test_legacy_mode(fd, eci, num_placement, n_exec_queues, n_execs,
> flags);  }
> 
> +/**
> + * SUBTEST: virtual
> + * Description: Validate virtual queues with multiple placements
> + * Test category: functionality test
> + */
> +static void
> +test_exec_virtual(int fd, int gt, int class) {
> +	struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> +	struct drm_xe_engine_class_instance *hwe;
> +	int n = 0;
> +
> +	xe_for_each_engine(fd, hwe) {
> +		if (hwe->engine_class != class || hwe->gt_id != gt)
> +			continue;
> +
> +		eci[n++] = *hwe;
> +	}
> +	igt_assert(n);
> +
> +	test_exec(fd, eci, n, n, n, 0);
> +}
> +
>  igt_main
>  {
>  	struct drm_xe_engine_class_instance *hwe; @@ -408,6 +431,11 @@
> igt_main
>  			xe_for_each_multi_queue_engine_class(class)
>  				test_sanity(fd, gt, class);
> 
> +	igt_subtest_f("virtual")
> +		xe_for_each_gt(fd, gt)
> +			xe_for_each_multi_queue_engine_class(class)
> +				test_exec_virtual(fd, gt, class);
> +
>  	for (const struct section *s = sections; s->name; s++) {
>  		igt_subtest_f("one-queue-%s", s->name)
>  			xe_for_each_multi_queue_engine(fd, hwe)
LGTM,
Reviewed-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> --
> 2.43.0

Re: [PATCH v2 07/19] tests/intel/xe_exec_multi_queue: Add multiple placement test

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Validate using virtual exec queues with multiple placements.
> 
> v2: Run test even with single engine instance
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> ---
>  tests/intel/xe_exec_multi_queue.c | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index df60835d6..fdaaf78c4 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -383,6 +383,29 @@ test_exec(int fd, struct
> drm_xe_engine_class_instance *eci, int num_placement,
>         test_legacy_mode(fd, eci, num_placement, n_exec_queues,
> n_execs, flags);
>  }
>  
> +/**
> + * SUBTEST: virtual
> + * Description: Validate virtual queues with multiple placements
> + * Test category: functionality test
> + */
> +static void
> +test_exec_virtual(int fd, int gt, int class)
> +{
> +       struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> +       struct drm_xe_engine_class_instance *hwe;
> +       int n = 0;
> +
> +       xe_for_each_engine(fd, hwe) {
> +               if (hwe->engine_class != class || hwe->gt_id != gt)
> +                       continue;
> +
> +               eci[n++] = *hwe;
> +       }
> +       igt_assert(n);
> +
> +       test_exec(fd, eci, n, n, n, 0);
> +}
> +
>  igt_main
>  {
>         struct drm_xe_engine_class_instance *hwe;
> @@ -408,6 +431,11 @@ igt_main
>                         xe_for_each_multi_queue_engine_class(class)
>                                 test_sanity(fd, gt, class);
>  
> +       igt_subtest_f("virtual")
> +               xe_for_each_gt(fd, gt)
> +                       xe_for_each_multi_queue_engine_class(class)
> +                               test_exec_virtual(fd, gt, class);
> +
>         for (const struct section *s = sections; s->name; s++) {
>                 igt_subtest_f("one-queue-%s", s->name)
>                         xe_for_each_multi_queue_engine(fd, hwe)

[PATCH v2 08/19] tests/intel/xe_exec_multi_queue: Add preempt mode test

[Niranjana Vishwanathapura]

Validate multi queue group functionality in preempt mode.

v2: Remove simulation related code (Priyanka)
    Use BASE_ADDRESS macro for address (Sai)

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 153 +++++++++++++++++++++++++++++-
 1 file changed, 148 insertions(+), 5 deletions(-)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index fdaaf78c4..1e33c5db8 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -28,6 +28,7 @@
 #define USERPTR			(0x1 << 0)
 #define PRIORITY		(0x1 << 1)
 #define CLOSE_FD		(0x1 << 2)
+#define PREEMPT_MODE		(0x1 << 3)
 
 #define MAX_INSTANCE 9
 
@@ -36,7 +37,7 @@
 #define BASE_ADDRESS	0x1a0000
 
 static void
-__test_sanity(int fd, int gt, int class)
+__test_sanity(int fd, int gt, int class, bool preempt_mode)
 {
 	uint32_t exec_queues[MAX_N_EXEC_QUEUES];
 	struct drm_xe_ext_set_property multi_queue = {
@@ -69,7 +70,7 @@ __test_sanity(int fd, int gt, int class)
 	if (!n)
 		return;
 
-	vm = xe_vm_create(fd, 0, 0);
+	vm = xe_vm_create(fd, preempt_mode ? DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
 
 	/* Invalid flags */
 	while (!invalid_flag)
@@ -118,7 +119,7 @@ __test_sanity(int fd, int gt, int class)
 
 	/* Queues in a queue group must share the same address space (vm) */
 	multi_queue.value = exec_queues[0];
-	vm2 = xe_vm_create(fd, 0, 0);
+	vm2 = xe_vm_create(fd, preempt_mode ? DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
 	igt_assert_eq(__xe_exec_queue_create(fd, vm2, 1, 1, eci, ext, &val), -EINVAL);
 	xe_vm_destroy(fd, vm2);
 
@@ -203,7 +204,137 @@ __test_sanity(int fd, int gt, int class)
 static void
 test_sanity(int fd, int gt, int class)
 {
-	__test_sanity(fd, gt, class);
+	__test_sanity(fd, gt, class, false);
+	__test_sanity(fd, gt, class, true);
+}
+
+static void
+test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
+		  int n_exec_queues, int n_execs, unsigned int flags)
+{
+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
+	struct drm_xe_sync sync = {
+		.type = DRM_XE_SYNC_TYPE_USER_FENCE,
+		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		.timeline_value = USER_FENCE_VALUE,
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&sync),
+	};
+	uint32_t vm;
+	uint64_t addr = BASE_ADDRESS;
+	uint32_t exec_queues[MAX_N_EXEC_QUEUES];
+	int64_t fence_timeout = NSEC_PER_SEC;
+	uint64_t vm_sync = 0;
+	size_t bo_size;
+	uint32_t bo = 0;
+	struct {
+		uint32_t batch[16];
+		uint64_t pad;
+		uint64_t exec_sync;
+		uint32_t data;
+	} *data;
+	int i, b;
+
+	if (flags & CLOSE_FD)
+		fd = drm_open_driver(DRIVER_XE);
+
+	igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
+	bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
+
+	if (flags & USERPTR) {
+		data = aligned_alloc(xe_get_default_alignment(fd), bo_size);
+		igt_assert(data);
+
+		memset(data, 0, bo_size);
+	} else {
+		bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
+				  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+		data = xe_bo_map(fd, bo, bo_size);
+	}
+
+	for (i = 0; i < n_exec_queues; i++) {
+		struct drm_xe_ext_set_property multi_queue = {
+			.base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+			.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
+		};
+		struct drm_xe_ext_set_property mq_priority = {
+			.base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+			.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
+		};
+		uint64_t ext = to_user_pointer(&multi_queue);
+
+		if (flags & PRIORITY) {
+			multi_queue.base.next_extension = to_user_pointer(&mq_priority);
+			mq_priority.value = XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2);
+		}
+
+		multi_queue.value = i ? exec_queues[0] : DRM_XE_MULTI_GROUP_CREATE;
+		igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, num_placement, eci,
+						     ext, &exec_queues[i]), 0);
+	};
+
+	sync.addr = to_user_pointer(&vm_sync);
+	if (bo)
+		xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, &sync, 1);
+	else
+		xe_vm_bind_userptr_async(fd, vm, 0, to_user_pointer(data),
+					 addr, bo_size, &sync, 1);
+
+	xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, fence_timeout);
+	vm_sync = 0;
+
+	for (i = 0; i < n_execs; i++) {
+		uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
+		uint64_t batch_addr = addr + batch_offset;
+		uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
+		uint64_t sdi_addr = addr + sdi_offset;
+		int e = i % n_exec_queues;
+
+		b = 0;
+		data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+		data[i].batch[b++] = sdi_addr;
+		data[i].batch[b++] = sdi_addr >> 32;
+		data[i].batch[b++] = 0xc0ffee;
+		data[i].batch[b++] = MI_BATCH_BUFFER_END;
+		igt_assert(b <= ARRAY_SIZE(data[i].batch));
+
+		sync.addr = addr + (char *)&data[i].exec_sync - (char *)data;
+
+		exec.exec_queue_id = exec_queues[e];
+		exec.address = batch_addr;
+		xe_exec(fd, &exec);
+	}
+
+	for (i = 0; i < n_execs; i++)
+		xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE,
+			       exec_queues[i % n_exec_queues], fence_timeout);
+
+	sync.addr = to_user_pointer(&vm_sync);
+	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
+	xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, fence_timeout);
+
+	for (i = 0; i < n_execs; i++)
+		igt_assert_eq(data[i].data, 0xc0ffee);
+
+	if (!(flags & CLOSE_FD))
+		for (i = 0; i < n_exec_queues; i++)
+			xe_exec_queue_destroy(fd, exec_queues[i]);
+
+	if (bo) {
+		munmap(data, bo_size);
+		gem_close(fd, bo);
+	} else {
+		free(data);
+	}
+
+	if (!(flags & CLOSE_FD))
+		xe_vm_destroy(fd, vm);
+	else
+		drm_close_driver(fd);
 }
 
 static void
@@ -375,12 +506,19 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
  * @userptr:					userptr
  * @priority:					priority
  * @close-fd:					close fd without destroying exec queues
+ * @preempt-mode-basic:				preempt-mode basic
+ * @preempt-mode-userptr:			preempt-mode userptr
+ * @preempt-mode-priority:			preempt-mode priority
+ * @preempt-mode-close-fd:			preempt-mode close fd without destroying exec queues
  */
 static void
 test_exec(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
 	  int n_exec_queues, int n_execs, unsigned int flags)
 {
-	test_legacy_mode(fd, eci, num_placement, n_exec_queues, n_execs, flags);
+	if (flags & PREEMPT_MODE)
+		test_preempt_mode(fd, eci, num_placement, n_exec_queues, n_execs, flags);
+	else
+		test_legacy_mode(fd, eci, num_placement, n_exec_queues, n_execs, flags);
 }
 
 /**
@@ -404,6 +542,7 @@ test_exec_virtual(int fd, int gt, int class)
 	igt_assert(n);
 
 	test_exec(fd, eci, n, n, n, 0);
+	test_exec(fd, eci, n, n, n, PREEMPT_MODE);
 }
 
 igt_main
@@ -417,6 +556,10 @@ igt_main
 		{ "userptr", USERPTR },
 		{ "priority", PRIORITY },
 		{ "close-fd", CLOSE_FD },
+		{ "preempt-mode-basic", PREEMPT_MODE },
+		{ "preempt-mode-userptr", PREEMPT_MODE | USERPTR },
+		{ "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
+		{ "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
 		{ NULL },
 	};
 	int fd, gt, class;
-- 
2.43.0

Re: [PATCH v2 08/19] tests/intel/xe_exec_multi_queue: Add preempt mode test

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Validate multi queue group functionality in preempt mode.
> 
> v2: Remove simulation related code (Priyanka)
>     Use BASE_ADDRESS macro for address (Sai)
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> ---
>  tests/intel/xe_exec_multi_queue.c | 153
> +++++++++++++++++++++++++++++-
>  1 file changed, 148 insertions(+), 5 deletions(-)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index fdaaf78c4..1e33c5db8 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -28,6 +28,7 @@
>  #define USERPTR                        (0x1 << 0)
>  #define PRIORITY               (0x1 << 1)
>  #define CLOSE_FD               (0x1 << 2)
> +#define PREEMPT_MODE           (0x1 << 3)
>  
>  #define MAX_INSTANCE 9
>  
> @@ -36,7 +37,7 @@
>  #define BASE_ADDRESS   0x1a0000
>  
>  static void
> -__test_sanity(int fd, int gt, int class)
> +__test_sanity(int fd, int gt, int class, bool preempt_mode)
>  {
>         uint32_t exec_queues[MAX_N_EXEC_QUEUES];
>         struct drm_xe_ext_set_property multi_queue = {
> @@ -69,7 +70,7 @@ __test_sanity(int fd, int gt, int class)
>         if (!n)
>                 return;
>  
> -       vm = xe_vm_create(fd, 0, 0);
> +       vm = xe_vm_create(fd, preempt_mode ?
> DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
>  
>         /* Invalid flags */
>         while (!invalid_flag)
> @@ -118,7 +119,7 @@ __test_sanity(int fd, int gt, int class)
>  
>         /* Queues in a queue group must share the same address space
> (vm) */
>         multi_queue.value = exec_queues[0];
> -       vm2 = xe_vm_create(fd, 0, 0);
> +       vm2 = xe_vm_create(fd, preempt_mode ?
> DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
>         igt_assert_eq(__xe_exec_queue_create(fd, vm2, 1, 1, eci, ext,
> &val), -EINVAL);
>         xe_vm_destroy(fd, vm2);
>  
> @@ -203,7 +204,137 @@ __test_sanity(int fd, int gt, int class)
>  static void
>  test_sanity(int fd, int gt, int class)
>  {
> -       __test_sanity(fd, gt, class);
> +       __test_sanity(fd, gt, class, false);
> +       __test_sanity(fd, gt, class, true);

I guess it doesn't hurt, but there also shouldn't be anything multi
queue specific tested between the two modes right? It just seems like
we're running extra test content here without a benefit - for the
sanity tests specifically.

> +}
> +
> +static void
> +test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci,
> int num_placement,
> +                 int n_exec_queues, int n_execs, unsigned int flags)
> +{

Is there a reason we can't just combine this with a PREEMPT_MODE flag
in the "legacy_mode" routine? Most of this is duplicated, and we do the
same in the sanity tests (assuming we keep them) above.

Thanks,
Stuart

> +#define USER_FENCE_VALUE       0xdeadbeefdeadbeefull
> +       struct drm_xe_sync sync = {
> +               .type = DRM_XE_SYNC_TYPE_USER_FENCE,
> +               .flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +               .timeline_value = USER_FENCE_VALUE,
> +       };
> +       struct drm_xe_exec exec = {
> +               .num_batch_buffer = 1,
> +               .num_syncs = 1,
> +               .syncs = to_user_pointer(&sync),
> +       };
> +       uint32_t vm;
> +       uint64_t addr = BASE_ADDRESS;
> +       uint32_t exec_queues[MAX_N_EXEC_QUEUES];
> +       int64_t fence_timeout = NSEC_PER_SEC;
> +       uint64_t vm_sync = 0;
> +       size_t bo_size;
> +       uint32_t bo = 0;
> +       struct {
> +               uint32_t batch[16];
> +               uint64_t pad;
> +               uint64_t exec_sync;
> +               uint32_t data;
> +       } *data;
> +       int i, b;
> +
> +       if (flags & CLOSE_FD)
> +               fd = drm_open_driver(DRIVER_XE);
> +
> +       igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
> +       vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> +       bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
> +
> +       if (flags & USERPTR) {
> +               data = aligned_alloc(xe_get_default_alignment(fd),
> bo_size);
> +               igt_assert(data);
> +
> +               memset(data, 0, bo_size);
> +       } else {
> +               bo = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> +                                
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +               data = xe_bo_map(fd, bo, bo_size);
> +       }
> +
> +       for (i = 0; i < n_exec_queues; i++) {
> +               struct drm_xe_ext_set_property multi_queue = {
> +                       .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +                       .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
> +               };
> +               struct drm_xe_ext_set_property mq_priority = {
> +                       .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +                       .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> +               };
> +               uint64_t ext = to_user_pointer(&multi_queue);
> +
> +               if (flags & PRIORITY) {
> +                       multi_queue.base.next_extension =
> to_user_pointer(&mq_priority);
> +                       mq_priority.value =
> XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2);
> +               }
> +
> +               multi_queue.value = i ? exec_queues[0] :
> DRM_XE_MULTI_GROUP_CREATE;
> +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 1,
> num_placement, eci,
> +                                                    ext,
> &exec_queues[i]), 0);
> +       };
> +
> +       sync.addr = to_user_pointer(&vm_sync);
> +       if (bo)
> +               xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size,
> &sync, 1);
> +       else
> +               xe_vm_bind_userptr_async(fd, vm, 0,
> to_user_pointer(data),
> +                                        addr, bo_size, &sync, 1);
> +
> +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
> fence_timeout);
> +       vm_sync = 0;
> +
> +       for (i = 0; i < n_execs; i++) {
> +               uint64_t batch_offset = (char *)&data[i].batch -
> (char *)data;
> +               uint64_t batch_addr = addr + batch_offset;
> +               uint64_t sdi_offset = (char *)&data[i].data - (char
> *)data;
> +               uint64_t sdi_addr = addr + sdi_offset;
> +               int e = i % n_exec_queues;
> +
> +               b = 0;
> +               data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> +               data[i].batch[b++] = sdi_addr;
> +               data[i].batch[b++] = sdi_addr >> 32;
> +               data[i].batch[b++] = 0xc0ffee;
> +               data[i].batch[b++] = MI_BATCH_BUFFER_END;
> +               igt_assert(b <= ARRAY_SIZE(data[i].batch));
> +
> +               sync.addr = addr + (char *)&data[i].exec_sync - (char
> *)data;
> +
> +               exec.exec_queue_id = exec_queues[e];
> +               exec.address = batch_addr;
> +               xe_exec(fd, &exec);
> +       }
> +
> +       for (i = 0; i < n_execs; i++)
> +               xe_wait_ufence(fd, &data[i].exec_sync,
> USER_FENCE_VALUE,
> +                              exec_queues[i % n_exec_queues],
> fence_timeout);
> +
> +       sync.addr = to_user_pointer(&vm_sync);
> +       xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
> +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
> fence_timeout);
> +
> +       for (i = 0; i < n_execs; i++)
> +               igt_assert_eq(data[i].data, 0xc0ffee);
> +
> +       if (!(flags & CLOSE_FD))
> +               for (i = 0; i < n_exec_queues; i++)
> +                       xe_exec_queue_destroy(fd, exec_queues[i]);
> +
> +       if (bo) {
> +               munmap(data, bo_size);
> +               gem_close(fd, bo);
> +       } else {
> +               free(data);
> +       }
> +
> +       if (!(flags & CLOSE_FD))
> +               xe_vm_destroy(fd, vm);
> +       else
> +               drm_close_driver(fd);
>  }
>  
>  static void
> @@ -375,12 +506,19 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>   * @userptr:                                   userptr
>   * @priority:                                  priority
>   * @close-fd:                                  close fd without
> destroying exec queues
> + * @preempt-mode-basic:                                preempt-mode
> basic
> + * @preempt-mode-userptr:                      preempt-mode userptr
> + * @preempt-mode-priority:                     preempt-mode priority
> + * @preempt-mode-close-fd:                     preempt-mode close fd
> without destroying exec queues
>   */
>  static void
>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement,
>           int n_exec_queues, int n_execs, unsigned int flags)
>  {
> -       test_legacy_mode(fd, eci, num_placement, n_exec_queues,
> n_execs, flags);
> +       if (flags & PREEMPT_MODE)
> +               test_preempt_mode(fd, eci, num_placement,
> n_exec_queues, n_execs, flags);
> +       else
> +               test_legacy_mode(fd, eci, num_placement,
> n_exec_queues, n_execs, flags);
>  }
>  
>  /**
> @@ -404,6 +542,7 @@ test_exec_virtual(int fd, int gt, int class)
>         igt_assert(n);
>  
>         test_exec(fd, eci, n, n, n, 0);
> +       test_exec(fd, eci, n, n, n, PREEMPT_MODE);
>  }
>  
>  igt_main
> @@ -417,6 +556,10 @@ igt_main
>                 { "userptr", USERPTR },
>                 { "priority", PRIORITY },
>                 { "close-fd", CLOSE_FD },
> +               { "preempt-mode-basic", PREEMPT_MODE },
> +               { "preempt-mode-userptr", PREEMPT_MODE | USERPTR },
> +               { "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
> +               { "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
>                 { NULL },
>         };
>         int fd, gt, class;

Re: [PATCH v2 08/19] tests/intel/xe_exec_multi_queue: Add preempt mode test

[Niranjana Vishwanathapura]

On Thu, Dec 04, 2025 at 12:52:54PM -0800, Summers, Stuart wrote:
>On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
>> Validate multi queue group functionality in preempt mode.
>>
>> v2: Remove simulation related code (Priyanka)
>>     Use BASE_ADDRESS macro for address (Sai)
>>
>> Signed-off-by: Niranjana Vishwanathapura
>> <niranjana.vishwanathapura@intel.com>
>> ---
>>  tests/intel/xe_exec_multi_queue.c | 153
>> +++++++++++++++++++++++++++++-
>>  1 file changed, 148 insertions(+), 5 deletions(-)
>>
>> diff --git a/tests/intel/xe_exec_multi_queue.c
>> b/tests/intel/xe_exec_multi_queue.c
>> index fdaaf78c4..1e33c5db8 100644
>> --- a/tests/intel/xe_exec_multi_queue.c
>> +++ b/tests/intel/xe_exec_multi_queue.c
>> @@ -28,6 +28,7 @@
>>  #define USERPTR                        (0x1 << 0)
>>  #define PRIORITY               (0x1 << 1)
>>  #define CLOSE_FD               (0x1 << 2)
>> +#define PREEMPT_MODE           (0x1 << 3)
>>  
>>  #define MAX_INSTANCE 9
>>  
>> @@ -36,7 +37,7 @@
>>  #define BASE_ADDRESS   0x1a0000
>>  
>>  static void
>> -__test_sanity(int fd, int gt, int class)
>> +__test_sanity(int fd, int gt, int class, bool preempt_mode)
>>  {
>>         uint32_t exec_queues[MAX_N_EXEC_QUEUES];
>>         struct drm_xe_ext_set_property multi_queue = {
>> @@ -69,7 +70,7 @@ __test_sanity(int fd, int gt, int class)
>>         if (!n)
>>                 return;
>>  
>> -       vm = xe_vm_create(fd, 0, 0);
>> +       vm = xe_vm_create(fd, preempt_mode ?
>> DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
>>  
>>         /* Invalid flags */
>>         while (!invalid_flag)
>> @@ -118,7 +119,7 @@ __test_sanity(int fd, int gt, int class)
>>  
>>         /* Queues in a queue group must share the same address space
>> (vm) */
>>         multi_queue.value = exec_queues[0];
>> -       vm2 = xe_vm_create(fd, 0, 0);
>> +       vm2 = xe_vm_create(fd, preempt_mode ?
>> DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
>>         igt_assert_eq(__xe_exec_queue_create(fd, vm2, 1, 1, eci, ext,
>> &val), -EINVAL);
>>         xe_vm_destroy(fd, vm2);
>>  
>> @@ -203,7 +204,137 @@ __test_sanity(int fd, int gt, int class)
>>  static void
>>  test_sanity(int fd, int gt, int class)
>>  {
>> -       __test_sanity(fd, gt, class);
>> +       __test_sanity(fd, gt, class, false);
>> +       __test_sanity(fd, gt, class, true);
>
>I guess it doesn't hurt, but there also shouldn't be anything multi
>queue specific tested between the two modes right? It just seems like
>we're running extra test content here without a benefit - for the
>sanity tests specifically.
>

There is. In preempt mode test, we are testing that KEEP_ACTIVE will
only be supported in FAULT mode (added in a later patch). Besides,
we should sanity test preempt mode also here to ensure KMD doesn't
reject mult-queue creation etc based on mode and other settings.

>> +}
>> +
>> +static void
>> +test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci,
>> int num_placement,
>> +                 int n_exec_queues, int n_execs, unsigned int flags)
>> +{
>
>Is there a reason we can't just combine this with a PREEMPT_MODE flag
>in the "legacy_mode" routine? Most of this is duplicated, and we do the
>same in the sanity tests (assuming we keep them) above.
>

We do that in exec-sanity test which is much simpler. But here we have
multiple sync objects etc and it was resulting in too many if/else
blocks among other changes. So, it made sense to keep them separate.
Other tests like xe_exec_balancer also keeps legacy and preempt mode
tests separate. May be we can revisit later to check all tradeoffs?

Niranjana

>Thanks,
>Stuart
>
>> +#define USER_FENCE_VALUE       0xdeadbeefdeadbeefull
>> +       struct drm_xe_sync sync = {
>> +               .type = DRM_XE_SYNC_TYPE_USER_FENCE,
>> +               .flags = DRM_XE_SYNC_FLAG_SIGNAL,
>> +               .timeline_value = USER_FENCE_VALUE,
>> +       };
>> +       struct drm_xe_exec exec = {
>> +               .num_batch_buffer = 1,
>> +               .num_syncs = 1,
>> +               .syncs = to_user_pointer(&sync),
>> +       };
>> +       uint32_t vm;
>> +       uint64_t addr = BASE_ADDRESS;
>> +       uint32_t exec_queues[MAX_N_EXEC_QUEUES];
>> +       int64_t fence_timeout = NSEC_PER_SEC;
>> +       uint64_t vm_sync = 0;
>> +       size_t bo_size;
>> +       uint32_t bo = 0;
>> +       struct {
>> +               uint32_t batch[16];
>> +               uint64_t pad;
>> +               uint64_t exec_sync;
>> +               uint32_t data;
>> +       } *data;
>> +       int i, b;
>> +
>> +       if (flags & CLOSE_FD)
>> +               fd = drm_open_driver(DRIVER_XE);
>> +
>> +       igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
>> +       vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
>> +       bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
>> +
>> +       if (flags & USERPTR) {
>> +               data = aligned_alloc(xe_get_default_alignment(fd),
>> bo_size);
>> +               igt_assert(data);
>> +
>> +               memset(data, 0, bo_size);
>> +       } else {
>> +               bo = xe_bo_create(fd, vm, bo_size,
>> vram_if_possible(fd, eci[0].gt_id),
>> +                                
>> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>> +               data = xe_bo_map(fd, bo, bo_size);
>> +       }
>> +
>> +       for (i = 0; i < n_exec_queues; i++) {
>> +               struct drm_xe_ext_set_property multi_queue = {
>> +                       .base.name =
>> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
>> +                       .property =
>> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
>> +               };
>> +               struct drm_xe_ext_set_property mq_priority = {
>> +                       .base.name =
>> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
>> +                       .property =
>> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
>> +               };
>> +               uint64_t ext = to_user_pointer(&multi_queue);
>> +
>> +               if (flags & PRIORITY) {
>> +                       multi_queue.base.next_extension =
>> to_user_pointer(&mq_priority);
>> +                       mq_priority.value =
>> XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2);
>> +               }
>> +
>> +               multi_queue.value = i ? exec_queues[0] :
>> DRM_XE_MULTI_GROUP_CREATE;
>> +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 1,
>> num_placement, eci,
>> +                                                    ext,
>> &exec_queues[i]), 0);
>> +       };
>> +
>> +       sync.addr = to_user_pointer(&vm_sync);
>> +       if (bo)
>> +               xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size,
>> &sync, 1);
>> +       else
>> +               xe_vm_bind_userptr_async(fd, vm, 0,
>> to_user_pointer(data),
>> +                                        addr, bo_size, &sync, 1);
>> +
>> +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
>> fence_timeout);
>> +       vm_sync = 0;
>> +
>> +       for (i = 0; i < n_execs; i++) {
>> +               uint64_t batch_offset = (char *)&data[i].batch -
>> (char *)data;
>> +               uint64_t batch_addr = addr + batch_offset;
>> +               uint64_t sdi_offset = (char *)&data[i].data - (char
>> *)data;
>> +               uint64_t sdi_addr = addr + sdi_offset;
>> +               int e = i % n_exec_queues;
>> +
>> +               b = 0;
>> +               data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
>> +               data[i].batch[b++] = sdi_addr;
>> +               data[i].batch[b++] = sdi_addr >> 32;
>> +               data[i].batch[b++] = 0xc0ffee;
>> +               data[i].batch[b++] = MI_BATCH_BUFFER_END;
>> +               igt_assert(b <= ARRAY_SIZE(data[i].batch));
>> +
>> +               sync.addr = addr + (char *)&data[i].exec_sync - (char
>> *)data;
>> +
>> +               exec.exec_queue_id = exec_queues[e];
>> +               exec.address = batch_addr;
>> +               xe_exec(fd, &exec);
>> +       }
>> +
>> +       for (i = 0; i < n_execs; i++)
>> +               xe_wait_ufence(fd, &data[i].exec_sync,
>> USER_FENCE_VALUE,
>> +                              exec_queues[i % n_exec_queues],
>> fence_timeout);
>> +
>> +       sync.addr = to_user_pointer(&vm_sync);
>> +       xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
>> +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
>> fence_timeout);
>> +
>> +       for (i = 0; i < n_execs; i++)
>> +               igt_assert_eq(data[i].data, 0xc0ffee);
>> +
>> +       if (!(flags & CLOSE_FD))
>> +               for (i = 0; i < n_exec_queues; i++)
>> +                       xe_exec_queue_destroy(fd, exec_queues[i]);
>> +
>> +       if (bo) {
>> +               munmap(data, bo_size);
>> +               gem_close(fd, bo);
>> +       } else {
>> +               free(data);
>> +       }
>> +
>> +       if (!(flags & CLOSE_FD))
>> +               xe_vm_destroy(fd, vm);
>> +       else
>> +               drm_close_driver(fd);
>>  }
>>  
>>  static void
>> @@ -375,12 +506,19 @@ test_legacy_mode(int fd, struct
>> drm_xe_engine_class_instance *eci, int num_place
>>   * @userptr:                                   userptr
>>   * @priority:                                  priority
>>   * @close-fd:                                  close fd without
>> destroying exec queues
>> + * @preempt-mode-basic:                                preempt-mode
>> basic
>> + * @preempt-mode-userptr:                      preempt-mode userptr
>> + * @preempt-mode-priority:                     preempt-mode priority
>> + * @preempt-mode-close-fd:                     preempt-mode close fd
>> without destroying exec queues
>>   */
>>  static void
>>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
>> num_placement,
>>           int n_exec_queues, int n_execs, unsigned int flags)
>>  {
>> -       test_legacy_mode(fd, eci, num_placement, n_exec_queues,
>> n_execs, flags);
>> +       if (flags & PREEMPT_MODE)
>> +               test_preempt_mode(fd, eci, num_placement,
>> n_exec_queues, n_execs, flags);
>> +       else
>> +               test_legacy_mode(fd, eci, num_placement,
>> n_exec_queues, n_execs, flags);
>>  }
>>  
>>  /**
>> @@ -404,6 +542,7 @@ test_exec_virtual(int fd, int gt, int class)
>>         igt_assert(n);
>>  
>>         test_exec(fd, eci, n, n, n, 0);
>> +       test_exec(fd, eci, n, n, n, PREEMPT_MODE);
>>  }
>>  
>>  igt_main
>> @@ -417,6 +556,10 @@ igt_main
>>                 { "userptr", USERPTR },
>>                 { "priority", PRIORITY },
>>                 { "close-fd", CLOSE_FD },
>> +               { "preempt-mode-basic", PREEMPT_MODE },
>> +               { "preempt-mode-userptr", PREEMPT_MODE | USERPTR },
>> +               { "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
>> +               { "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
>>                 { NULL },
>>         };
>>         int fd, gt, class;
>

Re: [PATCH v2 08/19] tests/intel/xe_exec_multi_queue: Add preempt mode test

[Summers, Stuart]

On Fri, 2025-12-05 at 11:12 -0800, Niranjana Vishwanathapura wrote:
> On Thu, Dec 04, 2025 at 12:52:54PM -0800, Summers, Stuart wrote:
> > On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> > > Validate multi queue group functionality in preempt mode.
> > > 
> > > v2: Remove simulation related code (Priyanka)
> > >     Use BASE_ADDRESS macro for address (Sai)
> > > 
> > > Signed-off-by: Niranjana Vishwanathapura
> > > <niranjana.vishwanathapura@intel.com>
> > > ---
> > >  tests/intel/xe_exec_multi_queue.c | 153
> > > +++++++++++++++++++++++++++++-
> > >  1 file changed, 148 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/tests/intel/xe_exec_multi_queue.c
> > > b/tests/intel/xe_exec_multi_queue.c
> > > index fdaaf78c4..1e33c5db8 100644
> > > --- a/tests/intel/xe_exec_multi_queue.c
> > > +++ b/tests/intel/xe_exec_multi_queue.c
> > > @@ -28,6 +28,7 @@
> > >  #define USERPTR                        (0x1 << 0)
> > >  #define PRIORITY               (0x1 << 1)
> > >  #define CLOSE_FD               (0x1 << 2)
> > > +#define PREEMPT_MODE           (0x1 << 3)
> > >  
> > >  #define MAX_INSTANCE 9
> > >  
> > > @@ -36,7 +37,7 @@
> > >  #define BASE_ADDRESS   0x1a0000
> > >  
> > >  static void
> > > -__test_sanity(int fd, int gt, int class)
> > > +__test_sanity(int fd, int gt, int class, bool preempt_mode)
> > >  {
> > >         uint32_t exec_queues[MAX_N_EXEC_QUEUES];
> > >         struct drm_xe_ext_set_property multi_queue = {
> > > @@ -69,7 +70,7 @@ __test_sanity(int fd, int gt, int class)
> > >         if (!n)
> > >                 return;
> > >  
> > > -       vm = xe_vm_create(fd, 0, 0);
> > > +       vm = xe_vm_create(fd, preempt_mode ?
> > > DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
> > >  
> > >         /* Invalid flags */
> > >         while (!invalid_flag)
> > > @@ -118,7 +119,7 @@ __test_sanity(int fd, int gt, int class)
> > >  
> > >         /* Queues in a queue group must share the same address
> > > space
> > > (vm) */
> > >         multi_queue.value = exec_queues[0];
> > > -       vm2 = xe_vm_create(fd, 0, 0);
> > > +       vm2 = xe_vm_create(fd, preempt_mode ?
> > > DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
> > >         igt_assert_eq(__xe_exec_queue_create(fd, vm2, 1, 1, eci,
> > > ext,
> > > &val), -EINVAL);
> > >         xe_vm_destroy(fd, vm2);
> > >  
> > > @@ -203,7 +204,137 @@ __test_sanity(int fd, int gt, int class)
> > >  static void
> > >  test_sanity(int fd, int gt, int class)
> > >  {
> > > -       __test_sanity(fd, gt, class);
> > > +       __test_sanity(fd, gt, class, false);
> > > +       __test_sanity(fd, gt, class, true);
> > 
> > I guess it doesn't hurt, but there also shouldn't be anything multi
> > queue specific tested between the two modes right? It just seems
> > like
> > we're running extra test content here without a benefit - for the
> > sanity tests specifically.
> > 
> 
> There is. In preempt mode test, we are testing that KEEP_ACTIVE will
> only be supported in FAULT mode (added in a later patch). Besides,
> we should sanity test preempt mode also here to ensure KMD doesn't
> reject mult-queue creation etc based on mode and other settings.

Ah right. Ok no problem here.

> 
> > > +}
> > > +
> > > +static void
> > > +test_preempt_mode(int fd, struct drm_xe_engine_class_instance
> > > *eci,
> > > int num_placement,
> > > +                 int n_exec_queues, int n_execs, unsigned int
> > > flags)
> > > +{
> > 
> > Is there a reason we can't just combine this with a PREEMPT_MODE
> > flag
> > in the "legacy_mode" routine? Most of this is duplicated, and we do
> > the
> > same in the sanity tests (assuming we keep them) above.
> > 
> 
> We do that in exec-sanity test which is much simpler. But here we
> have
> multiple sync objects etc and it was resulting in too many if/else
> blocks among other changes. So, it made sense to keep them separate.
> Other tests like xe_exec_balancer also keeps legacy and preempt mode
> tests separate. May be we can revisit later to check all tradeoffs?

Yeah sounds good to me. If we do something like that, probably better
as a general refactor and not multi-queue specific I agree.

Thanks,
Stuart

> 
> Niranjana
> 
> > Thanks,
> > Stuart
> > 
> > > +#define USER_FENCE_VALUE       0xdeadbeefdeadbeefull
> > > +       struct drm_xe_sync sync = {
> > > +               .type = DRM_XE_SYNC_TYPE_USER_FENCE,
> > > +               .flags = DRM_XE_SYNC_FLAG_SIGNAL,
> > > +               .timeline_value = USER_FENCE_VALUE,
> > > +       };
> > > +       struct drm_xe_exec exec = {
> > > +               .num_batch_buffer = 1,
> > > +               .num_syncs = 1,
> > > +               .syncs = to_user_pointer(&sync),
> > > +       };
> > > +       uint32_t vm;
> > > +       uint64_t addr = BASE_ADDRESS;
> > > +       uint32_t exec_queues[MAX_N_EXEC_QUEUES];
> > > +       int64_t fence_timeout = NSEC_PER_SEC;
> > > +       uint64_t vm_sync = 0;
> > > +       size_t bo_size;
> > > +       uint32_t bo = 0;
> > > +       struct {
> > > +               uint32_t batch[16];
> > > +               uint64_t pad;
> > > +               uint64_t exec_sync;
> > > +               uint32_t data;
> > > +       } *data;
> > > +       int i, b;
> > > +
> > > +       if (flags & CLOSE_FD)
> > > +               fd = drm_open_driver(DRIVER_XE);
> > > +
> > > +       igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
> > > +       vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> > > +       bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
> > > +
> > > +       if (flags & USERPTR) {
> > > +               data =
> > > aligned_alloc(xe_get_default_alignment(fd),
> > > bo_size);
> > > +               igt_assert(data);
> > > +
> > > +               memset(data, 0, bo_size);
> > > +       } else {
> > > +               bo = xe_bo_create(fd, vm, bo_size,
> > > vram_if_possible(fd, eci[0].gt_id),
> > > +                                
> > > DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> > > +               data = xe_bo_map(fd, bo, bo_size);
> > > +       }
> > > +
> > > +       for (i = 0; i < n_exec_queues; i++) {
> > > +               struct drm_xe_ext_set_property multi_queue = {
> > > +                       .base.name =
> > > DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> > > +                       .property =
> > > DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
> > > +               };
> > > +               struct drm_xe_ext_set_property mq_priority = {
> > > +                       .base.name =
> > > DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> > > +                       .property =
> > > DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> > > +               };
> > > +               uint64_t ext = to_user_pointer(&multi_queue);
> > > +
> > > +               if (flags & PRIORITY) {
> > > +                       multi_queue.base.next_extension =
> > > to_user_pointer(&mq_priority);
> > > +                       mq_priority.value =
> > > XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2);
> > > +               }
> > > +
> > > +               multi_queue.value = i ? exec_queues[0] :
> > > DRM_XE_MULTI_GROUP_CREATE;
> > > +               igt_assert_eq(__xe_exec_queue_create(fd, vm, 1,
> > > num_placement, eci,
> > > +                                                    ext,
> > > &exec_queues[i]), 0);
> > > +       };
> > > +
> > > +       sync.addr = to_user_pointer(&vm_sync);
> > > +       if (bo)
> > > +               xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size,
> > > &sync, 1);
> > > +       else
> > > +               xe_vm_bind_userptr_async(fd, vm, 0,
> > > to_user_pointer(data),
> > > +                                        addr, bo_size, &sync,
> > > 1);
> > > +
> > > +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
> > > fence_timeout);
> > > +       vm_sync = 0;
> > > +
> > > +       for (i = 0; i < n_execs; i++) {
> > > +               uint64_t batch_offset = (char *)&data[i].batch -
> > > (char *)data;
> > > +               uint64_t batch_addr = addr + batch_offset;
> > > +               uint64_t sdi_offset = (char *)&data[i].data -
> > > (char
> > > *)data;
> > > +               uint64_t sdi_addr = addr + sdi_offset;
> > > +               int e = i % n_exec_queues;
> > > +
> > > +               b = 0;
> > > +               data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> > > +               data[i].batch[b++] = sdi_addr;
> > > +               data[i].batch[b++] = sdi_addr >> 32;
> > > +               data[i].batch[b++] = 0xc0ffee;
> > > +               data[i].batch[b++] = MI_BATCH_BUFFER_END;
> > > +               igt_assert(b <= ARRAY_SIZE(data[i].batch));
> > > +
> > > +               sync.addr = addr + (char *)&data[i].exec_sync -
> > > (char
> > > *)data;
> > > +
> > > +               exec.exec_queue_id = exec_queues[e];
> > > +               exec.address = batch_addr;
> > > +               xe_exec(fd, &exec);
> > > +       }
> > > +
> > > +       for (i = 0; i < n_execs; i++)
> > > +               xe_wait_ufence(fd, &data[i].exec_sync,
> > > USER_FENCE_VALUE,
> > > +                              exec_queues[i % n_exec_queues],
> > > fence_timeout);
> > > +
> > > +       sync.addr = to_user_pointer(&vm_sync);
> > > +       xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync,
> > > 1);
> > > +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
> > > fence_timeout);
> > > +
> > > +       for (i = 0; i < n_execs; i++)
> > > +               igt_assert_eq(data[i].data, 0xc0ffee);
> > > +
> > > +       if (!(flags & CLOSE_FD))
> > > +               for (i = 0; i < n_exec_queues; i++)
> > > +                       xe_exec_queue_destroy(fd,
> > > exec_queues[i]);
> > > +
> > > +       if (bo) {
> > > +               munmap(data, bo_size);
> > > +               gem_close(fd, bo);
> > > +       } else {
> > > +               free(data);
> > > +       }
> > > +
> > > +       if (!(flags & CLOSE_FD))
> > > +               xe_vm_destroy(fd, vm);
> > > +       else
> > > +               drm_close_driver(fd);
> > >  }
> > >  
> > >  static void
> > > @@ -375,12 +506,19 @@ test_legacy_mode(int fd, struct
> > > drm_xe_engine_class_instance *eci, int num_place
> > >   * @userptr:                                   userptr
> > >   * @priority:                                  priority
> > >   * @close-fd:                                  close fd without
> > > destroying exec queues
> > > + * @preempt-mode-basic:                                preempt-
> > > mode
> > > basic
> > > + * @preempt-mode-userptr:                      preempt-mode
> > > userptr
> > > + * @preempt-mode-priority:                     preempt-mode
> > > priority
> > > + * @preempt-mode-close-fd:                     preempt-mode
> > > close fd
> > > without destroying exec queues
> > >   */
> > >  static void
> > >  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> > > num_placement,
> > >           int n_exec_queues, int n_execs, unsigned int flags)
> > >  {
> > > -       test_legacy_mode(fd, eci, num_placement, n_exec_queues,
> > > n_execs, flags);
> > > +       if (flags & PREEMPT_MODE)
> > > +               test_preempt_mode(fd, eci, num_placement,
> > > n_exec_queues, n_execs, flags);
> > > +       else
> > > +               test_legacy_mode(fd, eci, num_placement,
> > > n_exec_queues, n_execs, flags);
> > >  }
> > >  
> > >  /**
> > > @@ -404,6 +542,7 @@ test_exec_virtual(int fd, int gt, int class)
> > >         igt_assert(n);
> > >  
> > >         test_exec(fd, eci, n, n, n, 0);
> > > +       test_exec(fd, eci, n, n, n, PREEMPT_MODE);
> > >  }
> > >  
> > >  igt_main
> > > @@ -417,6 +556,10 @@ igt_main
> > >                 { "userptr", USERPTR },
> > >                 { "priority", PRIORITY },
> > >                 { "close-fd", CLOSE_FD },
> > > +               { "preempt-mode-basic", PREEMPT_MODE },
> > > +               { "preempt-mode-userptr", PREEMPT_MODE | USERPTR
> > > },
> > > +               { "preempt-mode-priority", PREEMPT_MODE |
> > > PRIORITY },
> > > +               { "preempt-mode-close-fd", PREEMPT_MODE |
> > > CLOSE_FD },
> > >                 { NULL },
> > >         };
> > >         int fd, gt, class;
> > 

[PATCH v2 09/19] lib/xe: Add exec_queue set_property ioctl support

[Niranjana Vishwanathapura]

Add infrastructure to support xe_exec_queue_set_property_ioctl()

Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 lib/xe/xe_ioctl.c | 27 +++++++++++++++++++++++++++
 lib/xe/xe_ioctl.h |  4 ++++
 2 files changed, 31 insertions(+)

diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 39c4667a1..319853da0 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -503,6 +503,33 @@ uint32_t xe_exec_queue_create_class(int fd, uint32_t vm, uint16_t class)
 	return create.exec_queue_id;
 }
 
+int __xe_exec_queue_set_property(int fd, uint32_t exec_queue, uint32_t property,
+				 uint64_t value)
+{
+	struct drm_xe_exec_queue_set_property xe_priority = {
+		.property = property,
+		.exec_queue_id = exec_queue,
+		.value  = value,
+	};
+	int err;
+
+	err = igt_ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY, &xe_priority);
+	if (err) {
+		err = -errno;
+		igt_assume(err);
+		errno = 0;
+		return err;
+	}
+
+	return 0;
+}
+
+void xe_exec_queue_set_property(int fd, uint32_t exec_queue, uint32_t property,
+				uint64_t value)
+{
+	igt_assert_eq(__xe_exec_queue_set_property(fd, exec_queue, property, value), 0);
+}
+
 void xe_exec_queue_destroy(int fd, uint32_t exec_queue)
 {
 	struct drm_xe_exec_queue_destroy destroy = {
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index ae8a23a54..a7fd43c9e 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -83,6 +83,10 @@ uint32_t xe_exec_queue_create(int fd, uint32_t vm,
 			  uint64_t ext);
 uint32_t xe_bind_exec_queue_create(int fd, uint32_t vm, uint64_t ext);
 uint32_t xe_exec_queue_create_class(int fd, uint32_t vm, uint16_t class);
+int __xe_exec_queue_set_property(int fd, uint32_t exec_queue, uint32_t property,
+				 uint64_t value);
+void xe_exec_queue_set_property(int fd, uint32_t exec_queue, uint32_t property,
+				uint64_t value);
 void xe_exec_queue_destroy(int fd, uint32_t exec_queue);
 uint64_t xe_bo_mmap_offset(int fd, uint32_t bo);
 void *xe_bo_map(int fd, uint32_t bo, size_t size);
-- 
2.43.0

Re: [PATCH v2 09/19] lib/xe: Add exec_queue set_property ioctl support

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Add infrastructure to support xe_exec_queue_set_property_ioctl()
> 
> Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> ---
>  lib/xe/xe_ioctl.c | 27 +++++++++++++++++++++++++++
>  lib/xe/xe_ioctl.h |  4 ++++
>  2 files changed, 31 insertions(+)
> 
> diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
> index 39c4667a1..319853da0 100644
> --- a/lib/xe/xe_ioctl.c
> +++ b/lib/xe/xe_ioctl.c
> @@ -503,6 +503,33 @@ uint32_t xe_exec_queue_create_class(int fd,
> uint32_t vm, uint16_t class)
>         return create.exec_queue_id;
>  }
>  
> +int __xe_exec_queue_set_property(int fd, uint32_t exec_queue,
> uint32_t property,
> +                                uint64_t value)
> +{
> +       struct drm_xe_exec_queue_set_property xe_priority = {
> +               .property = property,
> +               .exec_queue_id = exec_queue,
> +               .value  = value,
> +       };
> +       int err;
> +
> +       err = igt_ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY,
> &xe_priority);
> +       if (err) {
> +               err = -errno;
> +               igt_assume(err);
> +               errno = 0;
> +               return err;
> +       }
> +
> +       return 0;
> +}
> +
> +void xe_exec_queue_set_property(int fd, uint32_t exec_queue,
> uint32_t property,
> +                               uint64_t value)
> +{
> +       igt_assert_eq(__xe_exec_queue_set_property(fd, exec_queue,
> property, value), 0);
> +}
> +
>  void xe_exec_queue_destroy(int fd, uint32_t exec_queue)
>  {
>         struct drm_xe_exec_queue_destroy destroy = {
> diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
> index ae8a23a54..a7fd43c9e 100644
> --- a/lib/xe/xe_ioctl.h
> +++ b/lib/xe/xe_ioctl.h
> @@ -83,6 +83,10 @@ uint32_t xe_exec_queue_create(int fd, uint32_t vm,
>                           uint64_t ext);
>  uint32_t xe_bind_exec_queue_create(int fd, uint32_t vm, uint64_t
> ext);
>  uint32_t xe_exec_queue_create_class(int fd, uint32_t vm, uint16_t
> class);
> +int __xe_exec_queue_set_property(int fd, uint32_t exec_queue,
> uint32_t property,

I might have missed it, but why are we exposing this one? I don't see
that we use the internal function anywhere, just the wrapper below that
has the assert.

Thanks,
Stuart

> +                                uint64_t value);
> +void xe_exec_queue_set_property(int fd, uint32_t exec_queue,
> uint32_t property,
> +                               uint64_t value);
>  void xe_exec_queue_destroy(int fd, uint32_t exec_queue);
>  uint64_t xe_bo_mmap_offset(int fd, uint32_t bo);
>  void *xe_bo_map(int fd, uint32_t bo, size_t size);

Re: [PATCH v2 09/19] lib/xe: Add exec_queue set_property ioctl support

[Niranjana Vishwanathapura]

On Thu, Dec 04, 2025 at 11:24:01AM -0800, Summers, Stuart wrote:
>On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
>> Add infrastructure to support xe_exec_queue_set_property_ioctl()
>>
>> Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
>> Signed-off-by: Niranjana Vishwanathapura
>> <niranjana.vishwanathapura@intel.com>
>> ---
>>  lib/xe/xe_ioctl.c | 27 +++++++++++++++++++++++++++
>>  lib/xe/xe_ioctl.h |  4 ++++
>>  2 files changed, 31 insertions(+)
>>
>> diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
>> index 39c4667a1..319853da0 100644
>> --- a/lib/xe/xe_ioctl.c
>> +++ b/lib/xe/xe_ioctl.c
>> @@ -503,6 +503,33 @@ uint32_t xe_exec_queue_create_class(int fd,
>> uint32_t vm, uint16_t class)
>>         return create.exec_queue_id;
>>  }
>>  
>> +int __xe_exec_queue_set_property(int fd, uint32_t exec_queue,
>> uint32_t property,
>> +                                uint64_t value)
>> +{
>> +       struct drm_xe_exec_queue_set_property xe_priority = {
>> +               .property = property,
>> +               .exec_queue_id = exec_queue,
>> +               .value  = value,
>> +       };
>> +       int err;
>> +
>> +       err = igt_ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY,
>> &xe_priority);
>> +       if (err) {
>> +               err = -errno;
>> +               igt_assume(err);
>> +               errno = 0;
>> +               return err;
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +void xe_exec_queue_set_property(int fd, uint32_t exec_queue,
>> uint32_t property,
>> +                               uint64_t value)
>> +{
>> +       igt_assert_eq(__xe_exec_queue_set_property(fd, exec_queue,
>> property, value), 0);
>> +}
>> +
>>  void xe_exec_queue_destroy(int fd, uint32_t exec_queue)
>>  {
>>         struct drm_xe_exec_queue_destroy destroy = {
>> diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
>> index ae8a23a54..a7fd43c9e 100644
>> --- a/lib/xe/xe_ioctl.h
>> +++ b/lib/xe/xe_ioctl.h
>> @@ -83,6 +83,10 @@ uint32_t xe_exec_queue_create(int fd, uint32_t vm,
>>                           uint64_t ext);
>>  uint32_t xe_bind_exec_queue_create(int fd, uint32_t vm, uint64_t
>> ext);
>>  uint32_t xe_exec_queue_create_class(int fd, uint32_t vm, uint16_t
>> class);
>> +int __xe_exec_queue_set_property(int fd, uint32_t exec_queue,
>> uint32_t property,
>
>I might have missed it, but why are we exposing this one? I don't see
>that we use the internal function anywhere, just the wrapper below that
>has the assert.
>

These are library routines and it looks customary to add
both of these functions (one that asserts and one that doesn't)
in the library irrespective of tests use it or not currently.
And this patch is for the library update only.

Niranjana

>Thanks,
>Stuart
>
>> +                                uint64_t value);
>> +void xe_exec_queue_set_property(int fd, uint32_t exec_queue,
>> uint32_t property,
>> +                               uint64_t value);
>>  void xe_exec_queue_destroy(int fd, uint32_t exec_queue);
>>  uint64_t xe_bo_mmap_offset(int fd, uint32_t bo);
>>  void *xe_bo_map(int fd, uint32_t bo, size_t size);
>

Re: [PATCH v2 09/19] lib/xe: Add exec_queue set_property ioctl support

[Summers, Stuart]

On Thu, 2025-12-04 at 17:58 -0800, Niranjana Vishwanathapura wrote:
> On Thu, Dec 04, 2025 at 11:24:01AM -0800, Summers, Stuart wrote:
> > On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> > > Add infrastructure to support xe_exec_queue_set_property_ioctl()
> > > 
> > > Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
> > > Signed-off-by: Niranjana Vishwanathapura
> > > <niranjana.vishwanathapura@intel.com>
> > > ---
> > >  lib/xe/xe_ioctl.c | 27 +++++++++++++++++++++++++++
> > >  lib/xe/xe_ioctl.h |  4 ++++
> > >  2 files changed, 31 insertions(+)
> > > 
> > > diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
> > > index 39c4667a1..319853da0 100644
> > > --- a/lib/xe/xe_ioctl.c
> > > +++ b/lib/xe/xe_ioctl.c
> > > @@ -503,6 +503,33 @@ uint32_t xe_exec_queue_create_class(int fd,
> > > uint32_t vm, uint16_t class)
> > >         return create.exec_queue_id;
> > >  }
> > >  
> > > +int __xe_exec_queue_set_property(int fd, uint32_t exec_queue,
> > > uint32_t property,
> > > +                                uint64_t value)
> > > +{
> > > +       struct drm_xe_exec_queue_set_property xe_priority = {
> > > +               .property = property,
> > > +               .exec_queue_id = exec_queue,
> > > +               .value  = value,
> > > +       };
> > > +       int err;
> > > +
> > > +       err = igt_ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY,
> > > &xe_priority);
> > > +       if (err) {
> > > +               err = -errno;
> > > +               igt_assume(err);
> > > +               errno = 0;
> > > +               return err;
> > > +       }
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +void xe_exec_queue_set_property(int fd, uint32_t exec_queue,
> > > uint32_t property,
> > > +                               uint64_t value)
> > > +{
> > > +       igt_assert_eq(__xe_exec_queue_set_property(fd,
> > > exec_queue,
> > > property, value), 0);
> > > +}
> > > +
> > >  void xe_exec_queue_destroy(int fd, uint32_t exec_queue)
> > >  {
> > >         struct drm_xe_exec_queue_destroy destroy = {
> > > diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
> > > index ae8a23a54..a7fd43c9e 100644
> > > --- a/lib/xe/xe_ioctl.h
> > > +++ b/lib/xe/xe_ioctl.h
> > > @@ -83,6 +83,10 @@ uint32_t xe_exec_queue_create(int fd, uint32_t
> > > vm,
> > >                           uint64_t ext);
> > >  uint32_t xe_bind_exec_queue_create(int fd, uint32_t vm, uint64_t
> > > ext);
> > >  uint32_t xe_exec_queue_create_class(int fd, uint32_t vm,
> > > uint16_t
> > > class);
> > > +int __xe_exec_queue_set_property(int fd, uint32_t exec_queue,
> > > uint32_t property,
> > 
> > I might have missed it, but why are we exposing this one? I don't
> > see
> > that we use the internal function anywhere, just the wrapper below
> > that
> > has the assert.
> > 
> 
> These are library routines and it looks customary to add
> both of these functions (one that asserts and one that doesn't)
> in the library irrespective of tests use it or not currently.
> And this patch is for the library update only.

Ok no problem. Let's just stick to the convention.

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> 
> Niranjana
> 
> > Thanks,
> > Stuart
> > 
> > > +                                uint64_t value);
> > > +void xe_exec_queue_set_property(int fd, uint32_t exec_queue,
> > > uint32_t property,
> > > +                               uint64_t value);
> > >  void xe_exec_queue_destroy(int fd, uint32_t exec_queue);
> > >  uint64_t xe_bo_mmap_offset(int fd, uint32_t bo);
> > >  void *xe_bo_map(int fd, uint32_t bo, size_t size);
> > 

[PATCH v2 10/19] tests/intel/xe_exec_multi_queue: Add dynamic priority test

[Niranjana Vishwanathapura]

Add subtest for basic functionality of dynamic priority
change using set_property ioctl.

Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index 1e33c5db8..5d3a209e5 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -29,6 +29,7 @@
 #define PRIORITY		(0x1 << 1)
 #define CLOSE_FD		(0x1 << 2)
 #define PREEMPT_MODE		(0x1 << 3)
+#define DYN_PRIORITY		(0x1 << 4)
 
 #define MAX_INSTANCE 9
 
@@ -306,6 +307,12 @@ test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_plac
 
 		exec.exec_queue_id = exec_queues[e];
 		exec.address = batch_addr;
+
+		if (flags & DYN_PRIORITY)
+			xe_exec_queue_set_property(fd, exec_queues[e],
+						   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
+						   XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2));
+
 		xe_exec(fd, &exec);
 	}
 
@@ -439,6 +446,11 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
 		if (e != i)
 			syncobj_reset(fd, &syncobjs[e], 1);
 
+		if (flags & DYN_PRIORITY)
+			xe_exec_queue_set_property(fd, exec_queues[e],
+						   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
+						   XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2));
+
 		xe_exec(fd, &exec);
 	}
 
@@ -506,10 +518,12 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
  * @userptr:					userptr
  * @priority:					priority
  * @close-fd:					close fd without destroying exec queues
+ * @dyn-priority:				dynamic priority
  * @preempt-mode-basic:				preempt-mode basic
  * @preempt-mode-userptr:			preempt-mode userptr
  * @preempt-mode-priority:			preempt-mode priority
  * @preempt-mode-close-fd:			preempt-mode close fd without destroying exec queues
+ * @preempt-mode-dyn-priority:			preempt-mode dynamic priority
  */
 static void
 test_exec(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
@@ -556,10 +570,12 @@ igt_main
 		{ "userptr", USERPTR },
 		{ "priority", PRIORITY },
 		{ "close-fd", CLOSE_FD },
+		{ "dyn-priority", DYN_PRIORITY },
 		{ "preempt-mode-basic", PREEMPT_MODE },
 		{ "preempt-mode-userptr", PREEMPT_MODE | USERPTR },
 		{ "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
 		{ "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
+		{ "preempt-mode-dyn-priority", PREEMPT_MODE | DYN_PRIORITY },
 		{ NULL },
 	};
 	int fd, gt, class;
-- 
2.43.0

Re: [PATCH v2 10/19] tests/intel/xe_exec_multi_queue: Add dynamic priority test

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Add subtest for basic functionality of dynamic priority
> change using set_property ioctl.
> 
> Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> Reviewed-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> ---
>  tests/intel/xe_exec_multi_queue.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index 1e33c5db8..5d3a209e5 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -29,6 +29,7 @@
>  #define PRIORITY               (0x1 << 1)
>  #define CLOSE_FD               (0x1 << 2)
>  #define PREEMPT_MODE           (0x1 << 3)
> +#define DYN_PRIORITY           (0x1 << 4)
>  
>  #define MAX_INSTANCE 9
>  
> @@ -306,6 +307,12 @@ test_preempt_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_plac
>  
>                 exec.exec_queue_id = exec_queues[e];
>                 exec.address = batch_addr;
> +
> +               if (flags & DYN_PRIORITY)
> +                       xe_exec_queue_set_property(fd,
> exec_queues[e],
> +                                                 
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> +                                                 
> XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2));
> +
>                 xe_exec(fd, &exec);
>         }
>  
> @@ -439,6 +446,11 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>                 if (e != i)
>                         syncobj_reset(fd, &syncobjs[e], 1);
>  
> +               if (flags & DYN_PRIORITY)
> +                       xe_exec_queue_set_property(fd,
> exec_queues[e],
> +                                                 
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> +                                                 
> XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2));
> +
>                 xe_exec(fd, &exec);
>         }
>  
> @@ -506,10 +518,12 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>   * @userptr:                                   userptr
>   * @priority:                                  priority
>   * @close-fd:                                  close fd without
> destroying exec queues
> + * @dyn-priority:                              dynamic priority
>   * @preempt-mode-basic:                                preempt-mode
> basic
>   * @preempt-mode-userptr:                      preempt-mode userptr
>   * @preempt-mode-priority:                     preempt-mode priority
>   * @preempt-mode-close-fd:                     preempt-mode close fd
> without destroying exec queues
> + * @preempt-mode-dyn-priority:                 preempt-mode dynamic
> priority
>   */
>  static void
>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement,
> @@ -556,10 +570,12 @@ igt_main
>                 { "userptr", USERPTR },
>                 { "priority", PRIORITY },
>                 { "close-fd", CLOSE_FD },
> +               { "dyn-priority", DYN_PRIORITY },
>                 { "preempt-mode-basic", PREEMPT_MODE },
>                 { "preempt-mode-userptr", PREEMPT_MODE | USERPTR },
>                 { "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
>                 { "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
> +               { "preempt-mode-dyn-priority", PREEMPT_MODE |
> DYN_PRIORITY },
>                 { NULL },
>         };
>         int fd, gt, class;

[PATCH v2 11/19] tests/intel/xe_exec_multi_queue: Add userptr invalidation tests

[Niranjana Vishwanathapura]

Add validation support for userptr invalidation. For normal tests,
userptr invalidation will happen after all the gpu jobs using that
userptr are complete. For preempt mode tests, userptr invalidation
suspends the execution queue and resumes it after invalidation is
complete.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 95 +++++++++++++++++++++++++------
 1 file changed, 78 insertions(+), 17 deletions(-)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index 5d3a209e5..aa86f8a38 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -30,6 +30,7 @@
 #define CLOSE_FD		(0x1 << 2)
 #define PREEMPT_MODE		(0x1 << 3)
 #define DYN_PRIORITY		(0x1 << 4)
+#define INVALIDATE		(0x1 << 5)
 
 #define MAX_INSTANCE 9
 
@@ -247,9 +248,16 @@ test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_plac
 	bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
 
 	if (flags & USERPTR) {
-		data = aligned_alloc(xe_get_default_alignment(fd), bo_size);
-		igt_assert(data);
-
+#define	MAP_ADDRESS	0x00007fadeadbe000
+		if (flags & INVALIDATE) {
+			data = mmap((void *)MAP_ADDRESS, bo_size, PROT_READ |
+				    PROT_WRITE, MAP_SHARED | MAP_FIXED |
+				    MAP_ANONYMOUS, -1, 0);
+			igt_assert(data != MAP_FAILED);
+		} else {
+			data = aligned_alloc(xe_get_default_alignment(fd), bo_size);
+			igt_assert(data);
+		}
 		memset(data, 0, bo_size);
 	} else {
 		bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
@@ -314,18 +322,40 @@ test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_plac
 						   XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2));
 
 		xe_exec(fd, &exec);
+
+		if (flags & INVALIDATE) {
+			/*
+			 * Wait for exec completion and check data as userptr will
+			 * likely change to different physical memory on next mmap
+			 * call triggering an invalidate.
+			 */
+			xe_wait_ufence(fd, &data[i].exec_sync,
+				       USER_FENCE_VALUE, exec_queues[e],
+				       fence_timeout);
+			igt_assert_eq(data[i].data, 0xc0ffee);
+
+			if (i) {
+				data = mmap((void *)MAP_ADDRESS, bo_size,
+					    PROT_READ | PROT_WRITE, MAP_SHARED |
+					    MAP_FIXED | MAP_ANONYMOUS, -1, 0);
+				igt_assert(data != MAP_FAILED);
+			}
+
+		}
 	}
 
-	for (i = 0; i < n_execs; i++)
-		xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE,
-			       exec_queues[i % n_exec_queues], fence_timeout);
+	if (!(flags & INVALIDATE))
+		for (i = 0; i < n_execs; i++)
+			xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE,
+				       exec_queues[i % n_exec_queues], fence_timeout);
 
 	sync.addr = to_user_pointer(&vm_sync);
 	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
 	xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, fence_timeout);
 
-	for (i = 0; i < n_execs; i++)
-		igt_assert_eq(data[i].data, 0xc0ffee);
+	if (!(flags & INVALIDATE))
+		for (i = 0; i < n_execs; i++)
+			igt_assert_eq(data[i].data, 0xc0ffee);
 
 	if (!(flags & CLOSE_FD))
 		for (i = 0; i < n_exec_queues; i++)
@@ -334,7 +364,7 @@ test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_plac
 	if (bo) {
 		munmap(data, bo_size);
 		gem_close(fd, bo);
-	} else {
+	} else if (!(flags & INVALIDATE)) {
 		free(data);
 	}
 
@@ -380,9 +410,16 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
 	bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
 
 	if (flags & USERPTR) {
-		data = aligned_alloc(xe_get_default_alignment(fd), bo_size);
-		igt_assert(data);
-
+#define	MAP_ADDRESS	0x00007fadeadbe000
+		if (flags & INVALIDATE) {
+			data = mmap((void *)MAP_ADDRESS, bo_size, PROT_READ |
+				    PROT_WRITE, MAP_SHARED | MAP_FIXED |
+				    MAP_ANONYMOUS, -1, 0);
+			igt_assert(data != MAP_FAILED);
+		} else {
+			data = aligned_alloc(xe_get_default_alignment(fd), bo_size);
+			igt_assert(data);
+		}
 		memset(data, 0, bo_size);
 	} else {
 		bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
@@ -452,10 +489,29 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
 						   XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2));
 
 		xe_exec(fd, &exec);
+
+		if (flags & INVALIDATE) {
+			/*
+			 * Wait for exec completion and check data as userptr will
+			 * likely change to different physical memory on next mmap
+			 * call triggering an invalidate.
+			 */
+			igt_assert(syncobj_wait(fd, &syncobjs[e], 1,
+						INT64_MAX, 0, NULL));
+			igt_assert_eq(data[i].data, 0xc0ffee);
+
+			if (i) {
+				data = mmap((void *)MAP_ADDRESS, bo_size, PROT_READ |
+					    PROT_WRITE, MAP_SHARED | MAP_FIXED |
+					    MAP_ANONYMOUS, -1, 0);
+				igt_assert(data != MAP_FAILED);
+			}
+		}
 	}
 
-	for (i = 0; i < n_exec_queues && i < n_execs; i++)
-		igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0, NULL));
+	if (!(flags & INVALIDATE))
+		for (i = 0; i < n_exec_queues && i < n_execs; i++)
+			igt_assert(syncobj_wait(fd, &syncobjs[i], 1, INT64_MAX, 0, NULL));
 
 	igt_assert(syncobj_wait(fd, &bind_syncobj, 1, INT64_MAX, 0, NULL));
 	sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
@@ -463,8 +519,9 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
 	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
 	igt_assert(syncobj_wait(fd, &sync[0].handle, 1,	INT64_MAX, 0, NULL));
 
-	for (i = 0; i < n_execs; i++)
-		igt_assert_eq(data[i].data, 0xc0ffee);
+	if (!(flags & INVALIDATE))
+		for (i = 0; i < n_execs; i++)
+			igt_assert_eq(data[i].data, 0xc0ffee);
 
 	for (i = 0; i < n_exec_queues; i++) {
 		syncobj_destroy(fd, syncobjs[i]);
@@ -475,7 +532,7 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
 	if (bo) {
 		munmap(data, bo_size);
 		gem_close(fd, bo);
-	} else {
+	} else if (!(flags & INVALIDATE)) {
 		free(data);
 	}
 
@@ -516,11 +573,13 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
  *
  * @basic:					basic
  * @userptr:					userptr
+ * @userptr-invalidate:				userptr invalidate
  * @priority:					priority
  * @close-fd:					close fd without destroying exec queues
  * @dyn-priority:				dynamic priority
  * @preempt-mode-basic:				preempt-mode basic
  * @preempt-mode-userptr:			preempt-mode userptr
+ * @preempt-mode-userptr-invalidate:		preempt-mode userptr invalidate
  * @preempt-mode-priority:			preempt-mode priority
  * @preempt-mode-close-fd:			preempt-mode close fd without destroying exec queues
  * @preempt-mode-dyn-priority:			preempt-mode dynamic priority
@@ -568,11 +627,13 @@ igt_main
 	} sections[] = {
 		{ "basic", 0 },
 		{ "userptr", USERPTR },
+		{ "userptr-invalidate", USERPTR | INVALIDATE },
 		{ "priority", PRIORITY },
 		{ "close-fd", CLOSE_FD },
 		{ "dyn-priority", DYN_PRIORITY },
 		{ "preempt-mode-basic", PREEMPT_MODE },
 		{ "preempt-mode-userptr", PREEMPT_MODE | USERPTR },
+		{ "preempt-mode-userptr-invalidate", PREEMPT_MODE | USERPTR | INVALIDATE },
 		{ "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
 		{ "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
 		{ "preempt-mode-dyn-priority", PREEMPT_MODE | DYN_PRIORITY },
-- 
2.43.0

Re: [PATCH v2 11/19] tests/intel/xe_exec_multi_queue: Add userptr invalidation tests

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Add validation support for userptr invalidation. For normal tests,
> userptr invalidation will happen after all the gpu jobs using that
> userptr are complete. For preempt mode tests, userptr invalidation
> suspends the execution queue and resumes it after invalidation is
> complete.
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>

I still have the question about duplicated code in the preempt path,
but otherwise this looks good:
Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> ---
>  tests/intel/xe_exec_multi_queue.c | 95 +++++++++++++++++++++++++----
> --
>  1 file changed, 78 insertions(+), 17 deletions(-)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index 5d3a209e5..aa86f8a38 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -30,6 +30,7 @@
>  #define CLOSE_FD               (0x1 << 2)
>  #define PREEMPT_MODE           (0x1 << 3)
>  #define DYN_PRIORITY           (0x1 << 4)
> +#define INVALIDATE             (0x1 << 5)
>  
>  #define MAX_INSTANCE 9
>  
> @@ -247,9 +248,16 @@ test_preempt_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_plac
>         bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
>  
>         if (flags & USERPTR) {
> -               data = aligned_alloc(xe_get_default_alignment(fd),
> bo_size);
> -               igt_assert(data);
> -
> +#define        MAP_ADDRESS     0x00007fadeadbe000
> +               if (flags & INVALIDATE) {
> +                       data = mmap((void *)MAP_ADDRESS, bo_size,
> PROT_READ |
> +                                   PROT_WRITE, MAP_SHARED |
> MAP_FIXED |
> +                                   MAP_ANONYMOUS, -1, 0);
> +                       igt_assert(data != MAP_FAILED);
> +               } else {
> +                       data =
> aligned_alloc(xe_get_default_alignment(fd), bo_size);
> +                       igt_assert(data);
> +               }
>                 memset(data, 0, bo_size);
>         } else {
>                 bo = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> @@ -314,18 +322,40 @@ test_preempt_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_plac
>                                                   
> XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2));
>  
>                 xe_exec(fd, &exec);
> +
> +               if (flags & INVALIDATE) {
> +                       /*
> +                        * Wait for exec completion and check data as
> userptr will
> +                        * likely change to different physical memory
> on next mmap
> +                        * call triggering an invalidate.
> +                        */
> +                       xe_wait_ufence(fd, &data[i].exec_sync,
> +                                      USER_FENCE_VALUE,
> exec_queues[e],
> +                                      fence_timeout);
> +                       igt_assert_eq(data[i].data, 0xc0ffee);
> +
> +                       if (i) {
> +                               data = mmap((void *)MAP_ADDRESS,
> bo_size,
> +                                           PROT_READ | PROT_WRITE,
> MAP_SHARED |
> +                                           MAP_FIXED |
> MAP_ANONYMOUS, -1, 0);
> +                               igt_assert(data != MAP_FAILED);
> +                       }
> +
> +               }
>         }
>  
> -       for (i = 0; i < n_execs; i++)
> -               xe_wait_ufence(fd, &data[i].exec_sync,
> USER_FENCE_VALUE,
> -                              exec_queues[i % n_exec_queues],
> fence_timeout);
> +       if (!(flags & INVALIDATE))
> +               for (i = 0; i < n_execs; i++)
> +                       xe_wait_ufence(fd, &data[i].exec_sync,
> USER_FENCE_VALUE,
> +                                      exec_queues[i %
> n_exec_queues], fence_timeout);
>  
>         sync.addr = to_user_pointer(&vm_sync);
>         xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
>         xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
> fence_timeout);
>  
> -       for (i = 0; i < n_execs; i++)
> -               igt_assert_eq(data[i].data, 0xc0ffee);
> +       if (!(flags & INVALIDATE))
> +               for (i = 0; i < n_execs; i++)
> +                       igt_assert_eq(data[i].data, 0xc0ffee);
>  
>         if (!(flags & CLOSE_FD))
>                 for (i = 0; i < n_exec_queues; i++)
> @@ -334,7 +364,7 @@ test_preempt_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_plac
>         if (bo) {
>                 munmap(data, bo_size);
>                 gem_close(fd, bo);
> -       } else {
> +       } else if (!(flags & INVALIDATE)) {
>                 free(data);
>         }
>  
> @@ -380,9 +410,16 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>         bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
>  
>         if (flags & USERPTR) {
> -               data = aligned_alloc(xe_get_default_alignment(fd),
> bo_size);
> -               igt_assert(data);
> -
> +#define        MAP_ADDRESS     0x00007fadeadbe000
> +               if (flags & INVALIDATE) {
> +                       data = mmap((void *)MAP_ADDRESS, bo_size,
> PROT_READ |
> +                                   PROT_WRITE, MAP_SHARED |
> MAP_FIXED |
> +                                   MAP_ANONYMOUS, -1, 0);
> +                       igt_assert(data != MAP_FAILED);
> +               } else {
> +                       data =
> aligned_alloc(xe_get_default_alignment(fd), bo_size);
> +                       igt_assert(data);
> +               }
>                 memset(data, 0, bo_size);
>         } else {
>                 bo = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> @@ -452,10 +489,29 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>                                                   
> XE_EXEC_QUEUE_PRIORITY_NORMAL + (rand() % 2));
>  
>                 xe_exec(fd, &exec);
> +
> +               if (flags & INVALIDATE) {
> +                       /*
> +                        * Wait for exec completion and check data as
> userptr will
> +                        * likely change to different physical memory
> on next mmap
> +                        * call triggering an invalidate.
> +                        */
> +                       igt_assert(syncobj_wait(fd, &syncobjs[e], 1,
> +                                               INT64_MAX, 0, NULL));
> +                       igt_assert_eq(data[i].data, 0xc0ffee);
> +
> +                       if (i) {
> +                               data = mmap((void *)MAP_ADDRESS,
> bo_size, PROT_READ |
> +                                           PROT_WRITE, MAP_SHARED |
> MAP_FIXED |
> +                                           MAP_ANONYMOUS, -1, 0);
> +                               igt_assert(data != MAP_FAILED);
> +                       }
> +               }
>         }
>  
> -       for (i = 0; i < n_exec_queues && i < n_execs; i++)
> -               igt_assert(syncobj_wait(fd, &syncobjs[i], 1,
> INT64_MAX, 0, NULL));
> +       if (!(flags & INVALIDATE))
> +               for (i = 0; i < n_exec_queues && i < n_execs; i++)
> +                       igt_assert(syncobj_wait(fd, &syncobjs[i], 1,
> INT64_MAX, 0, NULL));
>  
>         igt_assert(syncobj_wait(fd, &bind_syncobj, 1, INT64_MAX, 0,
> NULL));
>         sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> @@ -463,8 +519,9 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>         xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
>         igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0,
> NULL));
>  
> -       for (i = 0; i < n_execs; i++)
> -               igt_assert_eq(data[i].data, 0xc0ffee);
> +       if (!(flags & INVALIDATE))
> +               for (i = 0; i < n_execs; i++)
> +                       igt_assert_eq(data[i].data, 0xc0ffee);
>  
>         for (i = 0; i < n_exec_queues; i++) {
>                 syncobj_destroy(fd, syncobjs[i]);
> @@ -475,7 +532,7 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>         if (bo) {
>                 munmap(data, bo_size);
>                 gem_close(fd, bo);
> -       } else {
> +       } else if (!(flags & INVALIDATE)) {
>                 free(data);
>         }
>  
> @@ -516,11 +573,13 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>   *
>   * @basic:                                     basic
>   * @userptr:                                   userptr
> + * @userptr-invalidate:                                userptr
> invalidate
>   * @priority:                                  priority
>   * @close-fd:                                  close fd without
> destroying exec queues
>   * @dyn-priority:                              dynamic priority
>   * @preempt-mode-basic:                                preempt-mode
> basic
>   * @preempt-mode-userptr:                      preempt-mode userptr
> + * @preempt-mode-userptr-invalidate:           preempt-mode userptr
> invalidate
>   * @preempt-mode-priority:                     preempt-mode priority
>   * @preempt-mode-close-fd:                     preempt-mode close fd
> without destroying exec queues
>   * @preempt-mode-dyn-priority:                 preempt-mode dynamic
> priority
> @@ -568,11 +627,13 @@ igt_main
>         } sections[] = {
>                 { "basic", 0 },
>                 { "userptr", USERPTR },
> +               { "userptr-invalidate", USERPTR | INVALIDATE },
>                 { "priority", PRIORITY },
>                 { "close-fd", CLOSE_FD },
>                 { "dyn-priority", DYN_PRIORITY },
>                 { "preempt-mode-basic", PREEMPT_MODE },
>                 { "preempt-mode-userptr", PREEMPT_MODE | USERPTR },
> +               { "preempt-mode-userptr-invalidate", PREEMPT_MODE |
> USERPTR | INVALIDATE },
>                 { "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
>                 { "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
>                 { "preempt-mode-dyn-priority", PREEMPT_MODE |
> DYN_PRIORITY },

[PATCH v2 12/19] tests/intel/xe_exec_multi_queue: Add fault mode test

[Niranjana Vishwanathapura]

From: Nakshtra Goyal <nakshtra.goyal@intel.com>

Test multiq functionality with fault mode. Adding a flag check for
xe_vm_create for fault mode test cases.

Signed-off-by: Nakshtra Goyal <nakshtra.goyal@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index aa86f8a38..da8117d57 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -31,6 +31,7 @@
 #define PREEMPT_MODE		(0x1 << 3)
 #define DYN_PRIORITY		(0x1 << 4)
 #define INVALIDATE		(0x1 << 5)
+#define FAULT_MODE		(0x1 << 6)
 
 #define MAX_INSTANCE 9
 
@@ -244,7 +245,12 @@ test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_plac
 		fd = drm_open_driver(DRIVER_XE);
 
 	igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
-	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
+	if (flags & FAULT_MODE)
+		vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE |
+				  DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0);
+	else
+		vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
+
 	bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
 
 	if (flags & USERPTR) {
@@ -583,6 +589,12 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
  * @preempt-mode-priority:			preempt-mode priority
  * @preempt-mode-close-fd:			preempt-mode close fd without destroying exec queues
  * @preempt-mode-dyn-priority:			preempt-mode dynamic priority
+ * @preempt-mode-fault-basic:			preempt-mode-fault-mode basic
+ * @preempt-mode-fault-userptr:			preempt-mode-fault-mode userptr
+ * @preempt-mode-fault-userptr-invalidate:	preempt-mode-fault-mode userptr invalidate
+ * @preempt-mode-fault-priority:		preempt-mode-fault-mode priority
+ * @preempt-mode-fault-close-fd:		preempt-mode-fault-mode close fd
+ * @preempt-mode-fault-dyn-priority:		preempt-mode-fault-mode dynamic priority
  */
 static void
 test_exec(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
@@ -637,6 +649,13 @@ igt_main
 		{ "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
 		{ "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
 		{ "preempt-mode-dyn-priority", PREEMPT_MODE | DYN_PRIORITY },
+		{ "preempt-mode-fault-basic", PREEMPT_MODE | FAULT_MODE },
+		{ "preempt-mode-fault-userptr", PREEMPT_MODE | FAULT_MODE | USERPTR },
+		{ "preempt-mode-fault-userptr-invalidate", PREEMPT_MODE | FAULT_MODE |
+			USERPTR | INVALIDATE },
+		{ "preempt-mode-fault-priority", PREEMPT_MODE | FAULT_MODE | PRIORITY },
+		{ "preempt-mode-fault-close-fd", PREEMPT_MODE | FAULT_MODE | CLOSE_FD },
+		{ "preempt-mode-fault-dyn-priority", PREEMPT_MODE | FAULT_MODE | DYN_PRIORITY },
 		{ NULL },
 	};
 	int fd, gt, class;
-- 
2.43.0

RE: [PATCH v2 12/19] tests/intel/xe_exec_multi_queue: Add fault mode test

[Goyal, Nakshtra]

> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of
> Niranjana Vishwanathapura
> Sent: 21 November 2025 09:27
> To: igt-dev@lists.freedesktop.org
> Cc: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>; kamil.konieczny@linux.intel.com
> Subject: [PATCH v2 12/19] tests/intel/xe_exec_multi_queue: Add fault mode
> test
> 
> From: Nakshtra Goyal <nakshtra.goyal@intel.com>
> 
> Test multiq functionality with fault mode. Adding a flag check for
> xe_vm_create for fault mode test cases.
> 
> Signed-off-by: Nakshtra Goyal <nakshtra.goyal@intel.com>
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
Looks good to me
Reviewed-by: Nakshtra Goyal <nakshtra.goyal@intel.com>

> ---
>  tests/intel/xe_exec_multi_queue.c | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index aa86f8a38..da8117d57 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -31,6 +31,7 @@
>  #define PREEMPT_MODE		(0x1 << 3)
>  #define DYN_PRIORITY		(0x1 << 4)
>  #define INVALIDATE		(0x1 << 5)
> +#define FAULT_MODE		(0x1 << 6)
> 
>  #define MAX_INSTANCE 9
> 
> @@ -244,7 +245,12 @@ test_preempt_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_plac
>  		fd = drm_open_driver(DRIVER_XE);
> 
>  	igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
> -	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> +	if (flags & FAULT_MODE)
> +		vm = xe_vm_create(fd,
> DRM_XE_VM_CREATE_FLAG_LR_MODE |
> +				  DRM_XE_VM_CREATE_FLAG_FAULT_MODE,
> 0);
> +	else
> +		vm = xe_vm_create(fd,
> DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> +
>  	bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
> 
>  	if (flags & USERPTR) {
> @@ -583,6 +589,12 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>   * @preempt-mode-priority:			preempt-mode priority
>   * @preempt-mode-close-fd:			preempt-mode close fd
> without destroying exec queues
>   * @preempt-mode-dyn-priority:			preempt-mode
> dynamic priority
> + * @preempt-mode-fault-basic:			preempt-mode-fault-
> mode basic
> + * @preempt-mode-fault-userptr:			preempt-mode-fault-
> mode userptr
> + * @preempt-mode-fault-userptr-invalidate:	preempt-mode-fault-mode
> userptr invalidate
> + * @preempt-mode-fault-priority:		preempt-mode-fault-mode
> priority
> + * @preempt-mode-fault-close-fd:		preempt-mode-fault-mode
> close fd
> + * @preempt-mode-fault-dyn-priority:		preempt-mode-fault-mode
> dynamic priority
>   */
>  static void
>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement, @@ -637,6 +649,13 @@ igt_main
>  		{ "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
>  		{ "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
>  		{ "preempt-mode-dyn-priority", PREEMPT_MODE |
> DYN_PRIORITY },
> +		{ "preempt-mode-fault-basic", PREEMPT_MODE |
> FAULT_MODE },
> +		{ "preempt-mode-fault-userptr", PREEMPT_MODE |
> FAULT_MODE | USERPTR },
> +		{ "preempt-mode-fault-userptr-invalidate", PREEMPT_MODE
> | FAULT_MODE |
> +			USERPTR | INVALIDATE },
> +		{ "preempt-mode-fault-priority", PREEMPT_MODE |
> FAULT_MODE | PRIORITY },
> +		{ "preempt-mode-fault-close-fd", PREEMPT_MODE |
> FAULT_MODE | CLOSE_FD },
> +		{ "preempt-mode-fault-dyn-priority", PREEMPT_MODE |
> FAULT_MODE |
> +DYN_PRIORITY },
>  		{ NULL },
>  	};
>  	int fd, gt, class;
> --
> 2.43.0

Re: [PATCH v2 12/19] tests/intel/xe_exec_multi_queue: Add fault mode test

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> From: Nakshtra Goyal <nakshtra.goyal@intel.com>
> 
> Test multiq functionality with fault mode. Adding a flag check for
> xe_vm_create for fault mode test cases.
> 
> Signed-off-by: Nakshtra Goyal <nakshtra.goyal@intel.com>
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> ---
>  tests/intel/xe_exec_multi_queue.c | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index aa86f8a38..da8117d57 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -31,6 +31,7 @@
>  #define PREEMPT_MODE           (0x1 << 3)
>  #define DYN_PRIORITY           (0x1 << 4)
>  #define INVALIDATE             (0x1 << 5)
> +#define FAULT_MODE             (0x1 << 6)
>  
>  #define MAX_INSTANCE 9
>  
> @@ -244,7 +245,12 @@ test_preempt_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_plac
>                 fd = drm_open_driver(DRIVER_XE);
>  
>         igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
> -       vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> +       if (flags & FAULT_MODE)
> +               vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE |
> +                                 DRM_XE_VM_CREATE_FLAG_FAULT_MODE,

Does it make sense to test only fault mode (separately from only LR and
LR+FAULT) if we eventually plan to drop the LR mode support? We have
this case covered in other tests as well.

Thanks,
Stuart

> 0);
> +       else
> +               vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE,
> 0);
> +
>         bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
>  
>         if (flags & USERPTR) {
> @@ -583,6 +589,12 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>   * @preempt-mode-priority:                     preempt-mode priority
>   * @preempt-mode-close-fd:                     preempt-mode close fd
> without destroying exec queues
>   * @preempt-mode-dyn-priority:                 preempt-mode dynamic
> priority
> + * @preempt-mode-fault-basic:                  preempt-mode-fault-
> mode basic
> + * @preempt-mode-fault-userptr:                        preempt-mode-
> fault-mode userptr
> + * @preempt-mode-fault-userptr-invalidate:     preempt-mode-fault-
> mode userptr invalidate
> + * @preempt-mode-fault-priority:               preempt-mode-fault-
> mode priority
> + * @preempt-mode-fault-close-fd:               preempt-mode-fault-
> mode close fd
> + * @preempt-mode-fault-dyn-priority:           preempt-mode-fault-
> mode dynamic priority
>   */
>  static void
>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement,
> @@ -637,6 +649,13 @@ igt_main
>                 { "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
>                 { "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
>                 { "preempt-mode-dyn-priority", PREEMPT_MODE |
> DYN_PRIORITY },
> +               { "preempt-mode-fault-basic", PREEMPT_MODE |
> FAULT_MODE },
> +               { "preempt-mode-fault-userptr", PREEMPT_MODE |
> FAULT_MODE | USERPTR },
> +               { "preempt-mode-fault-userptr-invalidate",
> PREEMPT_MODE | FAULT_MODE |
> +                       USERPTR | INVALIDATE },
> +               { "preempt-mode-fault-priority", PREEMPT_MODE |
> FAULT_MODE | PRIORITY },
> +               { "preempt-mode-fault-close-fd", PREEMPT_MODE |
> FAULT_MODE | CLOSE_FD },
> +               { "preempt-mode-fault-dyn-priority", PREEMPT_MODE |
> FAULT_MODE | DYN_PRIORITY },
>                 { NULL },
>         };
>         int fd, gt, class;

Re: [PATCH v2 12/19] tests/intel/xe_exec_multi_queue: Add fault mode test

[Niranjana Vishwanathapura]

On Thu, Dec 04, 2025 at 12:59:09PM -0800, Summers, Stuart wrote:
>On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
>> From: Nakshtra Goyal <nakshtra.goyal@intel.com>
>>
>> Test multiq functionality with fault mode. Adding a flag check for
>> xe_vm_create for fault mode test cases.
>>
>> Signed-off-by: Nakshtra Goyal <nakshtra.goyal@intel.com>
>> Signed-off-by: Niranjana Vishwanathapura
>> <niranjana.vishwanathapura@intel.com>
>> ---
>>  tests/intel/xe_exec_multi_queue.c | 21 ++++++++++++++++++++-
>>  1 file changed, 20 insertions(+), 1 deletion(-)
>>
>> diff --git a/tests/intel/xe_exec_multi_queue.c
>> b/tests/intel/xe_exec_multi_queue.c
>> index aa86f8a38..da8117d57 100644
>> --- a/tests/intel/xe_exec_multi_queue.c
>> +++ b/tests/intel/xe_exec_multi_queue.c
>> @@ -31,6 +31,7 @@
>>  #define PREEMPT_MODE           (0x1 << 3)
>>  #define DYN_PRIORITY           (0x1 << 4)
>>  #define INVALIDATE             (0x1 << 5)
>> +#define FAULT_MODE             (0x1 << 6)
>>  
>>  #define MAX_INSTANCE 9
>>  
>> @@ -244,7 +245,12 @@ test_preempt_mode(int fd, struct
>> drm_xe_engine_class_instance *eci, int num_plac
>>                 fd = drm_open_driver(DRIVER_XE);
>>  
>>         igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
>> -       vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
>> +       if (flags & FAULT_MODE)
>> +               vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE |
>> +                                 DRM_XE_VM_CREATE_FLAG_FAULT_MODE,
>
>Does it make sense to test only fault mode (separately from only LR and
>LR+FAULT) if we eventually plan to drop the LR mode support? We have
>this case covered in other tests as well.
>

FAULT mode is only supported along with LR mode. So, FAULT only mode is
supported. LR only mode is supported, but KEEP_ACTIVE flag is not supported
in that mode. So, I think we are good here.

Niranjana

>Thanks,
>Stuart
>
>> 0);
>> +       else
>> +               vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE,
>> 0);
>> +
>>         bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
>>  
>>         if (flags & USERPTR) {
>> @@ -583,6 +589,12 @@ test_legacy_mode(int fd, struct
>> drm_xe_engine_class_instance *eci, int num_place
>>   * @preempt-mode-priority:                     preempt-mode priority
>>   * @preempt-mode-close-fd:                     preempt-mode close fd
>> without destroying exec queues
>>   * @preempt-mode-dyn-priority:                 preempt-mode dynamic
>> priority
>> + * @preempt-mode-fault-basic:                  preempt-mode-fault-
>> mode basic
>> + * @preempt-mode-fault-userptr:                        preempt-mode-
>> fault-mode userptr
>> + * @preempt-mode-fault-userptr-invalidate:     preempt-mode-fault-
>> mode userptr invalidate
>> + * @preempt-mode-fault-priority:               preempt-mode-fault-
>> mode priority
>> + * @preempt-mode-fault-close-fd:               preempt-mode-fault-
>> mode close fd
>> + * @preempt-mode-fault-dyn-priority:           preempt-mode-fault-
>> mode dynamic priority
>>   */
>>  static void
>>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
>> num_placement,
>> @@ -637,6 +649,13 @@ igt_main
>>                 { "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
>>                 { "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
>>                 { "preempt-mode-dyn-priority", PREEMPT_MODE |
>> DYN_PRIORITY },
>> +               { "preempt-mode-fault-basic", PREEMPT_MODE |
>> FAULT_MODE },
>> +               { "preempt-mode-fault-userptr", PREEMPT_MODE |
>> FAULT_MODE | USERPTR },
>> +               { "preempt-mode-fault-userptr-invalidate",
>> PREEMPT_MODE | FAULT_MODE |
>> +                       USERPTR | INVALIDATE },
>> +               { "preempt-mode-fault-priority", PREEMPT_MODE |
>> FAULT_MODE | PRIORITY },
>> +               { "preempt-mode-fault-close-fd", PREEMPT_MODE |
>> FAULT_MODE | CLOSE_FD },
>> +               { "preempt-mode-fault-dyn-priority", PREEMPT_MODE |
>> FAULT_MODE | DYN_PRIORITY },
>>                 { NULL },
>>         };
>>         int fd, gt, class;
>

Re: [PATCH v2 12/19] tests/intel/xe_exec_multi_queue: Add fault mode test

[Summers, Stuart]

On Thu, 2025-12-04 at 15:25 -0800, Niranjana Vishwanathapura wrote:
> On Thu, Dec 04, 2025 at 12:59:09PM -0800, Summers, Stuart wrote:
> > On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> > > From: Nakshtra Goyal <nakshtra.goyal@intel.com>
> > > 
> > > Test multiq functionality with fault mode. Adding a flag check
> > > for
> > > xe_vm_create for fault mode test cases.
> > > 
> > > Signed-off-by: Nakshtra Goyal <nakshtra.goyal@intel.com>
> > > Signed-off-by: Niranjana Vishwanathapura
> > > <niranjana.vishwanathapura@intel.com>
> > > ---
> > >  tests/intel/xe_exec_multi_queue.c | 21 ++++++++++++++++++++-
> > >  1 file changed, 20 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/tests/intel/xe_exec_multi_queue.c
> > > b/tests/intel/xe_exec_multi_queue.c
> > > index aa86f8a38..da8117d57 100644
> > > --- a/tests/intel/xe_exec_multi_queue.c
> > > +++ b/tests/intel/xe_exec_multi_queue.c
> > > @@ -31,6 +31,7 @@
> > >  #define PREEMPT_MODE           (0x1 << 3)
> > >  #define DYN_PRIORITY           (0x1 << 4)
> > >  #define INVALIDATE             (0x1 << 5)
> > > +#define FAULT_MODE             (0x1 << 6)
> > >  
> > >  #define MAX_INSTANCE 9
> > >  
> > > @@ -244,7 +245,12 @@ test_preempt_mode(int fd, struct
> > > drm_xe_engine_class_instance *eci, int num_plac
> > >                 fd = drm_open_driver(DRIVER_XE);
> > >  
> > >         igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
> > > -       vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> > > +       if (flags & FAULT_MODE)
> > > +               vm = xe_vm_create(fd,
> > > DRM_XE_VM_CREATE_FLAG_LR_MODE |
> > > +                                
> > > DRM_XE_VM_CREATE_FLAG_FAULT_MODE,
> > 
> > Does it make sense to test only fault mode (separately from only LR
> > and
> > LR+FAULT) if we eventually plan to drop the LR mode support? We
> > have
> > this case covered in other tests as well.
> > 
> 
> FAULT mode is only supported along with LR mode. So, FAULT only mode
> is
> supported. LR only mode is supported, but KEEP_ACTIVE flag is not
> supported
> in that mode. So, I think we are good here.

Makes sense, thanks.

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> 
> Niranjana
> 
> > Thanks,
> > Stuart
> > 
> > > 0);
> > > +       else
> > > +               vm = xe_vm_create(fd,
> > > DRM_XE_VM_CREATE_FLAG_LR_MODE,
> > > 0);
> > > +
> > >         bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
> > >  
> > >         if (flags & USERPTR) {
> > > @@ -583,6 +589,12 @@ test_legacy_mode(int fd, struct
> > > drm_xe_engine_class_instance *eci, int num_place
> > >   * @preempt-mode-priority:                     preempt-mode
> > > priority
> > >   * @preempt-mode-close-fd:                     preempt-mode
> > > close fd
> > > without destroying exec queues
> > >   * @preempt-mode-dyn-priority:                 preempt-mode
> > > dynamic
> > > priority
> > > + * @preempt-mode-fault-basic:                  preempt-mode-
> > > fault-
> > > mode basic
> > > + * @preempt-mode-fault-userptr:                        preempt-
> > > mode-
> > > fault-mode userptr
> > > + * @preempt-mode-fault-userptr-invalidate:     preempt-mode-
> > > fault-
> > > mode userptr invalidate
> > > + * @preempt-mode-fault-priority:               preempt-mode-
> > > fault-
> > > mode priority
> > > + * @preempt-mode-fault-close-fd:               preempt-mode-
> > > fault-
> > > mode close fd
> > > + * @preempt-mode-fault-dyn-priority:           preempt-mode-
> > > fault-
> > > mode dynamic priority
> > >   */
> > >  static void
> > >  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> > > num_placement,
> > > @@ -637,6 +649,13 @@ igt_main
> > >                 { "preempt-mode-priority", PREEMPT_MODE |
> > > PRIORITY },
> > >                 { "preempt-mode-close-fd", PREEMPT_MODE |
> > > CLOSE_FD },
> > >                 { "preempt-mode-dyn-priority", PREEMPT_MODE |
> > > DYN_PRIORITY },
> > > +               { "preempt-mode-fault-basic", PREEMPT_MODE |
> > > FAULT_MODE },
> > > +               { "preempt-mode-fault-userptr", PREEMPT_MODE |
> > > FAULT_MODE | USERPTR },
> > > +               { "preempt-mode-fault-userptr-invalidate",
> > > PREEMPT_MODE | FAULT_MODE |
> > > +                       USERPTR | INVALIDATE },
> > > +               { "preempt-mode-fault-priority", PREEMPT_MODE |
> > > FAULT_MODE | PRIORITY },
> > > +               { "preempt-mode-fault-close-fd", PREEMPT_MODE |
> > > FAULT_MODE | CLOSE_FD },
> > > +               { "preempt-mode-fault-dyn-priority", PREEMPT_MODE
> > > |
> > > FAULT_MODE | DYN_PRIORITY },
> > >                 { NULL },
> > >         };
> > >         int fd, gt, class;
> > 

[PATCH v2 13/19] tests/intel/xe_exec_multi_queue: Add multi queues with SMEM

[Niranjana Vishwanathapura]

From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>

Extend multi queue tests with SMEM.

Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 40 +++++++++++++++++++++++++++----
 1 file changed, 36 insertions(+), 4 deletions(-)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index da8117d57..df65ccafb 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -32,6 +32,7 @@
 #define DYN_PRIORITY		(0x1 << 4)
 #define INVALIDATE		(0x1 << 5)
 #define FAULT_MODE		(0x1 << 6)
+#define SMEM			(0x1 << 7)
 
 #define MAX_INSTANCE 9
 
@@ -266,8 +267,11 @@ test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_plac
 		}
 		memset(data, 0, bo_size);
 	} else {
-		bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
-				  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+		if (flags & SMEM)
+			bo = xe_bo_create(fd, vm, bo_size, system_memory(fd), 0);
+		else
+			bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
+					  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 
@@ -428,8 +432,11 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
 		}
 		memset(data, 0, bo_size);
 	} else {
-		bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
-				  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+		if (flags & SMEM)
+			bo = xe_bo_create(fd, vm, bo_size, system_memory(fd), 0);
+		else
+			bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
+					  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 
@@ -578,23 +585,36 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_place
  * arg[1]:
  *
  * @basic:					basic
+ * @basic-smem:					basic smem
  * @userptr:					userptr
  * @userptr-invalidate:				userptr invalidate
  * @priority:					priority
  * @close-fd:					close fd without destroying exec queues
  * @dyn-priority:				dynamic priority
  * @preempt-mode-basic:				preempt-mode basic
+ * @priority-smem:				priority smem
+ * @close-fd-smem:				close fd without destroying exec queues smem
+ * @dyn-priority-smem:				dynamic priority smem
+ * @preempt-mode-basic-smem:			preempt-mode basic smem
  * @preempt-mode-userptr:			preempt-mode userptr
  * @preempt-mode-userptr-invalidate:		preempt-mode userptr invalidate
  * @preempt-mode-priority:			preempt-mode priority
  * @preempt-mode-close-fd:			preempt-mode close fd without destroying exec queues
  * @preempt-mode-dyn-priority:			preempt-mode dynamic priority
  * @preempt-mode-fault-basic:			preempt-mode-fault-mode basic
+ * @preempt-mode-priority-smem:			preempt-mode priority smem
+ * @preempt-mode-close-fd-smem:			preempt-mode close fd without destroying exec queues smem
+ * @preempt-mode-dyn-priority-smem:		preempt-mode dynamic priority smem
+ * @preempt-mode-fault-basic-smem:		preempt-mode-fault-mode basic smem
  * @preempt-mode-fault-userptr:			preempt-mode-fault-mode userptr
  * @preempt-mode-fault-userptr-invalidate:	preempt-mode-fault-mode userptr invalidate
  * @preempt-mode-fault-priority:		preempt-mode-fault-mode priority
  * @preempt-mode-fault-close-fd:		preempt-mode-fault-mode close fd
  * @preempt-mode-fault-dyn-priority:		preempt-mode-fault-mode dynamic priority
+ * @preempt-mode-fault-priority-smem:		preempt-mode-fault-mode priority smem
+ * @preempt-mode-fault-close-fd-smem:		preempt-mode-fault-mode close fd smem
+ * @preempt-mode-fault-dyn-priority-smem:	preempt-mode-fault-mode dynamic priority smem
+ *
  */
 static void
 test_exec(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
@@ -638,24 +658,36 @@ igt_main
 		unsigned int flags;
 	} sections[] = {
 		{ "basic", 0 },
+		{ "basic-smem", SMEM },
 		{ "userptr", USERPTR },
 		{ "userptr-invalidate", USERPTR | INVALIDATE },
 		{ "priority", PRIORITY },
+		{ "priority-smem", PRIORITY | SMEM },
 		{ "close-fd", CLOSE_FD },
+		{ "close-fd-smem", CLOSE_FD | SMEM },
 		{ "dyn-priority", DYN_PRIORITY },
+		{ "dyn-priority-smem", DYN_PRIORITY | SMEM },
 		{ "preempt-mode-basic", PREEMPT_MODE },
+		{ "preempt-mode-basic-smem", PREEMPT_MODE | SMEM },
 		{ "preempt-mode-userptr", PREEMPT_MODE | USERPTR },
 		{ "preempt-mode-userptr-invalidate", PREEMPT_MODE | USERPTR | INVALIDATE },
 		{ "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
+		{ "preempt-mode-priority-smem", PREEMPT_MODE | PRIORITY | SMEM },
 		{ "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
+		{ "preempt-mode-close-fd-smem", PREEMPT_MODE | CLOSE_FD | SMEM },
 		{ "preempt-mode-dyn-priority", PREEMPT_MODE | DYN_PRIORITY },
+		{ "preempt-mode-dyn-priority-smem", PREEMPT_MODE | DYN_PRIORITY | SMEM },
 		{ "preempt-mode-fault-basic", PREEMPT_MODE | FAULT_MODE },
+		{ "preempt-mode-fault-basic-smem", PREEMPT_MODE | FAULT_MODE | SMEM },
 		{ "preempt-mode-fault-userptr", PREEMPT_MODE | FAULT_MODE | USERPTR },
 		{ "preempt-mode-fault-userptr-invalidate", PREEMPT_MODE | FAULT_MODE |
 			USERPTR | INVALIDATE },
 		{ "preempt-mode-fault-priority", PREEMPT_MODE | FAULT_MODE | PRIORITY },
+		{ "preempt-mode-fault-priority-smem", PREEMPT_MODE | FAULT_MODE | PRIORITY | SMEM },
 		{ "preempt-mode-fault-close-fd", PREEMPT_MODE | FAULT_MODE | CLOSE_FD },
+		{ "preempt-mode-fault-close-fd-smem", PREEMPT_MODE | FAULT_MODE | CLOSE_FD | SMEM },
 		{ "preempt-mode-fault-dyn-priority", PREEMPT_MODE | FAULT_MODE | DYN_PRIORITY },
+		{ "preempt-mode-fault-dyn-priority-smem", PREEMPT_MODE | FAULT_MODE | DYN_PRIORITY | SMEM },
 		{ NULL },
 	};
 	int fd, gt, class;
-- 
2.43.0

RE: [PATCH v2 13/19] tests/intel/xe_exec_multi_queue: Add multi queues with SMEM

[Goyal, Nakshtra]

> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of
> Niranjana Vishwanathapura
> Sent: 21 November 2025 09:27
> To: igt-dev@lists.freedesktop.org
> Cc: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>; kamil.konieczny@linux.intel.com
> Subject: [PATCH v2 13/19] tests/intel/xe_exec_multi_queue: Add multi queues
> with SMEM
> 
> From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> 
> Extend multi queue tests with SMEM.
> 
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
LGTM
Reviewed-by: Nakshtra Goyal <nakshtra.goyal@intel.com>

> ---
>  tests/intel/xe_exec_multi_queue.c | 40 +++++++++++++++++++++++++++----
>  1 file changed, 36 insertions(+), 4 deletions(-)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index da8117d57..df65ccafb 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -32,6 +32,7 @@
>  #define DYN_PRIORITY		(0x1 << 4)
>  #define INVALIDATE		(0x1 << 5)
>  #define FAULT_MODE		(0x1 << 6)
> +#define SMEM			(0x1 << 7)
> 
>  #define MAX_INSTANCE 9
> 
> @@ -266,8 +267,11 @@ test_preempt_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_plac
>  		}
>  		memset(data, 0, bo_size);
>  	} else {
> -		bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd,
> eci[0].gt_id),
> -
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +		if (flags & SMEM)
> +			bo = xe_bo_create(fd, vm, bo_size,
> system_memory(fd), 0);
> +		else
> +			bo = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> +
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>  		data = xe_bo_map(fd, bo, bo_size);
>  	}
> 
> @@ -428,8 +432,11 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>  		}
>  		memset(data, 0, bo_size);
>  	} else {
> -		bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd,
> eci[0].gt_id),
> -
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +		if (flags & SMEM)
> +			bo = xe_bo_create(fd, vm, bo_size,
> system_memory(fd), 0);
> +		else
> +			bo = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> +
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>  		data = xe_bo_map(fd, bo, bo_size);
>  	}
> 
> @@ -578,23 +585,36 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>   * arg[1]:
>   *
>   * @basic:					basic
> + * @basic-smem:					basic smem
>   * @userptr:					userptr
>   * @userptr-invalidate:				userptr invalidate
>   * @priority:					priority
>   * @close-fd:					close fd without destroying
> exec queues
>   * @dyn-priority:				dynamic priority
>   * @preempt-mode-basic:				preempt-mode basic
> + * @priority-smem:				priority smem
> + * @close-fd-smem:				close fd without destroying
> exec queues smem
> + * @dyn-priority-smem:				dynamic priority
> smem
> + * @preempt-mode-basic-smem:			preempt-mode basic
> smem
>   * @preempt-mode-userptr:			preempt-mode userptr
>   * @preempt-mode-userptr-invalidate:		preempt-mode userptr
> invalidate
>   * @preempt-mode-priority:			preempt-mode priority
>   * @preempt-mode-close-fd:			preempt-mode close fd
> without destroying exec queues
>   * @preempt-mode-dyn-priority:			preempt-mode
> dynamic priority
>   * @preempt-mode-fault-basic:			preempt-mode-fault-
> mode basic
> + * @preempt-mode-priority-smem:			preempt-mode
> priority smem
> + * @preempt-mode-close-fd-smem:			preempt-mode close
> fd without destroying exec queues smem
> + * @preempt-mode-dyn-priority-smem:		preempt-mode
> dynamic priority smem
> + * @preempt-mode-fault-basic-smem:		preempt-mode-fault-
> mode basic smem
>   * @preempt-mode-fault-userptr:			preempt-mode-fault-
> mode userptr
>   * @preempt-mode-fault-userptr-invalidate:	preempt-mode-fault-mode
> userptr invalidate
>   * @preempt-mode-fault-priority:		preempt-mode-fault-mode
> priority
>   * @preempt-mode-fault-close-fd:		preempt-mode-fault-mode
> close fd
>   * @preempt-mode-fault-dyn-priority:		preempt-mode-fault-mode
> dynamic priority
> + * @preempt-mode-fault-priority-smem:		preempt-mode-fault-
> mode priority smem
> + * @preempt-mode-fault-close-fd-smem:		preempt-mode-fault-
> mode close fd smem
> + * @preempt-mode-fault-dyn-priority-smem:	preempt-mode-fault-mode
> dynamic priority smem
> + *
>   */
>  static void
>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement, @@ -638,24 +658,36 @@ igt_main
>  		unsigned int flags;
>  	} sections[] = {
>  		{ "basic", 0 },
> +		{ "basic-smem", SMEM },
>  		{ "userptr", USERPTR },
>  		{ "userptr-invalidate", USERPTR | INVALIDATE },
>  		{ "priority", PRIORITY },
> +		{ "priority-smem", PRIORITY | SMEM },
>  		{ "close-fd", CLOSE_FD },
> +		{ "close-fd-smem", CLOSE_FD | SMEM },
>  		{ "dyn-priority", DYN_PRIORITY },
> +		{ "dyn-priority-smem", DYN_PRIORITY | SMEM },
>  		{ "preempt-mode-basic", PREEMPT_MODE },
> +		{ "preempt-mode-basic-smem", PREEMPT_MODE | SMEM },
>  		{ "preempt-mode-userptr", PREEMPT_MODE | USERPTR },
>  		{ "preempt-mode-userptr-invalidate", PREEMPT_MODE |
> USERPTR | INVALIDATE },
>  		{ "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
> +		{ "preempt-mode-priority-smem", PREEMPT_MODE |
> PRIORITY | SMEM },
>  		{ "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
> +		{ "preempt-mode-close-fd-smem", PREEMPT_MODE |
> CLOSE_FD | SMEM },
>  		{ "preempt-mode-dyn-priority", PREEMPT_MODE |
> DYN_PRIORITY },
> +		{ "preempt-mode-dyn-priority-smem", PREEMPT_MODE |
> DYN_PRIORITY |
> +SMEM },
>  		{ "preempt-mode-fault-basic", PREEMPT_MODE |
> FAULT_MODE },
> +		{ "preempt-mode-fault-basic-smem", PREEMPT_MODE |
> FAULT_MODE | SMEM
> +},
>  		{ "preempt-mode-fault-userptr", PREEMPT_MODE |
> FAULT_MODE | USERPTR },
>  		{ "preempt-mode-fault-userptr-invalidate", PREEMPT_MODE
> | FAULT_MODE |
>  			USERPTR | INVALIDATE },
>  		{ "preempt-mode-fault-priority", PREEMPT_MODE |
> FAULT_MODE | PRIORITY },
> +		{ "preempt-mode-fault-priority-smem", PREEMPT_MODE |
> FAULT_MODE |
> +PRIORITY | SMEM },
>  		{ "preempt-mode-fault-close-fd", PREEMPT_MODE |
> FAULT_MODE | CLOSE_FD },
> +		{ "preempt-mode-fault-close-fd-smem", PREEMPT_MODE |
> FAULT_MODE |
> +CLOSE_FD | SMEM },
>  		{ "preempt-mode-fault-dyn-priority", PREEMPT_MODE |
> FAULT_MODE | DYN_PRIORITY },
> +		{ "preempt-mode-fault-dyn-priority-smem", PREEMPT_MODE
> | FAULT_MODE |
> +DYN_PRIORITY | SMEM },
>  		{ NULL },
>  	};
>  	int fd, gt, class;
> --
> 2.43.0

Re: [PATCH v2 13/19] tests/intel/xe_exec_multi_queue: Add multi queues with SMEM

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> 
> Extend multi queue tests with SMEM.

This one is definitely interesting.

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> 
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> ---
>  tests/intel/xe_exec_multi_queue.c | 40 +++++++++++++++++++++++++++--
> --
>  1 file changed, 36 insertions(+), 4 deletions(-)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index da8117d57..df65ccafb 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -32,6 +32,7 @@
>  #define DYN_PRIORITY           (0x1 << 4)
>  #define INVALIDATE             (0x1 << 5)
>  #define FAULT_MODE             (0x1 << 6)
> +#define SMEM                   (0x1 << 7)
>  
>  #define MAX_INSTANCE 9
>  
> @@ -266,8 +267,11 @@ test_preempt_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_plac
>                 }
>                 memset(data, 0, bo_size);
>         } else {
> -               bo = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> -                                
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +               if (flags & SMEM)
> +                       bo = xe_bo_create(fd, vm, bo_size,
> system_memory(fd), 0);
> +               else
> +                       bo = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> +                                        
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>                 data = xe_bo_map(fd, bo, bo_size);
>         }
>  
> @@ -428,8 +432,11 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>                 }
>                 memset(data, 0, bo_size);
>         } else {
> -               bo = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> -                                
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +               if (flags & SMEM)
> +                       bo = xe_bo_create(fd, vm, bo_size,
> system_memory(fd), 0);
> +               else
> +                       bo = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> +                                        
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>                 data = xe_bo_map(fd, bo, bo_size);
>         }
>  
> @@ -578,23 +585,36 @@ test_legacy_mode(int fd, struct
> drm_xe_engine_class_instance *eci, int num_place
>   * arg[1]:
>   *
>   * @basic:                                     basic
> + * @basic-smem:                                        basic smem
>   * @userptr:                                   userptr
>   * @userptr-invalidate:                                userptr
> invalidate
>   * @priority:                                  priority
>   * @close-fd:                                  close fd without
> destroying exec queues
>   * @dyn-priority:                              dynamic priority
>   * @preempt-mode-basic:                                preempt-mode
> basic
> + * @priority-smem:                             priority smem
> + * @close-fd-smem:                             close fd without
> destroying exec queues smem
> + * @dyn-priority-smem:                         dynamic priority smem
> + * @preempt-mode-basic-smem:                   preempt-mode basic
> smem
>   * @preempt-mode-userptr:                      preempt-mode userptr
>   * @preempt-mode-userptr-invalidate:           preempt-mode userptr
> invalidate
>   * @preempt-mode-priority:                     preempt-mode priority
>   * @preempt-mode-close-fd:                     preempt-mode close fd
> without destroying exec queues
>   * @preempt-mode-dyn-priority:                 preempt-mode dynamic
> priority
>   * @preempt-mode-fault-basic:                  preempt-mode-fault-
> mode basic
> + * @preempt-mode-priority-smem:                        preempt-mode
> priority smem
> + * @preempt-mode-close-fd-smem:                        preempt-mode
> close fd without destroying exec queues smem
> + * @preempt-mode-dyn-priority-smem:            preempt-mode dynamic
> priority smem
> + * @preempt-mode-fault-basic-smem:             preempt-mode-fault-
> mode basic smem
>   * @preempt-mode-fault-userptr:                        preempt-mode-
> fault-mode userptr
>   * @preempt-mode-fault-userptr-invalidate:     preempt-mode-fault-
> mode userptr invalidate
>   * @preempt-mode-fault-priority:               preempt-mode-fault-
> mode priority
>   * @preempt-mode-fault-close-fd:               preempt-mode-fault-
> mode close fd
>   * @preempt-mode-fault-dyn-priority:           preempt-mode-fault-
> mode dynamic priority
> + * @preempt-mode-fault-priority-smem:          preempt-mode-fault-
> mode priority smem
> + * @preempt-mode-fault-close-fd-smem:          preempt-mode-fault-
> mode close fd smem
> + * @preempt-mode-fault-dyn-priority-smem:      preempt-mode-fault-
> mode dynamic priority smem
> + *
>   */
>  static void
>  test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement,
> @@ -638,24 +658,36 @@ igt_main
>                 unsigned int flags;
>         } sections[] = {
>                 { "basic", 0 },
> +               { "basic-smem", SMEM },
>                 { "userptr", USERPTR },
>                 { "userptr-invalidate", USERPTR | INVALIDATE },
>                 { "priority", PRIORITY },
> +               { "priority-smem", PRIORITY | SMEM },
>                 { "close-fd", CLOSE_FD },
> +               { "close-fd-smem", CLOSE_FD | SMEM },
>                 { "dyn-priority", DYN_PRIORITY },
> +               { "dyn-priority-smem", DYN_PRIORITY | SMEM },
>                 { "preempt-mode-basic", PREEMPT_MODE },
> +               { "preempt-mode-basic-smem", PREEMPT_MODE | SMEM },
>                 { "preempt-mode-userptr", PREEMPT_MODE | USERPTR },
>                 { "preempt-mode-userptr-invalidate", PREEMPT_MODE |
> USERPTR | INVALIDATE },
>                 { "preempt-mode-priority", PREEMPT_MODE | PRIORITY },
> +               { "preempt-mode-priority-smem", PREEMPT_MODE |
> PRIORITY | SMEM },
>                 { "preempt-mode-close-fd", PREEMPT_MODE | CLOSE_FD },
> +               { "preempt-mode-close-fd-smem", PREEMPT_MODE |
> CLOSE_FD | SMEM },
>                 { "preempt-mode-dyn-priority", PREEMPT_MODE |
> DYN_PRIORITY },
> +               { "preempt-mode-dyn-priority-smem", PREEMPT_MODE |
> DYN_PRIORITY | SMEM },
>                 { "preempt-mode-fault-basic", PREEMPT_MODE |
> FAULT_MODE },
> +               { "preempt-mode-fault-basic-smem", PREEMPT_MODE |
> FAULT_MODE | SMEM },
>                 { "preempt-mode-fault-userptr", PREEMPT_MODE |
> FAULT_MODE | USERPTR },
>                 { "preempt-mode-fault-userptr-invalidate",
> PREEMPT_MODE | FAULT_MODE |
>                         USERPTR | INVALIDATE },
>                 { "preempt-mode-fault-priority", PREEMPT_MODE |
> FAULT_MODE | PRIORITY },
> +               { "preempt-mode-fault-priority-smem", PREEMPT_MODE |
> FAULT_MODE | PRIORITY | SMEM },
>                 { "preempt-mode-fault-close-fd", PREEMPT_MODE |
> FAULT_MODE | CLOSE_FD },
> +               { "preempt-mode-fault-close-fd-smem", PREEMPT_MODE |
> FAULT_MODE | CLOSE_FD | SMEM },
>                 { "preempt-mode-fault-dyn-priority", PREEMPT_MODE |
> FAULT_MODE | DYN_PRIORITY },
> +               { "preempt-mode-fault-dyn-priority-smem",
> PREEMPT_MODE | FAULT_MODE | DYN_PRIORITY | SMEM },
>                 { NULL },
>         };
>         int fd, gt, class;

[PATCH v2 14/19] lib/xe/xe_spin: Add switch point for preemptible spinner

[Niranjana Vishwanathapura]

When 'preempt' option is specified, insert a MI_SEMAPHORE_WAIT
command in the spinner batch buffer. This provides the switch
point for preemption to happen in multi queue mode.
Allow user to control preempt wait condition.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 include/intel_gpu_commands.h |  1 +
 lib/xe/xe_spin.c             | 41 ++++++++++++++++++++++++++++++++++++
 lib/xe/xe_spin.h             |  3 +++
 3 files changed, 45 insertions(+)

diff --git a/include/intel_gpu_commands.h b/include/intel_gpu_commands.h
index cd281ba89..5158bb0ea 100644
--- a/include/intel_gpu_commands.h
+++ b/include/intel_gpu_commands.h
@@ -123,6 +123,7 @@
 #define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
 #define MI_SEMAPHORE_WAIT_TOKEN	MI_INSTR(0x1c, 3) /* GEN12+ */
 #define   MI_SEMAPHORE_POLL		(1 << 15)
+#define   MI_SEMAPHORE_QUEUE_SWITCH_MODE	(1 << 11)
 #define   MI_SEMAPHORE_SAD_GT_SDD	(0 << 12)
 #define   MI_SEMAPHORE_SAD_GTE_SDD	(1 << 12)
 #define   MI_SEMAPHORE_SAD_LT_SDD	(2 << 12)
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 72b13ef42..174c5f7ec 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -57,6 +57,7 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
 
 	spin->start = 0;
 	spin->end = 0xffffffff;
+	spin->wait_cond = 0;
 	spin->ticks_delta = 0;
 
 	if (opts->ctx_ticks) {
@@ -167,6 +168,24 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
 				   opts->mem_copy->dst->mocs_index;
 	}
 
+	/*
+	 * Insert a MI_SEMAPHORE_WAIT_CMD instruction with condition controlled
+	 * by the user. It also acts as a queue switch point in multi queue mode.
+	 */
+	if (opts->preempt) {
+		uint64_t wait_addr = opts->addr + offsetof(struct xe_spin, wait_cond);
+
+		spin->batch[b++] = MI_SEMAPHORE_WAIT_CMD |
+				MI_SEMAPHORE_POLL |
+				MI_SEMAPHORE_QUEUE_SWITCH_MODE |
+				MI_SEMAPHORE_SAD_EQ_SDD |
+				3;
+		spin->batch[b++] = 0;
+		spin->batch[b++] = wait_addr;
+		spin->batch[b++] = wait_addr >> 32;
+		spin->batch[b++] = 0;
+	}
+
 	spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 2;
 	spin->batch[b++] = 0;
 	spin->batch[b++] = end_addr;
@@ -207,6 +226,28 @@ void xe_spin_end(struct xe_spin *spin)
 	WRITE_ONCE(spin->end, 0);
 }
 
+/**
+ * xe_spin_preempt_wait:
+ * @spin: pointer to spinner mapped bo
+ *
+ * Make the spinner wait on the preemption semaphore.
+ */
+void xe_spin_preempt_wait(struct xe_spin *spin)
+{
+	spin->wait_cond = 1;
+}
+
+/**
+ * xe_spin_preempt_nowait:
+ * @spin: pointer to spinner mapped bo
+ *
+ * Make the spinner do not wait on the preemption semaphore.
+ */
+void xe_spin_preempt_nowait(struct xe_spin *spin)
+{
+	spin->wait_cond = 0;
+}
+
 /**
  * xe_spin_create:
  * @opt: controlling options such as allocator handle, exec_queue, vm etc
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index c2199d0aa..eaf2a409e 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -64,6 +64,7 @@ struct xe_spin {
 	uint64_t pad;
 	uint32_t start;
 	uint32_t end;
+	uint32_t wait_cond;
 	uint32_t ticks_delta;
 	uint64_t exec_sync;
 	uint32_t timestamp;
@@ -76,6 +77,8 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts);
 bool xe_spin_started(struct xe_spin *spin);
 void xe_spin_wait_started(struct xe_spin *spin);
 void xe_spin_end(struct xe_spin *spin);
+void xe_spin_preempt_wait(struct xe_spin *spin);
+void xe_spin_preempt_nowait(struct xe_spin *spin);
 
 /*
  * xe_cork: higher level API that simplifies exec'ing an xe_spin by taking care
-- 
2.43.0

Re: [PATCH v2 14/19] lib/xe/xe_spin: Add switch point for preemptible spinner

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> When 'preempt' option is specified, insert a MI_SEMAPHORE_WAIT
> command in the spinner batch buffer. This provides the switch
> point for preemption to happen in multi queue mode.
> Allow user to control preempt wait condition.
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> ---
>  include/intel_gpu_commands.h |  1 +
>  lib/xe/xe_spin.c             | 41
> ++++++++++++++++++++++++++++++++++++
>  lib/xe/xe_spin.h             |  3 +++
>  3 files changed, 45 insertions(+)
> 
> diff --git a/include/intel_gpu_commands.h
> b/include/intel_gpu_commands.h
> index cd281ba89..5158bb0ea 100644
> --- a/include/intel_gpu_commands.h
> +++ b/include/intel_gpu_commands.h
> @@ -123,6 +123,7 @@
>  #define MI_SEMAPHORE_WAIT      MI_INSTR(0x1c, 2) /* GEN8+ */
>  #define MI_SEMAPHORE_WAIT_TOKEN        MI_INSTR(0x1c, 3) /* GEN12+
> */
>  #define   MI_SEMAPHORE_POLL            (1 << 15)
> +#define   MI_SEMAPHORE_QUEUE_SWITCH_MODE       (1 << 11)
>  #define   MI_SEMAPHORE_SAD_GT_SDD      (0 << 12)
>  #define   MI_SEMAPHORE_SAD_GTE_SDD     (1 << 12)
>  #define   MI_SEMAPHORE_SAD_LT_SDD      (2 << 12)
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 72b13ef42..174c5f7ec 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -57,6 +57,7 @@ void xe_spin_init(struct xe_spin *spin, struct
> xe_spin_opts *opts)
>  
>         spin->start = 0;
>         spin->end = 0xffffffff;
> +       spin->wait_cond = 0;
>         spin->ticks_delta = 0;
>  
>         if (opts->ctx_ticks) {
> @@ -167,6 +168,24 @@ void xe_spin_init(struct xe_spin *spin, struct
> xe_spin_opts *opts)
>                                    opts->mem_copy->dst->mocs_index;
>         }
>  
> +       /*
> +        * Insert a MI_SEMAPHORE_WAIT_CMD instruction with condition
> controlled
> +        * by the user. It also acts as a queue switch point in multi
> queue mode.
> +        */
> +       if (opts->preempt) {
> +               uint64_t wait_addr = opts->addr + offsetof(struct
> xe_spin, wait_cond);
> +
> +               spin->batch[b++] = MI_SEMAPHORE_WAIT_CMD |
> +                               MI_SEMAPHORE_POLL |
> +                               MI_SEMAPHORE_QUEUE_SWITCH_MODE |
> +                               MI_SEMAPHORE_SAD_EQ_SDD |
> +                               3;
> +               spin->batch[b++] = 0;

Should this be set to spin->wait_cond in case we ever want to change
the default value here?

Otherwise generally this is a great addition to the spinner toolkit:
Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> +               spin->batch[b++] = wait_addr;
> +               spin->batch[b++] = wait_addr >> 32;
> +               spin->batch[b++] = 0;
> +       }
> +
>         spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE |
> 2;
>         spin->batch[b++] = 0;
>         spin->batch[b++] = end_addr;
> @@ -207,6 +226,28 @@ void xe_spin_end(struct xe_spin *spin)
>         WRITE_ONCE(spin->end, 0);
>  }
>  
> +/**
> + * xe_spin_preempt_wait:
> + * @spin: pointer to spinner mapped bo
> + *
> + * Make the spinner wait on the preemption semaphore.
> + */
> +void xe_spin_preempt_wait(struct xe_spin *spin)
> +{
> +       spin->wait_cond = 1;
> +}
> +
> +/**
> + * xe_spin_preempt_nowait:
> + * @spin: pointer to spinner mapped bo
> + *
> + * Make the spinner do not wait on the preemption semaphore.
> + */
> +void xe_spin_preempt_nowait(struct xe_spin *spin)
> +{
> +       spin->wait_cond = 0;
> +}
> +
>  /**
>   * xe_spin_create:
>   * @opt: controlling options such as allocator handle, exec_queue,
> vm etc
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index c2199d0aa..eaf2a409e 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -64,6 +64,7 @@ struct xe_spin {
>         uint64_t pad;
>         uint32_t start;
>         uint32_t end;
> +       uint32_t wait_cond;
>         uint32_t ticks_delta;
>         uint64_t exec_sync;
>         uint32_t timestamp;
> @@ -76,6 +77,8 @@ void xe_spin_init(struct xe_spin *spin, struct
> xe_spin_opts *opts);
>  bool xe_spin_started(struct xe_spin *spin);
>  void xe_spin_wait_started(struct xe_spin *spin);
>  void xe_spin_end(struct xe_spin *spin);
> +void xe_spin_preempt_wait(struct xe_spin *spin);
> +void xe_spin_preempt_nowait(struct xe_spin *spin);
>  
>  /*
>   * xe_cork: higher level API that simplifies exec'ing an xe_spin by
> taking care

Re: [PATCH v2 14/19] lib/xe/xe_spin: Add switch point for preemptible spinner

[Niranjana Vishwanathapura]

On Thu, Dec 04, 2025 at 01:03:25PM -0800, Summers, Stuart wrote:
>On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
>> When 'preempt' option is specified, insert a MI_SEMAPHORE_WAIT
>> command in the spinner batch buffer. This provides the switch
>> point for preemption to happen in multi queue mode.
>> Allow user to control preempt wait condition.
>>
>> Signed-off-by: Niranjana Vishwanathapura
>> <niranjana.vishwanathapura@intel.com>
>> ---
>>  include/intel_gpu_commands.h |  1 +
>>  lib/xe/xe_spin.c             | 41
>> ++++++++++++++++++++++++++++++++++++
>>  lib/xe/xe_spin.h             |  3 +++
>>  3 files changed, 45 insertions(+)
>>
>> diff --git a/include/intel_gpu_commands.h
>> b/include/intel_gpu_commands.h
>> index cd281ba89..5158bb0ea 100644
>> --- a/include/intel_gpu_commands.h
>> +++ b/include/intel_gpu_commands.h
>> @@ -123,6 +123,7 @@
>>  #define MI_SEMAPHORE_WAIT      MI_INSTR(0x1c, 2) /* GEN8+ */
>>  #define MI_SEMAPHORE_WAIT_TOKEN        MI_INSTR(0x1c, 3) /* GEN12+
>> */
>>  #define   MI_SEMAPHORE_POLL            (1 << 15)
>> +#define   MI_SEMAPHORE_QUEUE_SWITCH_MODE       (1 << 11)
>>  #define   MI_SEMAPHORE_SAD_GT_SDD      (0 << 12)
>>  #define   MI_SEMAPHORE_SAD_GTE_SDD     (1 << 12)
>>  #define   MI_SEMAPHORE_SAD_LT_SDD      (2 << 12)
>> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
>> index 72b13ef42..174c5f7ec 100644
>> --- a/lib/xe/xe_spin.c
>> +++ b/lib/xe/xe_spin.c
>> @@ -57,6 +57,7 @@ void xe_spin_init(struct xe_spin *spin, struct
>> xe_spin_opts *opts)
>>  
>>         spin->start = 0;
>>         spin->end = 0xffffffff;
>> +       spin->wait_cond = 0;
>>         spin->ticks_delta = 0;
>>  
>>         if (opts->ctx_ticks) {
>> @@ -167,6 +168,24 @@ void xe_spin_init(struct xe_spin *spin, struct
>> xe_spin_opts *opts)
>>                                    opts->mem_copy->dst->mocs_index;
>>         }
>>  
>> +       /*
>> +        * Insert a MI_SEMAPHORE_WAIT_CMD instruction with condition
>> controlled
>> +        * by the user. It also acts as a queue switch point in multi
>> queue mode.
>> +        */
>> +       if (opts->preempt) {
>> +               uint64_t wait_addr = opts->addr + offsetof(struct
>> xe_spin, wait_cond);
>> +
>> +               spin->batch[b++] = MI_SEMAPHORE_WAIT_CMD |
>> +                               MI_SEMAPHORE_POLL |
>> +                               MI_SEMAPHORE_QUEUE_SWITCH_MODE |
>> +                               MI_SEMAPHORE_SAD_EQ_SDD |
>> +                               3;
>> +               spin->batch[b++] = 0;
>
>Should this be set to spin->wait_cond in case we ever want to change
>the default value here?
>

wait_cond is already part of wait_addr. So, user can control the
wait using xe_spin_preempt_wait()/nowait() functions below.

Niranjana

>Otherwise generally this is a great addition to the spinner toolkit:
>Reviewed-by: Stuart Summers <stuart.summers@intel.com>
>
>> +               spin->batch[b++] = wait_addr;
>> +               spin->batch[b++] = wait_addr >> 32;
>> +               spin->batch[b++] = 0;
>> +       }
>> +
>>         spin->batch[b++] = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE |
>> 2;
>>         spin->batch[b++] = 0;
>>         spin->batch[b++] = end_addr;
>> @@ -207,6 +226,28 @@ void xe_spin_end(struct xe_spin *spin)
>>         WRITE_ONCE(spin->end, 0);
>>  }
>>  
>> +/**
>> + * xe_spin_preempt_wait:
>> + * @spin: pointer to spinner mapped bo
>> + *
>> + * Make the spinner wait on the preemption semaphore.
>> + */
>> +void xe_spin_preempt_wait(struct xe_spin *spin)
>> +{
>> +       spin->wait_cond = 1;
>> +}
>> +
>> +/**
>> + * xe_spin_preempt_nowait:
>> + * @spin: pointer to spinner mapped bo
>> + *
>> + * Make the spinner do not wait on the preemption semaphore.
>> + */
>> +void xe_spin_preempt_nowait(struct xe_spin *spin)
>> +{
>> +       spin->wait_cond = 0;
>> +}
>> +
>>  /**
>>   * xe_spin_create:
>>   * @opt: controlling options such as allocator handle, exec_queue,
>> vm etc
>> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
>> index c2199d0aa..eaf2a409e 100644
>> --- a/lib/xe/xe_spin.h
>> +++ b/lib/xe/xe_spin.h
>> @@ -64,6 +64,7 @@ struct xe_spin {
>>         uint64_t pad;
>>         uint32_t start;
>>         uint32_t end;
>> +       uint32_t wait_cond;
>>         uint32_t ticks_delta;
>>         uint64_t exec_sync;
>>         uint32_t timestamp;
>> @@ -76,6 +77,8 @@ void xe_spin_init(struct xe_spin *spin, struct
>> xe_spin_opts *opts);
>>  bool xe_spin_started(struct xe_spin *spin);
>>  void xe_spin_wait_started(struct xe_spin *spin);
>>  void xe_spin_end(struct xe_spin *spin);
>> +void xe_spin_preempt_wait(struct xe_spin *spin);
>> +void xe_spin_preempt_nowait(struct xe_spin *spin);
>>  
>>  /*
>>   * xe_cork: higher level API that simplifies exec'ing an xe_spin by
>> taking care
>

Re: [PATCH v2 14/19] lib/xe/xe_spin: Add switch point for preemptible spinner

[Summers, Stuart]

On Thu, 2025-12-04 at 13:42 -0800, Niranjana Vishwanathapura wrote:
> On Thu, Dec 04, 2025 at 01:03:25PM -0800, Summers, Stuart wrote:
> > On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> > > When 'preempt' option is specified, insert a MI_SEMAPHORE_WAIT
> > > command in the spinner batch buffer. This provides the switch
> > > point for preemption to happen in multi queue mode.
> > > Allow user to control preempt wait condition.
> > > 
> > > Signed-off-by: Niranjana Vishwanathapura
> > > <niranjana.vishwanathapura@intel.com>
> > > ---
> > >  include/intel_gpu_commands.h |  1 +
> > >  lib/xe/xe_spin.c             | 41
> > > ++++++++++++++++++++++++++++++++++++
> > >  lib/xe/xe_spin.h             |  3 +++
> > >  3 files changed, 45 insertions(+)
> > > 
> > > diff --git a/include/intel_gpu_commands.h
> > > b/include/intel_gpu_commands.h
> > > index cd281ba89..5158bb0ea 100644
> > > --- a/include/intel_gpu_commands.h
> > > +++ b/include/intel_gpu_commands.h
> > > @@ -123,6 +123,7 @@
> > >  #define MI_SEMAPHORE_WAIT      MI_INSTR(0x1c, 2) /* GEN8+ */
> > >  #define MI_SEMAPHORE_WAIT_TOKEN        MI_INSTR(0x1c, 3) /*
> > > GEN12+
> > > */
> > >  #define   MI_SEMAPHORE_POLL            (1 << 15)
> > > +#define   MI_SEMAPHORE_QUEUE_SWITCH_MODE       (1 << 11)
> > >  #define   MI_SEMAPHORE_SAD_GT_SDD      (0 << 12)
> > >  #define   MI_SEMAPHORE_SAD_GTE_SDD     (1 << 12)
> > >  #define   MI_SEMAPHORE_SAD_LT_SDD      (2 << 12)
> > > diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> > > index 72b13ef42..174c5f7ec 100644
> > > --- a/lib/xe/xe_spin.c
> > > +++ b/lib/xe/xe_spin.c
> > > @@ -57,6 +57,7 @@ void xe_spin_init(struct xe_spin *spin, struct
> > > xe_spin_opts *opts)
> > >  
> > >         spin->start = 0;
> > >         spin->end = 0xffffffff;
> > > +       spin->wait_cond = 0;
> > >         spin->ticks_delta = 0;
> > >  
> > >         if (opts->ctx_ticks) {
> > > @@ -167,6 +168,24 @@ void xe_spin_init(struct xe_spin *spin,
> > > struct
> > > xe_spin_opts *opts)
> > >                                    opts->mem_copy->dst-
> > > >mocs_index;
> > >         }
> > >  
> > > +       /*
> > > +        * Insert a MI_SEMAPHORE_WAIT_CMD instruction with
> > > condition
> > > controlled
> > > +        * by the user. It also acts as a queue switch point in
> > > multi
> > > queue mode.
> > > +        */
> > > +       if (opts->preempt) {
> > > +               uint64_t wait_addr = opts->addr + offsetof(struct
> > > xe_spin, wait_cond);
> > > +
> > > +               spin->batch[b++] = MI_SEMAPHORE_WAIT_CMD |
> > > +                               MI_SEMAPHORE_POLL |
> > > +                               MI_SEMAPHORE_QUEUE_SWITCH_MODE |
> > > +                               MI_SEMAPHORE_SAD_EQ_SDD |
> > > +                               3;
> > > +               spin->batch[b++] = 0;
> > 
> > Should this be set to spin->wait_cond in case we ever want to
> > change
> > the default value here?
> > 
> 
> wait_cond is already part of wait_addr. So, user can control the
> wait using xe_spin_preempt_wait()/nowait() functions below.

Ah right and this is just the value we're using to compare against the
user value. So yeah makes sense what we have.

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> 
> Niranjana
> 
> > Otherwise generally this is a great addition to the spinner
> > toolkit:
> > Reviewed-by: Stuart Summers <stuart.summers@intel.com>
> > 
> > > +               spin->batch[b++] = wait_addr;
> > > +               spin->batch[b++] = wait_addr >> 32;
> > > +               spin->batch[b++] = 0;
> > > +       }
> > > +
> > >         spin->batch[b++] = MI_COND_BATCH_BUFFER_END |
> > > MI_DO_COMPARE |
> > > 2;
> > >         spin->batch[b++] = 0;
> > >         spin->batch[b++] = end_addr;
> > > @@ -207,6 +226,28 @@ void xe_spin_end(struct xe_spin *spin)
> > >         WRITE_ONCE(spin->end, 0);
> > >  }
> > >  
> > > +/**
> > > + * xe_spin_preempt_wait:
> > > + * @spin: pointer to spinner mapped bo
> > > + *
> > > + * Make the spinner wait on the preemption semaphore.
> > > + */
> > > +void xe_spin_preempt_wait(struct xe_spin *spin)
> > > +{
> > > +       spin->wait_cond = 1;
> > > +}
> > > +
> > > +/**
> > > + * xe_spin_preempt_nowait:
> > > + * @spin: pointer to spinner mapped bo
> > > + *
> > > + * Make the spinner do not wait on the preemption semaphore.
> > > + */
> > > +void xe_spin_preempt_nowait(struct xe_spin *spin)
> > > +{
> > > +       spin->wait_cond = 0;
> > > +}
> > > +
> > >  /**
> > >   * xe_spin_create:
> > >   * @opt: controlling options such as allocator handle,
> > > exec_queue,
> > > vm etc
> > > diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> > > index c2199d0aa..eaf2a409e 100644
> > > --- a/lib/xe/xe_spin.h
> > > +++ b/lib/xe/xe_spin.h
> > > @@ -64,6 +64,7 @@ struct xe_spin {
> > >         uint64_t pad;
> > >         uint32_t start;
> > >         uint32_t end;
> > > +       uint32_t wait_cond;
> > >         uint32_t ticks_delta;
> > >         uint64_t exec_sync;
> > >         uint32_t timestamp;
> > > @@ -76,6 +77,8 @@ void xe_spin_init(struct xe_spin *spin, struct
> > > xe_spin_opts *opts);
> > >  bool xe_spin_started(struct xe_spin *spin);
> > >  void xe_spin_wait_started(struct xe_spin *spin);
> > >  void xe_spin_end(struct xe_spin *spin);
> > > +void xe_spin_preempt_wait(struct xe_spin *spin);
> > > +void xe_spin_preempt_nowait(struct xe_spin *spin);
> > >  
> > >  /*
> > >   * xe_cork: higher level API that simplifies exec'ing an xe_spin
> > > by
> > > taking care
> > 

[PATCH v2 15/19] tests/intel/xe_exec_multi_queue: Add priority test

[Niranjana Vishwanathapura]

Validate intra queue group priority setting.
Validate that a higher priority queue in a queue group
can preempt the lower priority queue of the group.

During a queue switch, the currently running queue is
always switched out without regard to its priority.
The priority is only a factor in determining which
other queue of the group will be scheduled in.

v2: Macro and variable rename (priyanka)
    Remove simulation related code (Priyanka)
    Remove hardcoding of number of bits.
    Use BASE_ADDRESS macro for address (Sai)

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Xin Wang <x.wang@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 203 ++++++++++++++++++++++++++++++
 1 file changed, 203 insertions(+)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index df65ccafb..06e898a47 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -13,15 +13,18 @@
 
 #include "igt.h"
 #include "xe_drm.h"
+#include "igt_core.h"
 #include "lib/igt_syncobj.h"
 
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
+#include "xe/xe_spin.h"
 
 #define XE_EXEC_QUEUE_PRIORITY_LOW	0
 #define XE_EXEC_QUEUE_PRIORITY_NORMAL	1
 #define XE_EXEC_QUEUE_PRIORITY_HIGH	2
 #define XE_EXEC_QUEUE_NUM_PRIORITIES	3
+#define XE_EXEC_QUEUE_PRIORITY_N	(XE_EXEC_QUEUE_NUM_PRIORITIES * 2 + 1)
 
 #define MAX_N_EXEC_QUEUES	64
 
@@ -33,6 +36,7 @@
 #define INVALIDATE		(0x1 << 5)
 #define FAULT_MODE		(0x1 << 6)
 #define SMEM			(0x1 << 7)
+#define WAIT_MODE		(0x1 << 8)
 
 #define MAX_INSTANCE 9
 
@@ -212,6 +216,201 @@ test_sanity(int fd, int gt, int class)
 	__test_sanity(fd, gt, class, true);
 }
 
+static void
+__test_priority(int fd, struct drm_xe_engine_class_instance *eci,
+		unsigned int flags)
+{
+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
+	struct drm_xe_sync sync = {
+		.type = DRM_XE_SYNC_TYPE_USER_FENCE,
+		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		.timeline_value = USER_FENCE_VALUE,
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&sync),
+	};
+	uint64_t vm_sync = 0, addr = BASE_ADDRESS;
+	uint32_t exec_queues[XE_EXEC_QUEUE_PRIORITY_N];
+	struct xe_spin *spin[XE_EXEC_QUEUE_PRIORITY_N];
+	uint32_t vm, num_queues, num_queue_priorities, bo = 0;
+	uint32_t start_order[XE_EXEC_QUEUE_PRIORITY_N] = { 0 };
+	int64_t fence_timeout = NSEC_PER_SEC;
+	size_t bo_size;
+	/*
+	 * Q1 - Q6 are used for the priority test.
+	 * Q Priority = id % 3
+	 * 	QID	Q1 Q2 Q3 Q4 Q5 Q6
+	 * Priority	 1  2  0  1  2  0
+	 * The Priority 1 and 0 are the same priority so hw should pick Q with priority: Q2, Q5, Q1, Q3, Q4, Q6
+	 */
+	int expect_order[] = {0,2,5,1,3,4,6};
+	uint32_t already_in_order = 0;		// bitmask to record Q started info
+	struct drm_xe_ext_set_property multi_queue = {
+		.base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+		.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
+		.value = DRM_XE_MULTI_GROUP_CREATE,
+	};
+	uint64_t ext = to_user_pointer(&multi_queue);
+	int i, j, sleep_duration = 1;
+	void *bo_map;
+
+	num_queue_priorities = XE_EXEC_QUEUE_NUM_PRIORITIES;
+	num_queues = num_queue_priorities * 2 + 1;
+	igt_assert(num_queues <= XE_EXEC_QUEUE_PRIORITY_N);
+	igt_assert(num_queues <= sizeof(uint32_t) * 8);
+
+	igt_debug("%s flags 0x%x eci %d:%d:%d\n", __func__, flags, eci[0].gt_id,
+		 eci[0].engine_class, eci[0].engine_instance);
+
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
+	bo_size = xe_bb_size(fd, sizeof(*spin[0]) * num_queues);
+
+	bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
+			  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+	bo_map = xe_bo_map(fd, bo, bo_size);
+	for (i = 0; i < num_queues; i++)
+		spin[i] = bo_map + i * sizeof(*spin[0]);
+
+	/* Use the default priority for Q0 because we are explicitly waiting for it below */
+	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
+	multi_queue.value = exec_queues[0];
+
+	if (flags & DYN_PRIORITY) {
+		for (i = 1; i < num_queues; i++)
+			exec_queues[i] = xe_exec_queue_create(fd, vm, eci, ext);
+	} else {
+		struct drm_xe_ext_set_property mq_priority = {
+			.base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+			.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
+		};
+
+		multi_queue.base.next_extension = to_user_pointer(&mq_priority);
+
+		/* Create secondary queues with increasing order of priority */
+		for (i = 1; i < num_queues; i++) {
+			mq_priority.value = i % num_queue_priorities;
+			exec_queues[i] = xe_exec_queue_create(fd, vm, eci, ext);
+		}
+	}
+
+	sync.addr = to_user_pointer(&vm_sync);
+	xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, &sync, 1);
+
+	xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, fence_timeout);
+	vm_sync = 0;
+
+	for (i = 0; i < num_queues; i++) {
+		uint64_t spin_addr = addr + i * sizeof(struct xe_spin);
+
+		xe_spin_init_opts(spin[i], .addr = spin_addr, .preempt = true);
+		sync.addr = spin_addr + (char *)&spin[i]->exec_sync - (char *)spin[i];
+		exec.exec_queue_id = exec_queues[i];
+		exec.address = spin_addr;
+		xe_exec(fd, &exec);
+
+		/* Wait for job on Q0 to start, allow other queues to run to completion */
+		if (!i)
+			xe_spin_wait_started(spin[i]);
+	}
+
+	sleep(sleep_duration);
+
+	/*
+	 * Expect the job on other queue to not get scheduled while the spinner
+	 * on q0 is not waiting on preempt condition.
+	 */
+	for (i = 1; i < num_queues; i++)
+		igt_assert(!xe_spin_started(spin[i]));
+
+	if (flags & DYN_PRIORITY) {
+		/* Assign increasing order of priority for secondary queues */
+		for (i = 1; i < num_queues; i++)
+			xe_exec_queue_set_property(fd, exec_queues[i],
+						   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
+						   i % num_queue_priorities);
+
+		/* Wait for priorities to take effect */
+		sleep(sleep_duration);
+	}
+
+	/*
+	 * Trigger a queue switch by making the spinner on q0 to wait on preempt
+	 * condition, allowing job on q1 to get scheduled and finish. When we end
+	 * the spin[0], it triggers the CFEG to perform a queue priority arbitration
+	 * rather than a full context switch out. Consequently, in both semaphore
+	 * (WAIT_MODE) and non-semaphore scenarios, a priority check will occur.
+	 */
+	if (flags & WAIT_MODE)
+		xe_spin_preempt_wait(spin[0]);
+	else
+		xe_spin_end(spin[0]);
+
+	/* Wait for jobs to get scheduled */
+	i = 1;
+	while (i < num_queues) {
+		for (j = 1; j < num_queues; j++) {
+			if (xe_spin_started(spin[j]) && ((already_in_order & (1 << j)) == 0)) {
+				start_order[i] = j;
+				xe_spin_end(spin[j]);
+				xe_wait_ufence(fd, &spin[j]->exec_sync, USER_FENCE_VALUE,
+					       exec_queues[j], fence_timeout);
+				already_in_order |= (1 << j);
+				i++;
+			}
+		}
+	}
+
+	/* While ending spinner on q0, bring it out of preempt wait */
+	if (flags & WAIT_MODE) {
+		xe_spin_end(spin[0]);
+		xe_spin_preempt_nowait(spin[0]);
+	}
+	xe_wait_ufence(fd, &spin[0]->exec_sync, USER_FENCE_VALUE, exec_queues[0], fence_timeout);
+
+	igt_debug("Order\t Actual\t Expect\n");
+	for (i = 1, j = 0; i < num_queues; i++) {
+		igt_debug("  %d\t  Q%d(%d)\t  Q%d(%d)\n",i, start_order[i], start_order[i] % num_queue_priorities,
+                         expect_order[i], expect_order[i] % num_queue_priorities);
+
+		/* The priority 0, 1 are the same, so we can skip the comparison */
+		if (expect_order[i] % num_queue_priorities < XE_EXEC_QUEUE_PRIORITY_HIGH &&
+		    start_order[i] % num_queue_priorities < XE_EXEC_QUEUE_PRIORITY_HIGH)
+			continue;
+
+		if (start_order[i] % num_queue_priorities != expect_order[i] % num_queue_priorities)
+			j++;
+	}
+	igt_assert(j == 0);
+
+	sync.addr = to_user_pointer(&vm_sync);
+	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
+	xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, fence_timeout);
+
+	for (i = 0; i < num_queues; i++)
+		xe_exec_queue_destroy(fd, exec_queues[i]);
+
+	munmap(bo_map, bo_size);
+	gem_close(fd, bo);
+
+	xe_vm_destroy(fd, vm);
+}
+
+/**
+ * SUBTEST: priority
+ * Description: Validate queue priority setting
+ * Test category: functionality test
+ */
+static void
+test_priority(int fd, struct drm_xe_engine_class_instance *eci)
+{
+	__test_priority(fd, eci, 0);
+	__test_priority(fd, eci, WAIT_MODE);
+	__test_priority(fd, eci, DYN_PRIORITY);
+	__test_priority(fd, eci, DYN_PRIORITY | WAIT_MODE);
+}
+
 static void
 test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci, int num_placement,
 		  int n_exec_queues, int n_execs, unsigned int flags)
@@ -707,6 +906,10 @@ igt_main
 			xe_for_each_multi_queue_engine_class(class)
 				test_exec_virtual(fd, gt, class);
 
+	igt_subtest_f("priority")
+		xe_for_each_multi_queue_engine(fd, hwe)
+			test_priority(fd, hwe);
+
 	for (const struct section *s = sections; s->name; s++) {
 		igt_subtest_f("one-queue-%s", s->name)
 			xe_for_each_multi_queue_engine(fd, hwe)
-- 
2.43.0

RE: [PATCH v2 15/19] tests/intel/xe_exec_multi_queue: Add priority test

[Dandamudi, Priyanka]

> -----Original Message-----
> From: Vishwanathapura, Niranjana <niranjana.vishwanathapura@intel.com>
> Sent: 21 November 2025 09:27 AM
> To: igt-dev@lists.freedesktop.org
> Cc: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>; kamil.konieczny@linux.intel.com
> Subject: [PATCH v2 15/19] tests/intel/xe_exec_multi_queue: Add priority test
> 
> Validate intra queue group priority setting.
> Validate that a higher priority queue in a queue group can preempt the lower
> priority queue of the group.
> 
> During a queue switch, the currently running queue is always switched out
> without regard to its priority.
> The priority is only a factor in determining which other queue of the group
> will be scheduled in.
> 
> v2: Macro and variable rename (priyanka)
>     Remove simulation related code (Priyanka)
>     Remove hardcoding of number of bits.
>     Use BASE_ADDRESS macro for address (Sai)
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> Signed-off-by: Xin Wang <x.wang@intel.com>
> ---
>  tests/intel/xe_exec_multi_queue.c | 203
> ++++++++++++++++++++++++++++++
>  1 file changed, 203 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index df65ccafb..06e898a47 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -13,15 +13,18 @@
> 
>  #include "igt.h"
>  #include "xe_drm.h"
> +#include "igt_core.h"
>  #include "lib/igt_syncobj.h"
> 
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
> +#include "xe/xe_spin.h"
> 
>  #define XE_EXEC_QUEUE_PRIORITY_LOW	0
>  #define XE_EXEC_QUEUE_PRIORITY_NORMAL	1
>  #define XE_EXEC_QUEUE_PRIORITY_HIGH	2
>  #define XE_EXEC_QUEUE_NUM_PRIORITIES	3
> +#define XE_EXEC_QUEUE_PRIORITY_N
> 	(XE_EXEC_QUEUE_NUM_PRIORITIES * 2 + 1)
> 
>  #define MAX_N_EXEC_QUEUES	64
> 
> @@ -33,6 +36,7 @@
>  #define INVALIDATE		(0x1 << 5)
>  #define FAULT_MODE		(0x1 << 6)
>  #define SMEM			(0x1 << 7)
> +#define WAIT_MODE		(0x1 << 8)
> 
>  #define MAX_INSTANCE 9
> 
> @@ -212,6 +216,201 @@ test_sanity(int fd, int gt, int class)
>  	__test_sanity(fd, gt, class, true);
>  }
> 
> +static void
> +__test_priority(int fd, struct drm_xe_engine_class_instance *eci,
> +		unsigned int flags)
> +{
> +#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
> +	struct drm_xe_sync sync = {
> +		.type = DRM_XE_SYNC_TYPE_USER_FENCE,
> +		.flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +		.timeline_value = USER_FENCE_VALUE,
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.num_syncs = 1,
> +		.syncs = to_user_pointer(&sync),
> +	};
> +	uint64_t vm_sync = 0, addr = BASE_ADDRESS;
> +	uint32_t exec_queues[XE_EXEC_QUEUE_PRIORITY_N];
> +	struct xe_spin *spin[XE_EXEC_QUEUE_PRIORITY_N];
> +	uint32_t vm, num_queues, num_queue_priorities, bo = 0;
> +	uint32_t start_order[XE_EXEC_QUEUE_PRIORITY_N] = { 0 };
> +	int64_t fence_timeout = NSEC_PER_SEC;
> +	size_t bo_size;
> +	/*
> +	 * Q1 - Q6 are used for the priority test.
> +	 * Q Priority = id % 3
> +	 * 	QID	Q1 Q2 Q3 Q4 Q5 Q6
> +	 * Priority	 1  2  0  1  2  0
> +	 * The Priority 1 and 0 are the same priority so hw should pick Q with
> priority: Q2, Q5, Q1, Q3, Q4, Q6
> +	 */
> +	int expect_order[] = {0,2,5,1,3,4,6};
> +	uint32_t already_in_order = 0;		// bitmask to record Q started
> info
> +	struct drm_xe_ext_set_property multi_queue = {
> +		.base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +		.property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
> +		.value = DRM_XE_MULTI_GROUP_CREATE,
> +	};
> +	uint64_t ext = to_user_pointer(&multi_queue);
> +	int i, j, sleep_duration = 1;
> +	void *bo_map;
> +
> +	num_queue_priorities = XE_EXEC_QUEUE_NUM_PRIORITIES;
> +	num_queues = num_queue_priorities * 2 + 1;
> +	igt_assert(num_queues <= XE_EXEC_QUEUE_PRIORITY_N);
> +	igt_assert(num_queues <= sizeof(uint32_t) * 8);
> +
> +	igt_debug("%s flags 0x%x eci %d:%d:%d\n", __func__, flags,
> eci[0].gt_id,
> +		 eci[0].engine_class, eci[0].engine_instance);
> +
> +	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> +	bo_size = xe_bb_size(fd, sizeof(*spin[0]) * num_queues);
> +
> +	bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
> +
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +	bo_map = xe_bo_map(fd, bo, bo_size);
> +	for (i = 0; i < num_queues; i++)
> +		spin[i] = bo_map + i * sizeof(*spin[0]);
> +
> +	/* Use the default priority for Q0 because we are explicitly waiting for
> it below */
> +	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> +	multi_queue.value = exec_queues[0];
> +
> +	if (flags & DYN_PRIORITY) {
> +		for (i = 1; i < num_queues; i++)
> +			exec_queues[i] = xe_exec_queue_create(fd, vm, eci,
> ext);
> +	} else {
> +		struct drm_xe_ext_set_property mq_priority = {
> +			.base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +			.property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> +		};
> +
> +		multi_queue.base.next_extension =
> to_user_pointer(&mq_priority);
> +
> +		/* Create secondary queues with increasing order of priority
> */
> +		for (i = 1; i < num_queues; i++) {
> +			mq_priority.value = i % num_queue_priorities;
> +			exec_queues[i] = xe_exec_queue_create(fd, vm, eci,
> ext);
> +		}
> +	}
> +
> +	sync.addr = to_user_pointer(&vm_sync);
> +	xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, &sync, 1);
> +
> +	xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
> fence_timeout);
> +	vm_sync = 0;
> +
> +	for (i = 0; i < num_queues; i++) {
> +		uint64_t spin_addr = addr + i * sizeof(struct xe_spin);
> +
> +		xe_spin_init_opts(spin[i], .addr = spin_addr, .preempt =
> true);
> +		sync.addr = spin_addr + (char *)&spin[i]->exec_sync - (char
> *)spin[i];
> +		exec.exec_queue_id = exec_queues[i];
> +		exec.address = spin_addr;
> +		xe_exec(fd, &exec);
> +
> +		/* Wait for job on Q0 to start, allow other queues to run to
> completion */
> +		if (!i)
> +			xe_spin_wait_started(spin[i]);
> +	}
> +
> +	sleep(sleep_duration);
> +
> +	/*
> +	 * Expect the job on other queue to not get scheduled while the
> spinner
> +	 * on q0 is not waiting on preempt condition.
> +	 */
> +	for (i = 1; i < num_queues; i++)
> +		igt_assert(!xe_spin_started(spin[i]));
> +
> +	if (flags & DYN_PRIORITY) {
> +		/* Assign increasing order of priority for secondary queues */
> +		for (i = 1; i < num_queues; i++)
> +			xe_exec_queue_set_property(fd, exec_queues[i],
> +
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> +						   i % num_queue_priorities);
> +
> +		/* Wait for priorities to take effect */
> +		sleep(sleep_duration);
> +	}
> +
> +	/*
> +	 * Trigger a queue switch by making the spinner on q0 to wait on
> preempt
> +	 * condition, allowing job on q1 to get scheduled and finish. When
> we end
> +	 * the spin[0], it triggers the CFEG to perform a queue priority
> arbitration
> +	 * rather than a full context switch out. Consequently, in both
> semaphore
> +	 * (WAIT_MODE) and non-semaphore scenarios, a priority check will
> occur.
> +	 */
> +	if (flags & WAIT_MODE)
> +		xe_spin_preempt_wait(spin[0]);
> +	else
> +		xe_spin_end(spin[0]);
> +
> +	/* Wait for jobs to get scheduled */
> +	i = 1;
> +	while (i < num_queues) {
> +		for (j = 1; j < num_queues; j++) {
> +			if (xe_spin_started(spin[j]) && ((already_in_order &
> (1 << j)) == 0)) {
> +				start_order[i] = j;
> +				xe_spin_end(spin[j]);
> +				xe_wait_ufence(fd, &spin[j]->exec_sync,
> USER_FENCE_VALUE,
> +					       exec_queues[j], fence_timeout);
> +				already_in_order |= (1 << j);
> +				i++;
> +			}
> +		}
> +	}
> +
> +	/* While ending spinner on q0, bring it out of preempt wait */
> +	if (flags & WAIT_MODE) {
> +		xe_spin_end(spin[0]);
> +		xe_spin_preempt_nowait(spin[0]);
> +	}
> +	xe_wait_ufence(fd, &spin[0]->exec_sync, USER_FENCE_VALUE,
> +exec_queues[0], fence_timeout);
> +
> +	igt_debug("Order\t Actual\t Expect\n");
> +	for (i = 1, j = 0; i < num_queues; i++) {
> +		igt_debug("  %d\t  Q%d(%d)\t  Q%d(%d)\n",i, start_order[i],
> start_order[i] % num_queue_priorities,
> +                         expect_order[i], expect_order[i] %
> +num_queue_priorities);
> +
> +		/* The priority 0, 1 are the same, so we can skip the
> comparison */
> +		if (expect_order[i] % num_queue_priorities <
> XE_EXEC_QUEUE_PRIORITY_HIGH &&
> +		    start_order[i] % num_queue_priorities <
> XE_EXEC_QUEUE_PRIORITY_HIGH)
> +			continue;
> +
> +		if (start_order[i] % num_queue_priorities != expect_order[i]
> % num_queue_priorities)
> +			j++;
> +	}
> +	igt_assert(j == 0);
> +
> +	sync.addr = to_user_pointer(&vm_sync);
> +	xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
> +	xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
> fence_timeout);
> +
> +	for (i = 0; i < num_queues; i++)
> +		xe_exec_queue_destroy(fd, exec_queues[i]);
> +
> +	munmap(bo_map, bo_size);
> +	gem_close(fd, bo);
> +
> +	xe_vm_destroy(fd, vm);
> +}
> +
> +/**
> + * SUBTEST: priority
> + * Description: Validate queue priority setting
> + * Test category: functionality test
> + */
> +static void
> +test_priority(int fd, struct drm_xe_engine_class_instance *eci) {
> +	__test_priority(fd, eci, 0);
> +	__test_priority(fd, eci, WAIT_MODE);
> +	__test_priority(fd, eci, DYN_PRIORITY);
> +	__test_priority(fd, eci, DYN_PRIORITY | WAIT_MODE); }
> +
>  static void
>  test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement,
>  		  int n_exec_queues, int n_execs, unsigned int flags) @@ -
> 707,6 +906,10 @@ igt_main
>  			xe_for_each_multi_queue_engine_class(class)
>  				test_exec_virtual(fd, gt, class);
> 
> +	igt_subtest_f("priority")
> +		xe_for_each_multi_queue_engine(fd, hwe)
> +			test_priority(fd, hwe);
> +
>  	for (const struct section *s = sections; s->name; s++) {
>  		igt_subtest_f("one-queue-%s", s->name)
>  			xe_for_each_multi_queue_engine(fd, hwe)
LGTM,
Reviewed-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> --
> 2.43.0

Re: [PATCH v2 15/19] tests/intel/xe_exec_multi_queue: Add priority test

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Validate intra queue group priority setting.
> Validate that a higher priority queue in a queue group
> can preempt the lower priority queue of the group.
> 
> During a queue switch, the currently running queue is
> always switched out without regard to its priority.
> The priority is only a factor in determining which
> other queue of the group will be scheduled in.
> 
> v2: Macro and variable rename (priyanka)
>     Remove simulation related code (Priyanka)
>     Remove hardcoding of number of bits.
>     Use BASE_ADDRESS macro for address (Sai)
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> Signed-off-by: Xin Wang <x.wang@intel.com>
> ---
>  tests/intel/xe_exec_multi_queue.c | 203
> ++++++++++++++++++++++++++++++
>  1 file changed, 203 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index df65ccafb..06e898a47 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -13,15 +13,18 @@
>  
>  #include "igt.h"
>  #include "xe_drm.h"
> +#include "igt_core.h"
>  #include "lib/igt_syncobj.h"
>  
>  #include "xe/xe_ioctl.h"
>  #include "xe/xe_query.h"
> +#include "xe/xe_spin.h"
>  
>  #define XE_EXEC_QUEUE_PRIORITY_LOW     0
>  #define XE_EXEC_QUEUE_PRIORITY_NORMAL  1
>  #define XE_EXEC_QUEUE_PRIORITY_HIGH    2
>  #define XE_EXEC_QUEUE_NUM_PRIORITIES   3
> +#define XE_EXEC_QUEUE_PRIORITY_N       (XE_EXEC_QUEUE_NUM_PRIORITIES
> * 2 + 1)
>  
>  #define MAX_N_EXEC_QUEUES      64
>  
> @@ -33,6 +36,7 @@
>  #define INVALIDATE             (0x1 << 5)
>  #define FAULT_MODE             (0x1 << 6)
>  #define SMEM                   (0x1 << 7)
> +#define WAIT_MODE              (0x1 << 8)
>  
>  #define MAX_INSTANCE 9
>  
> @@ -212,6 +216,201 @@ test_sanity(int fd, int gt, int class)
>         __test_sanity(fd, gt, class, true);
>  }
>  
> +static void
> +__test_priority(int fd, struct drm_xe_engine_class_instance *eci,
> +               unsigned int flags)
> +{
> +#define USER_FENCE_VALUE       0xdeadbeefdeadbeefull
> +       struct drm_xe_sync sync = {
> +               .type = DRM_XE_SYNC_TYPE_USER_FENCE,
> +               .flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +               .timeline_value = USER_FENCE_VALUE,
> +       };
> +       struct drm_xe_exec exec = {
> +               .num_batch_buffer = 1,
> +               .num_syncs = 1,
> +               .syncs = to_user_pointer(&sync),
> +       };
> +       uint64_t vm_sync = 0, addr = BASE_ADDRESS;
> +       uint32_t exec_queues[XE_EXEC_QUEUE_PRIORITY_N];
> +       struct xe_spin *spin[XE_EXEC_QUEUE_PRIORITY_N];
> +       uint32_t vm, num_queues, num_queue_priorities, bo = 0;
> +       uint32_t start_order[XE_EXEC_QUEUE_PRIORITY_N] = { 0 };
> +       int64_t fence_timeout = NSEC_PER_SEC;
> +       size_t bo_size;
> +       /*
> +        * Q1 - Q6 are used for the priority test.
> +        * Q Priority = id % 3
> +        *      QID     Q1 Q2 Q3 Q4 Q5 Q6
> +        * Priority      1  2  0  1  2  0
> +        * The Priority 1 and 0 are the same priority so hw should
> pick Q with priority: Q2, Q5, Q1, Q3, Q4, Q6

I think we should reword this to something like:
Hardware treats priority 0 and 1 the same, so hw should pick Q with
priority...

> +        */
> +       int expect_order[] = {0,2,5,1,3,4,6};
> +       uint32_t already_in_order = 0;          // bitmask to record
> Q started info
> +       struct drm_xe_ext_set_property multi_queue = {
> +               .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +               .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
> +               .value = DRM_XE_MULTI_GROUP_CREATE,
> +       };
> +       uint64_t ext = to_user_pointer(&multi_queue);
> +       int i, j, sleep_duration = 1;
> +       void *bo_map;
> +
> +       num_queue_priorities = XE_EXEC_QUEUE_NUM_PRIORITIES;
> +       num_queues = num_queue_priorities * 2 + 1;
> +       igt_assert(num_queues <= XE_EXEC_QUEUE_PRIORITY_N);
> +       igt_assert(num_queues <= sizeof(uint32_t) * 8);
> +
> +       igt_debug("%s flags 0x%x eci %d:%d:%d\n", __func__, flags,
> eci[0].gt_id,
> +                eci[0].engine_class, eci[0].engine_instance);
> +
> +       vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> +       bo_size = xe_bb_size(fd, sizeof(*spin[0]) * num_queues);
> +
> +       bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd,
> eci[0].gt_id),
> +                         DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +       bo_map = xe_bo_map(fd, bo, bo_size);
> +       for (i = 0; i < num_queues; i++)
> +               spin[i] = bo_map + i * sizeof(*spin[0]);
> +
> +       /* Use the default priority for Q0 because we are explicitly
> waiting for it below */
> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> +       multi_queue.value = exec_queues[0];
> +
> +       if (flags & DYN_PRIORITY) {
> +               for (i = 1; i < num_queues; i++)
> +                       exec_queues[i] = xe_exec_queue_create(fd, vm,
> eci, ext);
> +       } else {
> +               struct drm_xe_ext_set_property mq_priority = {
> +                       .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +                       .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> +               };
> +
> +               multi_queue.base.next_extension =
> to_user_pointer(&mq_priority);
> +
> +               /* Create secondary queues with increasing order of
> priority */
> +               for (i = 1; i < num_queues; i++) {
> +                       mq_priority.value = i % num_queue_priorities;
> +                       exec_queues[i] = xe_exec_queue_create(fd, vm,
> eci, ext);
> +               }
> +       }
> +
> +       sync.addr = to_user_pointer(&vm_sync);
> +       xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, &sync, 1);
> +
> +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
> fence_timeout);
> +       vm_sync = 0;
> +
> +       for (i = 0; i < num_queues; i++) {
> +               uint64_t spin_addr = addr + i * sizeof(struct
> xe_spin);
> +
> +               xe_spin_init_opts(spin[i], .addr = spin_addr,
> .preempt = true);
> +               sync.addr = spin_addr + (char *)&spin[i]->exec_sync -
> (char *)spin[i];
> +               exec.exec_queue_id = exec_queues[i];
> +               exec.address = spin_addr;
> +               xe_exec(fd, &exec);
> +
> +               /* Wait for job on Q0 to start, allow other queues to
> run to completion */

So in this case we aren't waiting for anything with the other queues,
only Q0. We don't know if the other queues are sitting waiting for Q0
to end (or the semaphore to clear) or not. Maybe:
/* Wait for job on Q0 to start, other queues block behind Q0 */

> +               if (!i)
> +                       xe_spin_wait_started(spin[i]);
> +       }
> +
> +       sleep(sleep_duration);
> +
> +       /*
> +        * Expect the job on other queue to not get scheduled while
> the spinner
> +        * on q0 is not waiting on preempt condition.
> +        */
> +       for (i = 1; i < num_queues; i++)
> +               igt_assert(!xe_spin_started(spin[i]));
> +
> +       if (flags & DYN_PRIORITY) {
> +               /* Assign increasing order of priority for secondary
> queues */
> +               for (i = 1; i < num_queues; i++)
> +                       xe_exec_queue_set_property(fd,
> exec_queues[i],
> +                                                 
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> +                                                  i %
> num_queue_priorities);
> +
> +               /* Wait for priorities to take effect */
> +               sleep(sleep_duration);

I'd really rather have a way to determine these are set
programmatically... What if we moved this whole if condition up above
the xe_exec call to ensure the H2G ordering of the priority set
followed by the exec?

> +       }
> +
> +       /*
> +        * Trigger a queue switch by making the spinner on q0 to wait
> on preempt
> +        * condition, allowing job on q1 to get scheduled and finish.
> When we end
> +        * the spin[0], it triggers the CFEG to perform a queue
> priority arbitration
> +        * rather than a full context switch out. Consequently, in
> both semaphore
> +        * (WAIT_MODE) and non-semaphore scenarios, a priority check
> will occur.
> +        */

The CFEG arbitration points:
Semaphore wait successful/unsuccessful
 - covered here

Head == Tail
 - covered here in the spin_end below

Thread group end met in the walker
 - expected to be covered by compute tests
   - of course the compute UMD tests should support these checks
   - I don't see us doing anything here in IGT though. Should we?

pipecontrol/barrier with queue drain mode set
 - UMD is testing this I believe, but should we do that here also?

> +       if (flags & WAIT_MODE)
> +               xe_spin_preempt_wait(spin[0]);
> +       else
> +               xe_spin_end(spin[0]);

Do we want to wait for the spin end to take place before jumping to the
next sequence in the test?

> +
> +       /* Wait for jobs to get scheduled */
> +       i = 1;
> +       while (i < num_queues) {
> +               for (j = 1; j < num_queues; j++) {
> +                       if (xe_spin_started(spin[j]) &&
> ((already_in_order & (1 << j)) == 0)) {
> +                               start_order[i] = j;
> +                               xe_spin_end(spin[j]);
> +                               xe_wait_ufence(fd, &spin[j]-
> >exec_sync, USER_FENCE_VALUE,
> +                                              exec_queues[j],
> fence_timeout);
> +                               already_in_order |= (1 << j);
> +                               i++;
> +                       }
> +               }
> +       }
> +
> +       /* While ending spinner on q0, bring it out of preempt wait
> */
> +       if (flags & WAIT_MODE) {
> +               xe_spin_end(spin[0]);
> +               xe_spin_preempt_nowait(spin[0]);
> +       }
> +       xe_wait_ufence(fd, &spin[0]->exec_sync, USER_FENCE_VALUE,
> exec_queues[0], fence_timeout);
> +
> +       igt_debug("Order\t Actual\t Expect\n");
> +       for (i = 1, j = 0; i < num_queues; i++) {
> +               igt_debug("  %d\t  Q%d(%d)\t  Q%d(%d)\n",i,
> start_order[i], start_order[i] % num_queue_priorities,
> +                         expect_order[i], expect_order[i] %
> num_queue_priorities);
> +
> +               /* The priority 0, 1 are the same, so we can skip the
> comparison */
> +               if (expect_order[i] % num_queue_priorities <
> XE_EXEC_QUEUE_PRIORITY_HIGH &&
> +                   start_order[i] % num_queue_priorities <
> XE_EXEC_QUEUE_PRIORITY_HIGH)
> +                       continue;

The downside to this approach is if we get some future hardware that
has more than two priorities where more than two of these are the same,
we'll need to rework this.

> +
> +               if (start_order[i] % num_queue_priorities !=
> expect_order[i] % num_queue_priorities)
> +                       j++;

Instead of calling this 'j' can we use 'num_out_of_order' or something
to be more specific?

Thanks,
Stuart

> +       }
> +       igt_assert(j == 0);
> +
> +       sync.addr = to_user_pointer(&vm_sync);
> +       xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
> +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
> fence_timeout);
> +
> +       for (i = 0; i < num_queues; i++)
> +               xe_exec_queue_destroy(fd, exec_queues[i]);
> +
> +       munmap(bo_map, bo_size);
> +       gem_close(fd, bo);
> +
> +       xe_vm_destroy(fd, vm);
> +}
> +
> +/**
> + * SUBTEST: priority
> + * Description: Validate queue priority setting
> + * Test category: functionality test
> + */
> +static void
> +test_priority(int fd, struct drm_xe_engine_class_instance *eci)
> +{
> +       __test_priority(fd, eci, 0);
> +       __test_priority(fd, eci, WAIT_MODE);
> +       __test_priority(fd, eci, DYN_PRIORITY);
> +       __test_priority(fd, eci, DYN_PRIORITY | WAIT_MODE);
> +}
> +
>  static void
>  test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci,
> int num_placement,
>                   int n_exec_queues, int n_execs, unsigned int flags)
> @@ -707,6 +906,10 @@ igt_main
>                         xe_for_each_multi_queue_engine_class(class)
>                                 test_exec_virtual(fd, gt, class);
>  
> +       igt_subtest_f("priority")
> +               xe_for_each_multi_queue_engine(fd, hwe)
> +                       test_priority(fd, hwe);
> +
>         for (const struct section *s = sections; s->name; s++) {
>                 igt_subtest_f("one-queue-%s", s->name)
>                         xe_for_each_multi_queue_engine(fd, hwe)

Re: [PATCH v2 15/19] tests/intel/xe_exec_multi_queue: Add priority test

[Niranjana Vishwanathapura]

On Thu, Dec 04, 2025 at 01:53:26PM -0800, Summers, Stuart wrote:
>On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
>> Validate intra queue group priority setting.
>> Validate that a higher priority queue in a queue group
>> can preempt the lower priority queue of the group.
>>
>> During a queue switch, the currently running queue is
>> always switched out without regard to its priority.
>> The priority is only a factor in determining which
>> other queue of the group will be scheduled in.
>>
>> v2: Macro and variable rename (priyanka)
>>     Remove simulation related code (Priyanka)
>>     Remove hardcoding of number of bits.
>>     Use BASE_ADDRESS macro for address (Sai)
>>
>> Signed-off-by: Niranjana Vishwanathapura
>> <niranjana.vishwanathapura@intel.com>
>> Signed-off-by: Xin Wang <x.wang@intel.com>
>> ---
>>  tests/intel/xe_exec_multi_queue.c | 203
>> ++++++++++++++++++++++++++++++
>>  1 file changed, 203 insertions(+)
>>
>> diff --git a/tests/intel/xe_exec_multi_queue.c
>> b/tests/intel/xe_exec_multi_queue.c
>> index df65ccafb..06e898a47 100644
>> --- a/tests/intel/xe_exec_multi_queue.c
>> +++ b/tests/intel/xe_exec_multi_queue.c
>> @@ -13,15 +13,18 @@
>>  
>>  #include "igt.h"
>>  #include "xe_drm.h"
>> +#include "igt_core.h"
>>  #include "lib/igt_syncobj.h"
>>  
>>  #include "xe/xe_ioctl.h"
>>  #include "xe/xe_query.h"
>> +#include "xe/xe_spin.h"
>>  
>>  #define XE_EXEC_QUEUE_PRIORITY_LOW     0
>>  #define XE_EXEC_QUEUE_PRIORITY_NORMAL  1
>>  #define XE_EXEC_QUEUE_PRIORITY_HIGH    2
>>  #define XE_EXEC_QUEUE_NUM_PRIORITIES   3
>> +#define XE_EXEC_QUEUE_PRIORITY_N       (XE_EXEC_QUEUE_NUM_PRIORITIES
>> * 2 + 1)
>>  
>>  #define MAX_N_EXEC_QUEUES      64
>>  
>> @@ -33,6 +36,7 @@
>>  #define INVALIDATE             (0x1 << 5)
>>  #define FAULT_MODE             (0x1 << 6)
>>  #define SMEM                   (0x1 << 7)
>> +#define WAIT_MODE              (0x1 << 8)
>>  
>>  #define MAX_INSTANCE 9
>>  
>> @@ -212,6 +216,201 @@ test_sanity(int fd, int gt, int class)
>>         __test_sanity(fd, gt, class, true);
>>  }
>>  
>> +static void
>> +__test_priority(int fd, struct drm_xe_engine_class_instance *eci,
>> +               unsigned int flags)
>> +{
>> +#define USER_FENCE_VALUE       0xdeadbeefdeadbeefull
>> +       struct drm_xe_sync sync = {
>> +               .type = DRM_XE_SYNC_TYPE_USER_FENCE,
>> +               .flags = DRM_XE_SYNC_FLAG_SIGNAL,
>> +               .timeline_value = USER_FENCE_VALUE,
>> +       };
>> +       struct drm_xe_exec exec = {
>> +               .num_batch_buffer = 1,
>> +               .num_syncs = 1,
>> +               .syncs = to_user_pointer(&sync),
>> +       };
>> +       uint64_t vm_sync = 0, addr = BASE_ADDRESS;
>> +       uint32_t exec_queues[XE_EXEC_QUEUE_PRIORITY_N];
>> +       struct xe_spin *spin[XE_EXEC_QUEUE_PRIORITY_N];
>> +       uint32_t vm, num_queues, num_queue_priorities, bo = 0;
>> +       uint32_t start_order[XE_EXEC_QUEUE_PRIORITY_N] = { 0 };
>> +       int64_t fence_timeout = NSEC_PER_SEC;
>> +       size_t bo_size;
>> +       /*
>> +        * Q1 - Q6 are used for the priority test.
>> +        * Q Priority = id % 3
>> +        *      QID     Q1 Q2 Q3 Q4 Q5 Q6
>> +        * Priority      1  2  0  1  2  0
>> +        * The Priority 1 and 0 are the same priority so hw should
>> pick Q with priority: Q2, Q5, Q1, Q3, Q4, Q6
>
>I think we should reword this to something like:
>Hardware treats priority 0 and 1 the same, so hw should pick Q with
>priority...

Ok, will update.

>
>> +        */
>> +       int expect_order[] = {0,2,5,1,3,4,6};
>> +       uint32_t already_in_order = 0;          // bitmask to record
>> Q started info
>> +       struct drm_xe_ext_set_property multi_queue = {
>> +               .base.name =
>> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
>> +               .property =
>> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
>> +               .value = DRM_XE_MULTI_GROUP_CREATE,
>> +       };
>> +       uint64_t ext = to_user_pointer(&multi_queue);
>> +       int i, j, sleep_duration = 1;
>> +       void *bo_map;
>> +
>> +       num_queue_priorities = XE_EXEC_QUEUE_NUM_PRIORITIES;
>> +       num_queues = num_queue_priorities * 2 + 1;
>> +       igt_assert(num_queues <= XE_EXEC_QUEUE_PRIORITY_N);
>> +       igt_assert(num_queues <= sizeof(uint32_t) * 8);
>> +
>> +       igt_debug("%s flags 0x%x eci %d:%d:%d\n", __func__, flags,
>> eci[0].gt_id,
>> +                eci[0].engine_class, eci[0].engine_instance);
>> +
>> +       vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
>> +       bo_size = xe_bb_size(fd, sizeof(*spin[0]) * num_queues);
>> +
>> +       bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd,
>> eci[0].gt_id),
>> +                         DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>> +       bo_map = xe_bo_map(fd, bo, bo_size);
>> +       for (i = 0; i < num_queues; i++)
>> +               spin[i] = bo_map + i * sizeof(*spin[0]);
>> +
>> +       /* Use the default priority for Q0 because we are explicitly
>> waiting for it below */
>> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
>> +       multi_queue.value = exec_queues[0];
>> +
>> +       if (flags & DYN_PRIORITY) {
>> +               for (i = 1; i < num_queues; i++)
>> +                       exec_queues[i] = xe_exec_queue_create(fd, vm,
>> eci, ext);
>> +       } else {
>> +               struct drm_xe_ext_set_property mq_priority = {
>> +                       .base.name =
>> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
>> +                       .property =
>> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
>> +               };
>> +
>> +               multi_queue.base.next_extension =
>> to_user_pointer(&mq_priority);
>> +
>> +               /* Create secondary queues with increasing order of
>> priority */
>> +               for (i = 1; i < num_queues; i++) {
>> +                       mq_priority.value = i % num_queue_priorities;
>> +                       exec_queues[i] = xe_exec_queue_create(fd, vm,
>> eci, ext);
>> +               }
>> +       }
>> +
>> +       sync.addr = to_user_pointer(&vm_sync);
>> +       xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, &sync, 1);
>> +
>> +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
>> fence_timeout);
>> +       vm_sync = 0;
>> +
>> +       for (i = 0; i < num_queues; i++) {
>> +               uint64_t spin_addr = addr + i * sizeof(struct
>> xe_spin);
>> +
>> +               xe_spin_init_opts(spin[i], .addr = spin_addr,
>> .preempt = true);
>> +               sync.addr = spin_addr + (char *)&spin[i]->exec_sync -
>> (char *)spin[i];
>> +               exec.exec_queue_id = exec_queues[i];
>> +               exec.address = spin_addr;
>> +               xe_exec(fd, &exec);
>> +
>> +               /* Wait for job on Q0 to start, allow other queues to
>> run to completion */
>
>So in this case we aren't waiting for anything with the other queues,
>only Q0. We don't know if the other queues are sitting waiting for Q0
>to end (or the semaphore to clear) or not. Maybe:
>/* Wait for job on Q0 to start, other queues block behind Q0 */
>

Ok, will update.

>> +               if (!i)
>> +                       xe_spin_wait_started(spin[i]);
>> +       }
>> +
>> +       sleep(sleep_duration);
>> +
>> +       /*
>> +        * Expect the job on other queue to not get scheduled while
>> the spinner
>> +        * on q0 is not waiting on preempt condition.
>> +        */
>> +       for (i = 1; i < num_queues; i++)
>> +               igt_assert(!xe_spin_started(spin[i]));
>> +
>> +       if (flags & DYN_PRIORITY) {
>> +               /* Assign increasing order of priority for secondary
>> queues */
>> +               for (i = 1; i < num_queues; i++)
>> +                       xe_exec_queue_set_property(fd,
>> exec_queues[i],
>> +                                                 
>> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
>> +                                                  i %
>> num_queue_priorities);
>> +
>> +               /* Wait for priorities to take effect */
>> +               sleep(sleep_duration);
>
>I'd really rather have a way to determine these are set
>programmatically... What if we moved this whole if condition up above
>the xe_exec call to ensure the H2G ordering of the priority set
>followed by the exec?
>

No, the idea here is to dynamically change the priority. i.e,
after the job has been submitted to the HW.

>> +       }
>> +
>> +       /*
>> +        * Trigger a queue switch by making the spinner on q0 to wait
>> on preempt
>> +        * condition, allowing job on q1 to get scheduled and finish.
>> When we end
>> +        * the spin[0], it triggers the CFEG to perform a queue
>> priority arbitration
>> +        * rather than a full context switch out. Consequently, in
>> both semaphore
>> +        * (WAIT_MODE) and non-semaphore scenarios, a priority check
>> will occur.
>> +        */
>
>The CFEG arbitration points:
>Semaphore wait successful/unsuccessful
> - covered here
>
>Head == Tail
> - covered here in the spin_end below
>
>Thread group end met in the walker
> - expected to be covered by compute tests
>   - of course the compute UMD tests should support these checks
>   - I don't see us doing anything here in IGT though. Should we?
>
>pipecontrol/barrier with queue drain mode set
> - UMD is testing this I believe, but should we do that here also?
>

Yah, the idea here is to cover the arbitration cases that IGT
can easily test for. Will leave UMD validation to cover the rest.

>> +       if (flags & WAIT_MODE)
>> +               xe_spin_preempt_wait(spin[0]);
>> +       else
>> +               xe_spin_end(spin[0]);
>
>Do we want to wait for the spin end to take place before jumping to the
>next sequence in the test?
>

There is no added benefit in that.

>> +
>> +       /* Wait for jobs to get scheduled */
>> +       i = 1;
>> +       while (i < num_queues) {
>> +               for (j = 1; j < num_queues; j++) {
>> +                       if (xe_spin_started(spin[j]) &&
>> ((already_in_order & (1 << j)) == 0)) {
>> +                               start_order[i] = j;
>> +                               xe_spin_end(spin[j]);
>> +                               xe_wait_ufence(fd, &spin[j]-
>> >exec_sync, USER_FENCE_VALUE,
>> +                                              exec_queues[j],
>> fence_timeout);
>> +                               already_in_order |= (1 << j);
>> +                               i++;
>> +                       }
>> +               }
>> +       }
>> +
>> +       /* While ending spinner on q0, bring it out of preempt wait
>> */
>> +       if (flags & WAIT_MODE) {
>> +               xe_spin_end(spin[0]);
>> +               xe_spin_preempt_nowait(spin[0]);
>> +       }
>> +       xe_wait_ufence(fd, &spin[0]->exec_sync, USER_FENCE_VALUE,
>> exec_queues[0], fence_timeout);
>> +
>> +       igt_debug("Order\t Actual\t Expect\n");
>> +       for (i = 1, j = 0; i < num_queues; i++) {
>> +               igt_debug("  %d\t  Q%d(%d)\t  Q%d(%d)\n",i,
>> start_order[i], start_order[i] % num_queue_priorities,
>> +                         expect_order[i], expect_order[i] %
>> num_queue_priorities);
>> +
>> +               /* The priority 0, 1 are the same, so we can skip the
>> comparison */
>> +               if (expect_order[i] % num_queue_priorities <
>> XE_EXEC_QUEUE_PRIORITY_HIGH &&
>> +                   start_order[i] % num_queue_priorities <
>> XE_EXEC_QUEUE_PRIORITY_HIGH)
>> +                       continue;
>
>The downside to this approach is if we get some future hardware that
>has more than two priorities where more than two of these are the same,
>we'll need to rework this.
>

I think it should be one off thing and we shouldn't complicate the
design for that.

>> +
>> +               if (start_order[i] % num_queue_priorities !=
>> expect_order[i] % num_queue_priorities)
>> +                       j++;
>
>Instead of calling this 'j' can we use 'num_out_of_order' or something
>to be more specific?
>

Hmm...we already have 'j' which we can use. Let me added a comment
here so that it becomes more readable.

Niranjana

>Thanks,
>Stuart
>
>> +       }
>> +       igt_assert(j == 0);
>> +
>> +       sync.addr = to_user_pointer(&vm_sync);
>> +       xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync, 1);
>> +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
>> fence_timeout);
>> +
>> +       for (i = 0; i < num_queues; i++)
>> +               xe_exec_queue_destroy(fd, exec_queues[i]);
>> +
>> +       munmap(bo_map, bo_size);
>> +       gem_close(fd, bo);
>> +
>> +       xe_vm_destroy(fd, vm);
>> +}
>> +
>> +/**
>> + * SUBTEST: priority
>> + * Description: Validate queue priority setting
>> + * Test category: functionality test
>> + */
>> +static void
>> +test_priority(int fd, struct drm_xe_engine_class_instance *eci)
>> +{
>> +       __test_priority(fd, eci, 0);
>> +       __test_priority(fd, eci, WAIT_MODE);
>> +       __test_priority(fd, eci, DYN_PRIORITY);
>> +       __test_priority(fd, eci, DYN_PRIORITY | WAIT_MODE);
>> +}
>> +
>>  static void
>>  test_preempt_mode(int fd, struct drm_xe_engine_class_instance *eci,
>> int num_placement,
>>                   int n_exec_queues, int n_execs, unsigned int flags)
>> @@ -707,6 +906,10 @@ igt_main
>>                         xe_for_each_multi_queue_engine_class(class)
>>                                 test_exec_virtual(fd, gt, class);
>>  
>> +       igt_subtest_f("priority")
>> +               xe_for_each_multi_queue_engine(fd, hwe)
>> +                       test_priority(fd, hwe);
>> +
>>         for (const struct section *s = sections; s->name; s++) {
>>                 igt_subtest_f("one-queue-%s", s->name)
>>                         xe_for_each_multi_queue_engine(fd, hwe)
>

Re: [PATCH v2 15/19] tests/intel/xe_exec_multi_queue: Add priority test

[Summers, Stuart]

On Fri, 2025-12-05 at 10:23 -0800, Niranjana Vishwanathapura wrote:
> On Thu, Dec 04, 2025 at 01:53:26PM -0800, Summers, Stuart wrote:
> > On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> > > Validate intra queue group priority setting.
> > > Validate that a higher priority queue in a queue group
> > > can preempt the lower priority queue of the group.
> > > 
> > > During a queue switch, the currently running queue is
> > > always switched out without regard to its priority.
> > > The priority is only a factor in determining which
> > > other queue of the group will be scheduled in.
> > > 
> > > v2: Macro and variable rename (priyanka)
> > >     Remove simulation related code (Priyanka)
> > >     Remove hardcoding of number of bits.
> > >     Use BASE_ADDRESS macro for address (Sai)
> > > 
> > > Signed-off-by: Niranjana Vishwanathapura
> > > <niranjana.vishwanathapura@intel.com>
> > > Signed-off-by: Xin Wang <x.wang@intel.com>
> > > ---
> > >  tests/intel/xe_exec_multi_queue.c | 203
> > > ++++++++++++++++++++++++++++++
> > >  1 file changed, 203 insertions(+)
> > > 
> > > diff --git a/tests/intel/xe_exec_multi_queue.c
> > > b/tests/intel/xe_exec_multi_queue.c
> > > index df65ccafb..06e898a47 100644
> > > --- a/tests/intel/xe_exec_multi_queue.c
> > > +++ b/tests/intel/xe_exec_multi_queue.c
> > > @@ -13,15 +13,18 @@
> > >  
> > >  #include "igt.h"
> > >  #include "xe_drm.h"
> > > +#include "igt_core.h"
> > >  #include "lib/igt_syncobj.h"
> > >  
> > >  #include "xe/xe_ioctl.h"
> > >  #include "xe/xe_query.h"
> > > +#include "xe/xe_spin.h"
> > >  
> > >  #define XE_EXEC_QUEUE_PRIORITY_LOW     0
> > >  #define XE_EXEC_QUEUE_PRIORITY_NORMAL  1
> > >  #define XE_EXEC_QUEUE_PRIORITY_HIGH    2
> > >  #define XE_EXEC_QUEUE_NUM_PRIORITIES   3
> > > +#define
> > > XE_EXEC_QUEUE_PRIORITY_N       (XE_EXEC_QUEUE_NUM_PRIORITIES
> > > * 2 + 1)
> > >  
> > >  #define MAX_N_EXEC_QUEUES      64
> > >  
> > > @@ -33,6 +36,7 @@
> > >  #define INVALIDATE             (0x1 << 5)
> > >  #define FAULT_MODE             (0x1 << 6)
> > >  #define SMEM                   (0x1 << 7)
> > > +#define WAIT_MODE              (0x1 << 8)
> > >  
> > >  #define MAX_INSTANCE 9
> > >  
> > > @@ -212,6 +216,201 @@ test_sanity(int fd, int gt, int class)
> > >         __test_sanity(fd, gt, class, true);
> > >  }
> > >  
> > > +static void
> > > +__test_priority(int fd, struct drm_xe_engine_class_instance
> > > *eci,
> > > +               unsigned int flags)
> > > +{
> > > +#define USER_FENCE_VALUE       0xdeadbeefdeadbeefull
> > > +       struct drm_xe_sync sync = {
> > > +               .type = DRM_XE_SYNC_TYPE_USER_FENCE,
> > > +               .flags = DRM_XE_SYNC_FLAG_SIGNAL,
> > > +               .timeline_value = USER_FENCE_VALUE,
> > > +       };
> > > +       struct drm_xe_exec exec = {
> > > +               .num_batch_buffer = 1,
> > > +               .num_syncs = 1,
> > > +               .syncs = to_user_pointer(&sync),
> > > +       };
> > > +       uint64_t vm_sync = 0, addr = BASE_ADDRESS;
> > > +       uint32_t exec_queues[XE_EXEC_QUEUE_PRIORITY_N];
> > > +       struct xe_spin *spin[XE_EXEC_QUEUE_PRIORITY_N];
> > > +       uint32_t vm, num_queues, num_queue_priorities, bo = 0;
> > > +       uint32_t start_order[XE_EXEC_QUEUE_PRIORITY_N] = { 0 };
> > > +       int64_t fence_timeout = NSEC_PER_SEC;
> > > +       size_t bo_size;
> > > +       /*
> > > +        * Q1 - Q6 are used for the priority test.
> > > +        * Q Priority = id % 3
> > > +        *      QID     Q1 Q2 Q3 Q4 Q5 Q6
> > > +        * Priority      1  2  0  1  2  0
> > > +        * The Priority 1 and 0 are the same priority so hw
> > > should
> > > pick Q with priority: Q2, Q5, Q1, Q3, Q4, Q6
> > 
> > I think we should reword this to something like:
> > Hardware treats priority 0 and 1 the same, so hw should pick Q with
> > priority...
> 
> Ok, will update.
> 
> > 
> > > +        */
> > > +       int expect_order[] = {0,2,5,1,3,4,6};
> > > +       uint32_t already_in_order = 0;          // bitmask to
> > > record
> > > Q started info
> > > +       struct drm_xe_ext_set_property multi_queue = {
> > > +               .base.name =
> > > DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> > > +               .property =
> > > DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
> > > +               .value = DRM_XE_MULTI_GROUP_CREATE,
> > > +       };
> > > +       uint64_t ext = to_user_pointer(&multi_queue);
> > > +       int i, j, sleep_duration = 1;
> > > +       void *bo_map;
> > > +
> > > +       num_queue_priorities = XE_EXEC_QUEUE_NUM_PRIORITIES;
> > > +       num_queues = num_queue_priorities * 2 + 1;
> > > +       igt_assert(num_queues <= XE_EXEC_QUEUE_PRIORITY_N);
> > > +       igt_assert(num_queues <= sizeof(uint32_t) * 8);
> > > +
> > > +       igt_debug("%s flags 0x%x eci %d:%d:%d\n", __func__,
> > > flags,
> > > eci[0].gt_id,
> > > +                eci[0].engine_class, eci[0].engine_instance);
> > > +
> > > +       vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
> > > +       bo_size = xe_bb_size(fd, sizeof(*spin[0]) * num_queues);
> > > +
> > > +       bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd,
> > > eci[0].gt_id),
> > > +                        
> > > DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> > > +       bo_map = xe_bo_map(fd, bo, bo_size);
> > > +       for (i = 0; i < num_queues; i++)
> > > +               spin[i] = bo_map + i * sizeof(*spin[0]);
> > > +
> > > +       /* Use the default priority for Q0 because we are
> > > explicitly
> > > waiting for it below */
> > > +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> > > +       multi_queue.value = exec_queues[0];
> > > +
> > > +       if (flags & DYN_PRIORITY) {
> > > +               for (i = 1; i < num_queues; i++)
> > > +                       exec_queues[i] = xe_exec_queue_create(fd,
> > > vm,
> > > eci, ext);
> > > +       } else {
> > > +               struct drm_xe_ext_set_property mq_priority = {
> > > +                       .base.name =
> > > DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> > > +                       .property =
> > > DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> > > +               };
> > > +
> > > +               multi_queue.base.next_extension =
> > > to_user_pointer(&mq_priority);
> > > +
> > > +               /* Create secondary queues with increasing order
> > > of
> > > priority */
> > > +               for (i = 1; i < num_queues; i++) {
> > > +                       mq_priority.value = i %
> > > num_queue_priorities;
> > > +                       exec_queues[i] = xe_exec_queue_create(fd,
> > > vm,
> > > eci, ext);
> > > +               }
> > > +       }
> > > +
> > > +       sync.addr = to_user_pointer(&vm_sync);
> > > +       xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size, &sync,
> > > 1);
> > > +
> > > +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
> > > fence_timeout);
> > > +       vm_sync = 0;
> > > +
> > > +       for (i = 0; i < num_queues; i++) {
> > > +               uint64_t spin_addr = addr + i * sizeof(struct
> > > xe_spin);
> > > +
> > > +               xe_spin_init_opts(spin[i], .addr = spin_addr,
> > > .preempt = true);
> > > +               sync.addr = spin_addr + (char *)&spin[i]-
> > > >exec_sync -
> > > (char *)spin[i];
> > > +               exec.exec_queue_id = exec_queues[i];
> > > +               exec.address = spin_addr;
> > > +               xe_exec(fd, &exec);
> > > +
> > > +               /* Wait for job on Q0 to start, allow other
> > > queues to
> > > run to completion */
> > 
> > So in this case we aren't waiting for anything with the other
> > queues,
> > only Q0. We don't know if the other queues are sitting waiting for
> > Q0
> > to end (or the semaphore to clear) or not. Maybe:
> > /* Wait for job on Q0 to start, other queues block behind Q0 */
> > 
> 
> Ok, will update.
> 
> > > +               if (!i)
> > > +                       xe_spin_wait_started(spin[i]);
> > > +       }
> > > +
> > > +       sleep(sleep_duration);
> > > +
> > > +       /*
> > > +        * Expect the job on other queue to not get scheduled
> > > while
> > > the spinner
> > > +        * on q0 is not waiting on preempt condition.
> > > +        */
> > > +       for (i = 1; i < num_queues; i++)
> > > +               igt_assert(!xe_spin_started(spin[i]));
> > > +
> > > +       if (flags & DYN_PRIORITY) {
> > > +               /* Assign increasing order of priority for
> > > secondary
> > > queues */
> > > +               for (i = 1; i < num_queues; i++)
> > > +                       xe_exec_queue_set_property(fd,
> > > exec_queues[i],
> > > +                                                 
> > > DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY,
> > > +                                                  i %
> > > num_queue_priorities);
> > > +
> > > +               /* Wait for priorities to take effect */
> > > +               sleep(sleep_duration);
> > 
> > I'd really rather have a way to determine these are set
> > programmatically... What if we moved this whole if condition up
> > above
> > the xe_exec call to ensure the H2G ordering of the priority set
> > followed by the exec?
> > 
> 
> No, the idea here is to dynamically change the priority. i.e,
> after the job has been submitted to the HW.

Yeah that makes sense. I'm just worried this sleep won't cover all
cases. But I guess if it doesn't we should also see that in the results
below. That just puts the burden on the debugger if we hit some issue
here - to ensure the GuC wasn't overloaded from TLB invalidations or
something from a prior test and couldn't submit the priority change by
the time we do the spin end below.

We could add a new spinner on a different engine or something and wait
for that to start? This would ensure the same H2G ordering. But then
that gets pretty hacky and makes this test a lot more convoluted...

I guess what we have here works. I was trying to also see if there was
a better way we could comment this to suggest this kind of debug in the
future, but the fact that we just have the one sleep and the comment
you already have should hopefully be enough there.

Anyway, no problem with what you have for now. We can revisit if we do
end up hitting some issue here in the future.

> 
> > > +       }
> > > +
> > > +       /*
> > > +        * Trigger a queue switch by making the spinner on q0 to
> > > wait
> > > on preempt
> > > +        * condition, allowing job on q1 to get scheduled and
> > > finish.
> > > When we end
> > > +        * the spin[0], it triggers the CFEG to perform a queue
> > > priority arbitration
> > > +        * rather than a full context switch out. Consequently,
> > > in
> > > both semaphore
> > > +        * (WAIT_MODE) and non-semaphore scenarios, a priority
> > > check
> > > will occur.
> > > +        */
> > 
> > The CFEG arbitration points:
> > Semaphore wait successful/unsuccessful
> > - covered here
> > 
> > Head == Tail
> > - covered here in the spin_end below
> > 
> > Thread group end met in the walker
> > - expected to be covered by compute tests
> >   - of course the compute UMD tests should support these checks
> >   - I don't see us doing anything here in IGT though. Should we?
> > 
> > pipecontrol/barrier with queue drain mode set
> > - UMD is testing this I believe, but should we do that here also?
> > 
> 
> Yah, the idea here is to cover the arbitration cases that IGT
> can easily test for. Will leave UMD validation to cover the rest.

Sounds great.

> 
> > > +       if (flags & WAIT_MODE)
> > > +               xe_spin_preempt_wait(spin[0]);
> > > +       else
> > > +               xe_spin_end(spin[0]);
> > 
> > Do we want to wait for the spin end to take place before jumping to
> > the
> > next sequence in the test?
> > 
> 
> There is no added benefit in that.

And that's because we're already doing the wait user fence for the
secondary queues below? That makes sense then thanks.

> 
> > > +
> > > +       /* Wait for jobs to get scheduled */
> > > +       i = 1;
> > > +       while (i < num_queues) {
> > > +               for (j = 1; j < num_queues; j++) {
> > > +                       if (xe_spin_started(spin[j]) &&
> > > ((already_in_order & (1 << j)) == 0)) {
> > > +                               start_order[i] = j;
> > > +                               xe_spin_end(spin[j]);
> > > +                               xe_wait_ufence(fd, &spin[j]-
> > > > exec_sync, USER_FENCE_VALUE,
> > > +                                              exec_queues[j],
> > > fence_timeout);
> > > +                               already_in_order |= (1 << j);
> > > +                               i++;
> > > +                       }
> > > +               }
> > > +       }
> > > +
> > > +       /* While ending spinner on q0, bring it out of preempt
> > > wait
> > > */
> > > +       if (flags & WAIT_MODE) {
> > > +               xe_spin_end(spin[0]);
> > > +               xe_spin_preempt_nowait(spin[0]);
> > > +       }
> > > +       xe_wait_ufence(fd, &spin[0]->exec_sync, USER_FENCE_VALUE,
> > > exec_queues[0], fence_timeout);
> > > +
> > > +       igt_debug("Order\t Actual\t Expect\n");
> > > +       for (i = 1, j = 0; i < num_queues; i++) {
> > > +               igt_debug("  %d\t  Q%d(%d)\t  Q%d(%d)\n",i,
> > > start_order[i], start_order[i] % num_queue_priorities,
> > > +                         expect_order[i], expect_order[i] %
> > > num_queue_priorities);
> > > +
> > > +               /* The priority 0, 1 are the same, so we can skip
> > > the
> > > comparison */
> > > +               if (expect_order[i] % num_queue_priorities <
> > > XE_EXEC_QUEUE_PRIORITY_HIGH &&
> > > +                   start_order[i] % num_queue_priorities <
> > > XE_EXEC_QUEUE_PRIORITY_HIGH)
> > > +                       continue;
> > 
> > The downside to this approach is if we get some future hardware
> > that
> > has more than two priorities where more than two of these are the
> > same,
> > we'll need to rework this.
> > 
> 
> I think it should be one off thing and we shouldn't complicate the
> design for that.

Ok.

> 
> > > +
> > > +               if (start_order[i] % num_queue_priorities !=
> > > expect_order[i] % num_queue_priorities)
> > > +                       j++;
> > 
> > Instead of calling this 'j' can we use 'num_out_of_order' or
> > something
> > to be more specific?
> > 
> 
> Hmm...we already have 'j' which we can use. Let me added a comment
> here so that it becomes more readable.

Thanks, sounds great.

-Stuart

> 
> Niranjana
> 
> > Thanks,
> > Stuart
> > 
> > > +       }
> > > +       igt_assert(j == 0);
> > > +
> > > +       sync.addr = to_user_pointer(&vm_sync);
> > > +       xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, &sync,
> > > 1);
> > > +       xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
> > > fence_timeout);
> > > +
> > > +       for (i = 0; i < num_queues; i++)
> > > +               xe_exec_queue_destroy(fd, exec_queues[i]);
> > > +
> > > +       munmap(bo_map, bo_size);
> > > +       gem_close(fd, bo);
> > > +
> > > +       xe_vm_destroy(fd, vm);
> > > +}
> > > +
> > > +/**
> > > + * SUBTEST: priority
> > > + * Description: Validate queue priority setting
> > > + * Test category: functionality test
> > > + */
> > > +static void
> > > +test_priority(int fd, struct drm_xe_engine_class_instance *eci)
> > > +{
> > > +       __test_priority(fd, eci, 0);
> > > +       __test_priority(fd, eci, WAIT_MODE);
> > > +       __test_priority(fd, eci, DYN_PRIORITY);
> > > +       __test_priority(fd, eci, DYN_PRIORITY | WAIT_MODE);
> > > +}
> > > +
> > >  static void
> > >  test_preempt_mode(int fd, struct drm_xe_engine_class_instance
> > > *eci,
> > > int num_placement,
> > >                   int n_exec_queues, int n_execs, unsigned int
> > > flags)
> > > @@ -707,6 +906,10 @@ igt_main
> > >                         xe_for_each_multi_queue_engine_class(clas
> > > s)
> > >                                 test_exec_virtual(fd, gt, class);
> > >  
> > > +       igt_subtest_f("priority")
> > > +               xe_for_each_multi_queue_engine(fd, hwe)
> > > +                       test_priority(fd, hwe);
> > > +
> > >         for (const struct section *s = sections; s->name; s++) {
> > >                 igt_subtest_f("one-queue-%s", s->name)
> > >                         xe_for_each_multi_queue_engine(fd, hwe)
> > 

[PATCH v2 16/19] tests/intel/xe_exec_multi_queue: Add submission sanity test

[Niranjana Vishwanathapura]

Add sanity test involving exec submissions in multi queue group.

v2: Remove simulation related code (Priyanka)
    Use BASE_ADDRESS macro for address (Sai)

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 139 ++++++++++++++++++++++++++++++
 1 file changed, 139 insertions(+)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index 06e898a47..9f7b3b4d7 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -44,6 +44,9 @@
 
 #define BASE_ADDRESS	0x1a0000
 
+/* Number of queues in exec sanity tests */
+#define NUM_QUEUES		2
+
 static void
 __test_sanity(int fd, int gt, int class, bool preempt_mode)
 {
@@ -216,6 +219,138 @@ test_sanity(int fd, int gt, int class)
 	__test_sanity(fd, gt, class, true);
 }
 
+static void
+__test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci, unsigned int flags)
+{
+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
+	struct drm_xe_sync sync = { };
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(&sync),
+	};
+	uint64_t vm_sync = 0, addr[NUM_QUEUES];
+	uint32_t vm, exec_queues[NUM_QUEUES], bo[NUM_QUEUES];
+	int64_t fence_timeout = NSEC_PER_SEC;
+	struct xe_spin *spin[NUM_QUEUES];
+	size_t bo_size;
+	struct drm_xe_ext_set_property multi_queue = {
+		.base.name = DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
+		.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
+		.value = DRM_XE_MULTI_GROUP_CREATE,
+	};
+	uint64_t ext = to_user_pointer(&multi_queue);
+	bool preempt_mode = flags & PREEMPT_MODE;
+	int i;
+
+	sync.flags = DRM_XE_SYNC_FLAG_SIGNAL;
+	if (preempt_mode) {
+		sync.type = DRM_XE_SYNC_TYPE_USER_FENCE;
+		sync.timeline_value = USER_FENCE_VALUE;
+	} else {
+		sync.type = DRM_XE_SYNC_TYPE_SYNCOBJ;
+		sync.handle = syncobj_create(fd, 0);
+	}
+
+	vm = xe_vm_create(fd, preempt_mode ? DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
+	bo_size = xe_bb_size(fd, sizeof(struct xe_spin));
+
+	for (i = 0; i < NUM_QUEUES; i++) {
+		bo[i] = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
+				     DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
+		spin[i] = xe_bo_map(fd, bo[i], bo_size);
+		exec_queues[i] = xe_exec_queue_create(fd, vm, eci, ext);
+		if (i == 0)
+			multi_queue.value = exec_queues[i];
+
+		addr[i] = BASE_ADDRESS + i * bo_size;
+	}
+
+	if (preempt_mode)
+		sync.addr = to_user_pointer(&vm_sync);
+
+	for (i = 0; i < NUM_QUEUES; i++) {
+		xe_vm_bind_async(fd, vm, 0, bo[i], 0, addr[i], bo_size, &sync, 1);
+		if (preempt_mode) {
+			xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, fence_timeout);
+			vm_sync = 0;
+		} else {
+			igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL));
+			syncobj_reset(fd, &sync.handle, 1);
+		}
+	}
+
+	/* Validate job submission on secondary queue before primary queue */
+	for (i = 1; i >= 0; i--) {
+		xe_spin_init_opts(spin[i], .addr = addr[i]);
+		if (preempt_mode)
+			sync.addr = addr[i] + (char *)&spin[i]->exec_sync - (char *)spin[i];
+
+		exec.exec_queue_id = exec_queues[i];
+		exec.address = addr[i];
+		xe_exec(fd, &exec);
+		xe_spin_wait_started(spin[i]);
+		xe_spin_end(spin[i]);
+		if (preempt_mode) {
+			xe_wait_ufence(fd, &spin[i]->exec_sync, USER_FENCE_VALUE, exec_queues[i], fence_timeout);
+		} else {
+			igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL));
+			syncobj_reset(fd, &sync.handle, 1);
+		}
+	}
+
+	/* Destroy primary queue */
+	xe_exec_queue_destroy(fd, exec_queues[0]);
+
+	/* Validate submission on secondary queues fail after destroying the primary */
+	xe_spin_init_opts(spin[1], .addr = addr[1]);
+	if (preempt_mode)
+		sync.addr = addr[1] + (char *)&spin[1]->exec_sync - (char *)spin[1];
+
+	exec.exec_queue_id = exec_queues[1];
+	exec.address = addr[1];
+	igt_assert_eq(__xe_exec(fd, &exec), -ECANCELED);
+
+	if (preempt_mode)
+		sync.addr = to_user_pointer(&vm_sync);
+
+	for (i = 0; i < NUM_QUEUES; i++) {
+		xe_vm_unbind_async(fd, vm, 0, 0, addr[i], bo_size, &sync, 1);
+		if (preempt_mode) {
+			xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, fence_timeout);
+			vm_sync = 0;
+		} else {
+			igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL));
+			syncobj_reset(fd, &sync.handle, 1);
+		}
+	}
+
+	/* Destroy secondary queue */
+	xe_exec_queue_destroy(fd, exec_queues[1]);
+
+	for (i = 0; i < NUM_QUEUES; i++) {
+		munmap(spin[i], bo_size);
+		gem_close(fd, bo[i]);
+	}
+
+	if (!preempt_mode)
+		syncobj_destroy(fd, sync.handle);
+
+	xe_vm_destroy(fd, vm);
+}
+
+/**
+ * SUBTEST: exec-sanity
+ * Description: Run exec submission sanity tests
+ * Test category: functionality test
+ */
+static void
+test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci)
+{
+	__test_exec_sanity(fd, eci, 0);
+	__test_exec_sanity(fd, eci, PREEMPT_MODE);
+}
+
 static void
 __test_priority(int fd, struct drm_xe_engine_class_instance *eci,
 		unsigned int flags)
@@ -901,6 +1036,10 @@ igt_main
 			xe_for_each_multi_queue_engine_class(class)
 				test_sanity(fd, gt, class);
 
+	igt_subtest_f("exec-sanity")
+		xe_for_each_multi_queue_engine(fd, hwe)
+			test_exec_sanity(fd, hwe);
+
 	igt_subtest_f("virtual")
 		xe_for_each_gt(fd, gt)
 			xe_for_each_multi_queue_engine_class(class)
-- 
2.43.0

RE: [PATCH v2 16/19] tests/intel/xe_exec_multi_queue: Add submission sanity test

[Ch, Sai Gowtham]

>-----Original Message-----
>From: Vishwanathapura, Niranjana <niranjana.vishwanathapura@intel.com>
>Sent: Friday, November 21, 2025 9:27 AM
>To: igt-dev@lists.freedesktop.org
>Cc: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>; Dandamudi, Priyanka
><priyanka.dandamudi@intel.com>; kamil.konieczny@linux.intel.com
>Subject: [PATCH v2 16/19] tests/intel/xe_exec_multi_queue: Add submission
>sanity test
>
>Add sanity test involving exec submissions in multi queue group.
>
>v2: Remove simulation related code (Priyanka)
>    Use BASE_ADDRESS macro for address (Sai)
>
>Signed-off-by: Niranjana Vishwanathapura
><niranjana.vishwanathapura@intel.com>
>---
> tests/intel/xe_exec_multi_queue.c | 139
>++++++++++++++++++++++++++++++
> 1 file changed, 139 insertions(+)
>
>diff --git a/tests/intel/xe_exec_multi_queue.c
>b/tests/intel/xe_exec_multi_queue.c
>index 06e898a47..9f7b3b4d7 100644
>--- a/tests/intel/xe_exec_multi_queue.c
>+++ b/tests/intel/xe_exec_multi_queue.c
>@@ -44,6 +44,9 @@
>
> #define BASE_ADDRESS	0x1a0000
>
>+/* Number of queues in exec sanity tests */
>+#define NUM_QUEUES		2
>+
> static void
> __test_sanity(int fd, int gt, int class, bool preempt_mode)  { @@ -216,6
>+219,138 @@ test_sanity(int fd, int gt, int class)
> 	__test_sanity(fd, gt, class, true);
> }
>
>+static void
>+__test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci,
>+unsigned int flags) {
>+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
>+	struct drm_xe_sync sync = { };
>+	struct drm_xe_exec exec = {
>+		.num_batch_buffer = 1,
>+		.num_syncs = 1,
>+		.syncs = to_user_pointer(&sync),
>+	};
>+	uint64_t vm_sync = 0, addr[NUM_QUEUES];
>+	uint32_t vm, exec_queues[NUM_QUEUES], bo[NUM_QUEUES];
>+	int64_t fence_timeout = NSEC_PER_SEC;
>+	struct xe_spin *spin[NUM_QUEUES];
>+	size_t bo_size;
>+	struct drm_xe_ext_set_property multi_queue = {
>+		.base.name =
>DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
>+		.property =
>DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
>+		.value = DRM_XE_MULTI_GROUP_CREATE,
>+	};
>+	uint64_t ext = to_user_pointer(&multi_queue);
>+	bool preempt_mode = flags & PREEMPT_MODE;
>+	int i;
>+
>+	sync.flags = DRM_XE_SYNC_FLAG_SIGNAL;
>+	if (preempt_mode) {
>+		sync.type = DRM_XE_SYNC_TYPE_USER_FENCE;
>+		sync.timeline_value = USER_FENCE_VALUE;
>+	} else {
>+		sync.type = DRM_XE_SYNC_TYPE_SYNCOBJ;
>+		sync.handle = syncobj_create(fd, 0);
>+	}
>+
>+	vm = xe_vm_create(fd, preempt_mode ?
>DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
>+	bo_size = xe_bb_size(fd, sizeof(struct xe_spin));
>+
>+	for (i = 0; i < NUM_QUEUES; i++) {
>+		bo[i] = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd,
>eci[0].gt_id),
>+
>DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>+		spin[i] = xe_bo_map(fd, bo[i], bo_size);
>+		exec_queues[i] = xe_exec_queue_create(fd, vm, eci, ext);
>+		if (i == 0)
>+			multi_queue.value = exec_queues[i];
>+
>+		addr[i] = BASE_ADDRESS + i * bo_size;
>+	}
>+
>+	if (preempt_mode)
>+		sync.addr = to_user_pointer(&vm_sync);
>+
>+	for (i = 0; i < NUM_QUEUES; i++) {
>+		xe_vm_bind_async(fd, vm, 0, bo[i], 0, addr[i], bo_size, &sync,
>1);
>+		if (preempt_mode) {
>+			xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
>fence_timeout);
>+			vm_sync = 0;
>+		} else {
>+			igt_assert(syncobj_wait(fd, &sync.handle, 1,
>INT64_MAX, 0, NULL));
>+			syncobj_reset(fd, &sync.handle, 1);
>+		}
>+	}
>+
>+	/* Validate job submission on secondary queue before primary queue
>*/
>+	for (i = 1; i >= 0; i--) {
>+		xe_spin_init_opts(spin[i], .addr = addr[i]);
>+		if (preempt_mode)
>+			sync.addr = addr[i] + (char *)&spin[i]->exec_sync -
>(char *)spin[i];
>+
>+		exec.exec_queue_id = exec_queues[i];
>+		exec.address = addr[i];
>+		xe_exec(fd, &exec);
>+		xe_spin_wait_started(spin[i]);
>+		xe_spin_end(spin[i]);
>+		if (preempt_mode) {
>+			xe_wait_ufence(fd, &spin[i]->exec_sync,
>USER_FENCE_VALUE, exec_queues[i], fence_timeout);
>+		} else {
>+			igt_assert(syncobj_wait(fd, &sync.handle, 1,
>INT64_MAX, 0, NULL));
>+			syncobj_reset(fd, &sync.handle, 1);
>+		}
>+	}
>+
>+	/* Destroy primary queue */
>+	xe_exec_queue_destroy(fd, exec_queues[0]);
>+
>+	/* Validate submission on secondary queues fail after destroying the
>primary */
>+	xe_spin_init_opts(spin[1], .addr = addr[1]);
>+	if (preempt_mode)
>+		sync.addr = addr[1] + (char *)&spin[1]->exec_sync - (char
>*)spin[1];
>+
>+	exec.exec_queue_id = exec_queues[1];
>+	exec.address = addr[1];
>+	igt_assert_eq(__xe_exec(fd, &exec), -ECANCELED);
>+
>+	if (preempt_mode)
>+		sync.addr = to_user_pointer(&vm_sync);
>+
>+	for (i = 0; i < NUM_QUEUES; i++) {
>+		xe_vm_unbind_async(fd, vm, 0, 0, addr[i], bo_size, &sync, 1);
>+		if (preempt_mode) {
>+			xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0,
>fence_timeout);
>+			vm_sync = 0;
>+		} else {
>+			igt_assert(syncobj_wait(fd, &sync.handle, 1,
>INT64_MAX, 0, NULL));
>+			syncobj_reset(fd, &sync.handle, 1);
>+		}
>+	}
>+
>+	/* Destroy secondary queue */
>+	xe_exec_queue_destroy(fd, exec_queues[1]);
>+
>+	for (i = 0; i < NUM_QUEUES; i++) {
>+		munmap(spin[i], bo_size);
>+		gem_close(fd, bo[i]);
>+	}
>+
>+	if (!preempt_mode)
>+		syncobj_destroy(fd, sync.handle);
>+
>+	xe_vm_destroy(fd, vm);
>+}
>+
>+/**
>+ * SUBTEST: exec-sanity
>+ * Description: Run exec submission sanity tests
>+ * Test category: functionality test
>+ */
>+static void
>+test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci) {
>+	__test_exec_sanity(fd, eci, 0);
>+	__test_exec_sanity(fd, eci, PREEMPT_MODE); }
>+
> static void
> __test_priority(int fd, struct drm_xe_engine_class_instance *eci,
> 		unsigned int flags)
>@@ -901,6 +1036,10 @@ igt_main
> 			xe_for_each_multi_queue_engine_class(class)
> 				test_sanity(fd, gt, class);
>
>+	igt_subtest_f("exec-sanity")
>+		xe_for_each_multi_queue_engine(fd, hwe)
>+			test_exec_sanity(fd, hwe);
>+
LGTM
Reviewed-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 	igt_subtest_f("virtual")
> 		xe_for_each_gt(fd, gt)
> 			xe_for_each_multi_queue_engine_class(class)
>--
>2.43.0

Re: [PATCH v2 16/19] tests/intel/xe_exec_multi_queue: Add submission sanity test

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Add sanity test involving exec submissions in multi queue group.
> 
> v2: Remove simulation related code (Priyanka)
>     Use BASE_ADDRESS macro for address (Sai)
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> ---
>  tests/intel/xe_exec_multi_queue.c | 139
> ++++++++++++++++++++++++++++++
>  1 file changed, 139 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index 06e898a47..9f7b3b4d7 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -44,6 +44,9 @@
>  
>  #define BASE_ADDRESS   0x1a0000
>  
> +/* Number of queues in exec sanity tests */
> +#define NUM_QUEUES             2
> +
>  static void
>  __test_sanity(int fd, int gt, int class, bool preempt_mode)
>  {
> @@ -216,6 +219,138 @@ test_sanity(int fd, int gt, int class)
>         __test_sanity(fd, gt, class, true);
>  }
>  
> +static void
> +__test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci,
> unsigned int flags)
> +{
> +#define USER_FENCE_VALUE       0xdeadbeefdeadbeefull
> +       struct drm_xe_sync sync = { };
> +       struct drm_xe_exec exec = {
> +               .num_batch_buffer = 1,
> +               .num_syncs = 1,
> +               .syncs = to_user_pointer(&sync),
> +       };
> +       uint64_t vm_sync = 0, addr[NUM_QUEUES];
> +       uint32_t vm, exec_queues[NUM_QUEUES], bo[NUM_QUEUES];
> +       int64_t fence_timeout = NSEC_PER_SEC;
> +       struct xe_spin *spin[NUM_QUEUES];
> +       size_t bo_size;
> +       struct drm_xe_ext_set_property multi_queue = {
> +               .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> +               .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
> +               .value = DRM_XE_MULTI_GROUP_CREATE,
> +       };
> +       uint64_t ext = to_user_pointer(&multi_queue);
> +       bool preempt_mode = flags & PREEMPT_MODE;
> +       int i;
> +
> +       sync.flags = DRM_XE_SYNC_FLAG_SIGNAL;
> +       if (preempt_mode) {
> +               sync.type = DRM_XE_SYNC_TYPE_USER_FENCE;
> +               sync.timeline_value = USER_FENCE_VALUE;
> +       } else {
> +               sync.type = DRM_XE_SYNC_TYPE_SYNCOBJ;
> +               sync.handle = syncobj_create(fd, 0);
> +       }
> +
> +       vm = xe_vm_create(fd, preempt_mode ?
> DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
> +       bo_size = xe_bb_size(fd, sizeof(struct xe_spin));
> +
> +       for (i = 0; i < NUM_QUEUES; i++) {
> +               bo[i] = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> +                                   
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +               spin[i] = xe_bo_map(fd, bo[i], bo_size);
> +               exec_queues[i] = xe_exec_queue_create(fd, vm, eci,
> ext);
> +               if (i == 0)
> +                       multi_queue.value = exec_queues[i];
> +
> +               addr[i] = BASE_ADDRESS + i * bo_size;
> +       }
> +
> +       if (preempt_mode)
> +               sync.addr = to_user_pointer(&vm_sync);
> +
> +       for (i = 0; i < NUM_QUEUES; i++) {
> +               xe_vm_bind_async(fd, vm, 0, bo[i], 0, addr[i],
> bo_size, &sync, 1);
> +               if (preempt_mode) {
> +                       xe_wait_ufence(fd, &vm_sync,
> USER_FENCE_VALUE, 0, fence_timeout);
> +                       vm_sync = 0;
> +               } else {
> +                       igt_assert(syncobj_wait(fd, &sync.handle, 1,
> INT64_MAX, 0, NULL));
> +                       syncobj_reset(fd, &sync.handle, 1);
> +               }
> +       }
> +
> +       /* Validate job submission on secondary queue before primary
> queue */
> +       for (i = 1; i >= 0; i--) {

for i = NUM_QUEUES = 1

In case we ever need to increase this?

Looks good otherwise:
Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> +               xe_spin_init_opts(spin[i], .addr = addr[i]);
> +               if (preempt_mode)
> +                       sync.addr = addr[i] + (char *)&spin[i]-
> >exec_sync - (char *)spin[i];
> +
> +               exec.exec_queue_id = exec_queues[i];
> +               exec.address = addr[i];
> +               xe_exec(fd, &exec);
> +               xe_spin_wait_started(spin[i]);
> +               xe_spin_end(spin[i]);
> +               if (preempt_mode) {
> +                       xe_wait_ufence(fd, &spin[i]->exec_sync,
> USER_FENCE_VALUE, exec_queues[i], fence_timeout);
> +               } else {
> +                       igt_assert(syncobj_wait(fd, &sync.handle, 1,
> INT64_MAX, 0, NULL));
> +                       syncobj_reset(fd, &sync.handle, 1);
> +               }
> +       }
> +
> +       /* Destroy primary queue */
> +       xe_exec_queue_destroy(fd, exec_queues[0]);
> +
> +       /* Validate submission on secondary queues fail after
> destroying the primary */
> +       xe_spin_init_opts(spin[1], .addr = addr[1]);
> +       if (preempt_mode)
> +               sync.addr = addr[1] + (char *)&spin[1]->exec_sync -
> (char *)spin[1];
> +
> +       exec.exec_queue_id = exec_queues[1];
> +       exec.address = addr[1];
> +       igt_assert_eq(__xe_exec(fd, &exec), -ECANCELED);
> +
> +       if (preempt_mode)
> +               sync.addr = to_user_pointer(&vm_sync);
> +
> +       for (i = 0; i < NUM_QUEUES; i++) {
> +               xe_vm_unbind_async(fd, vm, 0, 0, addr[i], bo_size,
> &sync, 1);
> +               if (preempt_mode) {
> +                       xe_wait_ufence(fd, &vm_sync,
> USER_FENCE_VALUE, 0, fence_timeout);
> +                       vm_sync = 0;
> +               } else {
> +                       igt_assert(syncobj_wait(fd, &sync.handle, 1,
> INT64_MAX, 0, NULL));
> +                       syncobj_reset(fd, &sync.handle, 1);
> +               }
> +       }
> +
> +       /* Destroy secondary queue */
> +       xe_exec_queue_destroy(fd, exec_queues[1]);
> +
> +       for (i = 0; i < NUM_QUEUES; i++) {
> +               munmap(spin[i], bo_size);
> +               gem_close(fd, bo[i]);
> +       }
> +
> +       if (!preempt_mode)
> +               syncobj_destroy(fd, sync.handle);
> +
> +       xe_vm_destroy(fd, vm);
> +}
> +
> +/**
> + * SUBTEST: exec-sanity
> + * Description: Run exec submission sanity tests
> + * Test category: functionality test
> + */
> +static void
> +test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci)
> +{
> +       __test_exec_sanity(fd, eci, 0);
> +       __test_exec_sanity(fd, eci, PREEMPT_MODE);
> +}
> +
>  static void
>  __test_priority(int fd, struct drm_xe_engine_class_instance *eci,
>                 unsigned int flags)
> @@ -901,6 +1036,10 @@ igt_main
>                         xe_for_each_multi_queue_engine_class(class)
>                                 test_sanity(fd, gt, class);
>  
> +       igt_subtest_f("exec-sanity")
> +               xe_for_each_multi_queue_engine(fd, hwe)
> +                       test_exec_sanity(fd, hwe);
> +
>         igt_subtest_f("virtual")
>                 xe_for_each_gt(fd, gt)
>                         xe_for_each_multi_queue_engine_class(class)

Re: [PATCH v2 16/19] tests/intel/xe_exec_multi_queue: Add submission sanity test

[Niranjana Vishwanathapura]

On Thu, Dec 04, 2025 at 01:08:06PM -0800, Summers, Stuart wrote:
>On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
>> Add sanity test involving exec submissions in multi queue group.
>>
>> v2: Remove simulation related code (Priyanka)
>>     Use BASE_ADDRESS macro for address (Sai)
>>
>> Signed-off-by: Niranjana Vishwanathapura
>> <niranjana.vishwanathapura@intel.com>
>> ---
>>  tests/intel/xe_exec_multi_queue.c | 139
>> ++++++++++++++++++++++++++++++
>>  1 file changed, 139 insertions(+)
>>
>> diff --git a/tests/intel/xe_exec_multi_queue.c
>> b/tests/intel/xe_exec_multi_queue.c
>> index 06e898a47..9f7b3b4d7 100644
>> --- a/tests/intel/xe_exec_multi_queue.c
>> +++ b/tests/intel/xe_exec_multi_queue.c
>> @@ -44,6 +44,9 @@
>>  
>>  #define BASE_ADDRESS   0x1a0000
>>  
>> +/* Number of queues in exec sanity tests */
>> +#define NUM_QUEUES             2
>> +
>>  static void
>>  __test_sanity(int fd, int gt, int class, bool preempt_mode)
>>  {
>> @@ -216,6 +219,138 @@ test_sanity(int fd, int gt, int class)
>>         __test_sanity(fd, gt, class, true);
>>  }
>>  
>> +static void
>> +__test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci,
>> unsigned int flags)
>> +{
>> +#define USER_FENCE_VALUE       0xdeadbeefdeadbeefull
>> +       struct drm_xe_sync sync = { };
>> +       struct drm_xe_exec exec = {
>> +               .num_batch_buffer = 1,
>> +               .num_syncs = 1,
>> +               .syncs = to_user_pointer(&sync),
>> +       };
>> +       uint64_t vm_sync = 0, addr[NUM_QUEUES];
>> +       uint32_t vm, exec_queues[NUM_QUEUES], bo[NUM_QUEUES];
>> +       int64_t fence_timeout = NSEC_PER_SEC;
>> +       struct xe_spin *spin[NUM_QUEUES];
>> +       size_t bo_size;
>> +       struct drm_xe_ext_set_property multi_queue = {
>> +               .base.name =
>> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
>> +               .property =
>> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
>> +               .value = DRM_XE_MULTI_GROUP_CREATE,
>> +       };
>> +       uint64_t ext = to_user_pointer(&multi_queue);
>> +       bool preempt_mode = flags & PREEMPT_MODE;
>> +       int i;
>> +
>> +       sync.flags = DRM_XE_SYNC_FLAG_SIGNAL;
>> +       if (preempt_mode) {
>> +               sync.type = DRM_XE_SYNC_TYPE_USER_FENCE;
>> +               sync.timeline_value = USER_FENCE_VALUE;
>> +       } else {
>> +               sync.type = DRM_XE_SYNC_TYPE_SYNCOBJ;
>> +               sync.handle = syncobj_create(fd, 0);
>> +       }
>> +
>> +       vm = xe_vm_create(fd, preempt_mode ?
>> DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
>> +       bo_size = xe_bb_size(fd, sizeof(struct xe_spin));
>> +
>> +       for (i = 0; i < NUM_QUEUES; i++) {
>> +               bo[i] = xe_bo_create(fd, vm, bo_size,
>> vram_if_possible(fd, eci[0].gt_id),
>> +                                   
>> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>> +               spin[i] = xe_bo_map(fd, bo[i], bo_size);
>> +               exec_queues[i] = xe_exec_queue_create(fd, vm, eci,
>> ext);
>> +               if (i == 0)
>> +                       multi_queue.value = exec_queues[i];
>> +
>> +               addr[i] = BASE_ADDRESS + i * bo_size;
>> +       }
>> +
>> +       if (preempt_mode)
>> +               sync.addr = to_user_pointer(&vm_sync);
>> +
>> +       for (i = 0; i < NUM_QUEUES; i++) {
>> +               xe_vm_bind_async(fd, vm, 0, bo[i], 0, addr[i],
>> bo_size, &sync, 1);
>> +               if (preempt_mode) {
>> +                       xe_wait_ufence(fd, &vm_sync,
>> USER_FENCE_VALUE, 0, fence_timeout);
>> +                       vm_sync = 0;
>> +               } else {
>> +                       igt_assert(syncobj_wait(fd, &sync.handle, 1,
>> INT64_MAX, 0, NULL));
>> +                       syncobj_reset(fd, &sync.handle, 1);
>> +               }
>> +       }
>> +
>> +       /* Validate job submission on secondary queue before primary
>> queue */
>> +       for (i = 1; i >= 0; i--) {
>
>for i = NUM_QUEUES = 1
>
>In case we ever need to increase this?
>

Yah, will fix.

Niranjana

>Looks good otherwise:
>Reviewed-by: Stuart Summers <stuart.summers@intel.com>
>
>> +               xe_spin_init_opts(spin[i], .addr = addr[i]);
>> +               if (preempt_mode)
>> +                       sync.addr = addr[i] + (char *)&spin[i]-
>> >exec_sync - (char *)spin[i];
>> +
>> +               exec.exec_queue_id = exec_queues[i];
>> +               exec.address = addr[i];
>> +               xe_exec(fd, &exec);
>> +               xe_spin_wait_started(spin[i]);
>> +               xe_spin_end(spin[i]);
>> +               if (preempt_mode) {
>> +                       xe_wait_ufence(fd, &spin[i]->exec_sync,
>> USER_FENCE_VALUE, exec_queues[i], fence_timeout);
>> +               } else {
>> +                       igt_assert(syncobj_wait(fd, &sync.handle, 1,
>> INT64_MAX, 0, NULL));
>> +                       syncobj_reset(fd, &sync.handle, 1);
>> +               }
>> +       }
>> +
>> +       /* Destroy primary queue */
>> +       xe_exec_queue_destroy(fd, exec_queues[0]);
>> +
>> +       /* Validate submission on secondary queues fail after
>> destroying the primary */
>> +       xe_spin_init_opts(spin[1], .addr = addr[1]);
>> +       if (preempt_mode)
>> +               sync.addr = addr[1] + (char *)&spin[1]->exec_sync -
>> (char *)spin[1];
>> +
>> +       exec.exec_queue_id = exec_queues[1];
>> +       exec.address = addr[1];
>> +       igt_assert_eq(__xe_exec(fd, &exec), -ECANCELED);
>> +
>> +       if (preempt_mode)
>> +               sync.addr = to_user_pointer(&vm_sync);
>> +
>> +       for (i = 0; i < NUM_QUEUES; i++) {
>> +               xe_vm_unbind_async(fd, vm, 0, 0, addr[i], bo_size,
>> &sync, 1);
>> +               if (preempt_mode) {
>> +                       xe_wait_ufence(fd, &vm_sync,
>> USER_FENCE_VALUE, 0, fence_timeout);
>> +                       vm_sync = 0;
>> +               } else {
>> +                       igt_assert(syncobj_wait(fd, &sync.handle, 1,
>> INT64_MAX, 0, NULL));
>> +                       syncobj_reset(fd, &sync.handle, 1);
>> +               }
>> +       }
>> +
>> +       /* Destroy secondary queue */
>> +       xe_exec_queue_destroy(fd, exec_queues[1]);
>> +
>> +       for (i = 0; i < NUM_QUEUES; i++) {
>> +               munmap(spin[i], bo_size);
>> +               gem_close(fd, bo[i]);
>> +       }
>> +
>> +       if (!preempt_mode)
>> +               syncobj_destroy(fd, sync.handle);
>> +
>> +       xe_vm_destroy(fd, vm);
>> +}
>> +
>> +/**
>> + * SUBTEST: exec-sanity
>> + * Description: Run exec submission sanity tests
>> + * Test category: functionality test
>> + */
>> +static void
>> +test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci)
>> +{
>> +       __test_exec_sanity(fd, eci, 0);
>> +       __test_exec_sanity(fd, eci, PREEMPT_MODE);
>> +}
>> +
>>  static void
>>  __test_priority(int fd, struct drm_xe_engine_class_instance *eci,
>>                 unsigned int flags)
>> @@ -901,6 +1036,10 @@ igt_main
>>                         xe_for_each_multi_queue_engine_class(class)
>>                                 test_sanity(fd, gt, class);
>>  
>> +       igt_subtest_f("exec-sanity")
>> +               xe_for_each_multi_queue_engine(fd, hwe)
>> +                       test_exec_sanity(fd, hwe);
>> +
>>         igt_subtest_f("virtual")
>>                 xe_for_each_gt(fd, gt)
>>                         xe_for_each_multi_queue_engine_class(class)
>

[PATCH v2 17/19] tests/intel/xe_exec_multi_queue: Sanity test KEEP_ACTIVE flag

[Niranjana Vishwanathapura]

Add DRM_XE_MULTI_GROUP_KEEP_ACTIVE to valid flags list.
Validate that KEEP_ACTIVE is not supported in preempt mode
unless fault mode is set.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 31 +++++++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index 9f7b3b4d7..288ef9ed8 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -37,10 +37,12 @@
 #define FAULT_MODE		(0x1 << 6)
 #define SMEM			(0x1 << 7)
 #define WAIT_MODE		(0x1 << 8)
+#define KEEP_ACTIVE		(0x1 << 9)
 
 #define MAX_INSTANCE 9
 
-#define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE)
+#define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE |        \
+				      DRM_XE_MULTI_GROUP_KEEP_ACTIVE)
 
 #define BASE_ADDRESS	0x1a0000
 
@@ -81,7 +83,8 @@ __test_sanity(int fd, int gt, int class, bool preempt_mode)
 	if (!n)
 		return;
 
-	vm = xe_vm_create(fd, preempt_mode ? DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
+	vm = xe_vm_create(fd, preempt_mode ? DRM_XE_VM_CREATE_FLAG_LR_MODE |
+			  DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0, 0);
 
 	/* Invalid flags */
 	while (!invalid_flag)
@@ -105,6 +108,15 @@ __test_sanity(int fd, int gt, int class, bool preempt_mode)
 	multi_queue.base.next_extension = to_user_pointer(&multi_queue);
 	igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext, &val), -EINVAL);
 
+	/* KEEP_ACTIVE not supported in preempt mode without fault_mode */
+	if (preempt_mode) {
+		vm2 = xe_vm_create(fd, preempt_mode ? DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
+		multi_queue.value |= DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
+		igt_assert_eq(__xe_exec_queue_create(fd, vm2, 1, 1, eci, ext, &val), -EINVAL);
+		multi_queue.value &= ~DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
+		xe_vm_destroy(fd, vm2);
+	}
+
 	/* Setting other queue properties are valid for Q0 */
 	multi_queue.base.next_extension = to_user_pointer(&priority);
 	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
@@ -205,6 +217,21 @@ __test_sanity(int fd, int gt, int class, bool preempt_mode)
 	igt_waitchildren();
 
 	xe_vm_destroy(fd, vm);
+
+	/* Validate closing FD while keeping group active */
+	fd = drm_open_driver(DRIVER_XE);
+	vm = xe_vm_create(fd, preempt_mode ? DRM_XE_VM_CREATE_FLAG_LR_MODE |
+			  DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0, 0);
+
+	multi_queue.value = DRM_XE_MULTI_GROUP_CREATE | DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
+	multi_queue.base.next_extension = 0;
+	exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
+
+	multi_queue.value = exec_queues[0];
+	for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
+		exec_queues[i] = xe_exec_queue_create(fd, vm, eci, ext);
+
+	drm_close_driver(fd);
 }
 
 /**
-- 
2.43.0

Re: [PATCH v2 17/19] tests/intel/xe_exec_multi_queue: Sanity test KEEP_ACTIVE flag

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Add DRM_XE_MULTI_GROUP_KEEP_ACTIVE to valid flags list.
> Validate that KEEP_ACTIVE is not supported in preempt mode
> unless fault mode is set.
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
> ---
>  tests/intel/xe_exec_multi_queue.c | 31
> +++++++++++++++++++++++++++++--
>  1 file changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index 9f7b3b4d7..288ef9ed8 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -37,10 +37,12 @@
>  #define FAULT_MODE             (0x1 << 6)
>  #define SMEM                   (0x1 << 7)
>  #define WAIT_MODE              (0x1 << 8)
> +#define KEEP_ACTIVE            (0x1 << 9)
>  
>  #define MAX_INSTANCE 9
>  
> -#define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE)
> +#define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE
> |        \
> +                                     DRM_XE_MULTI_GROUP_KEEP_ACTIVE)
>  
>  #define BASE_ADDRESS   0x1a0000
>  
> @@ -81,7 +83,8 @@ __test_sanity(int fd, int gt, int class, bool
> preempt_mode)
>         if (!n)
>                 return;
>  
> -       vm = xe_vm_create(fd, preempt_mode ?
> DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
> +       vm = xe_vm_create(fd, preempt_mode ?
> DRM_XE_VM_CREATE_FLAG_LR_MODE |
> +                         DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0, 0);
>  
>         /* Invalid flags */
>         while (!invalid_flag)
> @@ -105,6 +108,15 @@ __test_sanity(int fd, int gt, int class, bool
> preempt_mode)
>         multi_queue.base.next_extension =
> to_user_pointer(&multi_queue);
>         igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
> &val), -EINVAL);
>  
> +       /* KEEP_ACTIVE not supported in preempt mode without
> fault_mode */
> +       if (preempt_mode) {
> +               vm2 = xe_vm_create(fd, preempt_mode ?
> DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);

Since we're checking preempt_mode explicitly in the if condition above,
do we need to keep that here?

Functionally all looks good though.

Thanks,
Stuart

> +               multi_queue.value |= DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
> +               igt_assert_eq(__xe_exec_queue_create(fd, vm2, 1, 1,
> eci, ext, &val), -EINVAL);
> +               multi_queue.value &= ~DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
> +               xe_vm_destroy(fd, vm2);
> +       }
> +
>         /* Setting other queue properties are valid for Q0 */
>         multi_queue.base.next_extension = to_user_pointer(&priority);
>         exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> @@ -205,6 +217,21 @@ __test_sanity(int fd, int gt, int class, bool
> preempt_mode)
>         igt_waitchildren();
>  
>         xe_vm_destroy(fd, vm);
> +
> +       /* Validate closing FD while keeping group active */
> +       fd = drm_open_driver(DRIVER_XE);
> +       vm = xe_vm_create(fd, preempt_mode ?
> DRM_XE_VM_CREATE_FLAG_LR_MODE |
> +                         DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0, 0);
> +
> +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE |
> DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
> +       multi_queue.base.next_extension = 0;
> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
> +
> +       multi_queue.value = exec_queues[0];
> +       for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
> +               exec_queues[i] = xe_exec_queue_create(fd, vm, eci,
> ext);
> +
> +       drm_close_driver(fd);
>  }
>  
>  /**

Re: [PATCH v2 17/19] tests/intel/xe_exec_multi_queue: Sanity test KEEP_ACTIVE flag

[Niranjana Vishwanathapura]

On Thu, Dec 04, 2025 at 01:10:38PM -0800, Summers, Stuart wrote:
>On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
>> Add DRM_XE_MULTI_GROUP_KEEP_ACTIVE to valid flags list.
>> Validate that KEEP_ACTIVE is not supported in preempt mode
>> unless fault mode is set.
>>
>> Signed-off-by: Niranjana Vishwanathapura
>> <niranjana.vishwanathapura@intel.com>
>> ---
>>  tests/intel/xe_exec_multi_queue.c | 31
>> +++++++++++++++++++++++++++++--
>>  1 file changed, 29 insertions(+), 2 deletions(-)
>>
>> diff --git a/tests/intel/xe_exec_multi_queue.c
>> b/tests/intel/xe_exec_multi_queue.c
>> index 9f7b3b4d7..288ef9ed8 100644
>> --- a/tests/intel/xe_exec_multi_queue.c
>> +++ b/tests/intel/xe_exec_multi_queue.c
>> @@ -37,10 +37,12 @@
>>  #define FAULT_MODE             (0x1 << 6)
>>  #define SMEM                   (0x1 << 7)
>>  #define WAIT_MODE              (0x1 << 8)
>> +#define KEEP_ACTIVE            (0x1 << 9)
>>  
>>  #define MAX_INSTANCE 9
>>  
>> -#define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE)
>> +#define XE_MULTI_GROUP_VALID_FLAGS   (DRM_XE_MULTI_GROUP_CREATE
>> |        \
>> +                                     DRM_XE_MULTI_GROUP_KEEP_ACTIVE)
>>  
>>  #define BASE_ADDRESS   0x1a0000
>>  
>> @@ -81,7 +83,8 @@ __test_sanity(int fd, int gt, int class, bool
>> preempt_mode)
>>         if (!n)
>>                 return;
>>  
>> -       vm = xe_vm_create(fd, preempt_mode ?
>> DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
>> +       vm = xe_vm_create(fd, preempt_mode ?
>> DRM_XE_VM_CREATE_FLAG_LR_MODE |
>> +                         DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0, 0);
>>  
>>         /* Invalid flags */
>>         while (!invalid_flag)
>> @@ -105,6 +108,15 @@ __test_sanity(int fd, int gt, int class, bool
>> preempt_mode)
>>         multi_queue.base.next_extension =
>> to_user_pointer(&multi_queue);
>>         igt_assert_eq(__xe_exec_queue_create(fd, vm, 1, 1, eci, ext,
>> &val), -EINVAL);
>>  
>> +       /* KEEP_ACTIVE not supported in preempt mode without
>> fault_mode */
>> +       if (preempt_mode) {
>> +               vm2 = xe_vm_create(fd, preempt_mode ?
>> DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
>
>Since we're checking preempt_mode explicitly in the if condition above,
>do we need to keep that here?
>

Yah, good catch, will remove the redundant check.

Niranjana

>Functionally all looks good though.
>
>Thanks,
>Stuart
>
>> +               multi_queue.value |= DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
>> +               igt_assert_eq(__xe_exec_queue_create(fd, vm2, 1, 1,
>> eci, ext, &val), -EINVAL);
>> +               multi_queue.value &= ~DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
>> +               xe_vm_destroy(fd, vm2);
>> +       }
>> +
>>         /* Setting other queue properties are valid for Q0 */
>>         multi_queue.base.next_extension = to_user_pointer(&priority);
>>         exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
>> @@ -205,6 +217,21 @@ __test_sanity(int fd, int gt, int class, bool
>> preempt_mode)
>>         igt_waitchildren();
>>  
>>         xe_vm_destroy(fd, vm);
>> +
>> +       /* Validate closing FD while keeping group active */
>> +       fd = drm_open_driver(DRIVER_XE);
>> +       vm = xe_vm_create(fd, preempt_mode ?
>> DRM_XE_VM_CREATE_FLAG_LR_MODE |
>> +                         DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0, 0);
>> +
>> +       multi_queue.value = DRM_XE_MULTI_GROUP_CREATE |
>> DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
>> +       multi_queue.base.next_extension = 0;
>> +       exec_queues[0] = xe_exec_queue_create(fd, vm, eci, ext);
>> +
>> +       multi_queue.value = exec_queues[0];
>> +       for (i = 1; i < MAX_N_EXEC_QUEUES; i++)
>> +               exec_queues[i] = xe_exec_queue_create(fd, vm, eci,
>> ext);
>> +
>> +       drm_close_driver(fd);
>>  }
>>  
>>  /**
>

[PATCH v2 18/19] tests/intel/xe_exec_multi_queue: Keep group active in exec-sanity

[Niranjana Vishwanathapura]

In exec-sanity subtest, validate that job can be submitted
on secondary queue after closing the primary queue if the
user specifies the KEEP_ACTIVE flag while creating the group.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_multi_queue.c | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/tests/intel/xe_exec_multi_queue.c b/tests/intel/xe_exec_multi_queue.c
index 288ef9ed8..1449fa94e 100644
--- a/tests/intel/xe_exec_multi_queue.c
+++ b/tests/intel/xe_exec_multi_queue.c
@@ -268,6 +268,7 @@ __test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci, unsigned in
 	};
 	uint64_t ext = to_user_pointer(&multi_queue);
 	bool preempt_mode = flags & PREEMPT_MODE;
+	bool keep_active = flags & KEEP_ACTIVE;
 	int i;
 
 	sync.flags = DRM_XE_SYNC_FLAG_SIGNAL;
@@ -279,9 +280,13 @@ __test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci, unsigned in
 		sync.handle = syncobj_create(fd, 0);
 	}
 
-	vm = xe_vm_create(fd, preempt_mode ? DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
+	vm = xe_vm_create(fd, preempt_mode ? DRM_XE_VM_CREATE_FLAG_LR_MODE |
+			  DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0, 0);
 	bo_size = xe_bb_size(fd, sizeof(struct xe_spin));
 
+	if (keep_active)
+		multi_queue.value |= DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
+
 	for (i = 0; i < NUM_QUEUES; i++) {
 		bo[i] = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci[0].gt_id),
 				     DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
@@ -329,14 +334,27 @@ __test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci, unsigned in
 	/* Destroy primary queue */
 	xe_exec_queue_destroy(fd, exec_queues[0]);
 
-	/* Validate submission on secondary queues fail after destroying the primary */
+	/* Validate submission on secondary queues after destroying the primary */
 	xe_spin_init_opts(spin[1], .addr = addr[1]);
 	if (preempt_mode)
 		sync.addr = addr[1] + (char *)&spin[1]->exec_sync - (char *)spin[1];
 
 	exec.exec_queue_id = exec_queues[1];
 	exec.address = addr[1];
-	igt_assert_eq(__xe_exec(fd, &exec), -ECANCELED);
+
+	if (keep_active) {
+		xe_exec(fd, &exec);
+		xe_spin_wait_started(spin[1]);
+		xe_spin_end(spin[1]);
+		if (preempt_mode) {
+			xe_wait_ufence(fd, &spin[1]->exec_sync, USER_FENCE_VALUE, exec_queues[1], fence_timeout);
+		} else {
+			igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX, 0, NULL));
+			syncobj_reset(fd, &sync.handle, 1);
+		}
+	} else {
+		igt_assert_eq(__xe_exec(fd, &exec), -ECANCELED);
+	}
 
 	if (preempt_mode)
 		sync.addr = to_user_pointer(&vm_sync);
@@ -376,6 +394,8 @@ test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci)
 {
 	__test_exec_sanity(fd, eci, 0);
 	__test_exec_sanity(fd, eci, PREEMPT_MODE);
+	__test_exec_sanity(fd, eci, KEEP_ACTIVE);
+	__test_exec_sanity(fd, eci, PREEMPT_MODE | KEEP_ACTIVE);
 }
 
 static void
-- 
2.43.0

RE: [PATCH v2 18/19] tests/intel/xe_exec_multi_queue: Keep group active in exec-sanity

[Ch, Sai Gowtham]

>-----Original Message-----
>From: Vishwanathapura, Niranjana <niranjana.vishwanathapura@intel.com>
>Sent: Friday, November 21, 2025 9:28 AM
>To: igt-dev@lists.freedesktop.org
>Cc: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>; Dandamudi, Priyanka
><priyanka.dandamudi@intel.com>; kamil.konieczny@linux.intel.com
>Subject: [PATCH v2 18/19] tests/intel/xe_exec_multi_queue: Keep group active in
>exec-sanity
>
>In exec-sanity subtest, validate that job can be submitted on secondary queue after
>closing the primary queue if the user specifies the KEEP_ACTIVE flag while creating
>the group.
>
>Signed-off-by: Niranjana Vishwanathapura
><niranjana.vishwanathapura@intel.com>
>---
> tests/intel/xe_exec_multi_queue.c | 26 +++++++++++++++++++++++---
> 1 file changed, 23 insertions(+), 3 deletions(-)
>
>diff --git a/tests/intel/xe_exec_multi_queue.c
>b/tests/intel/xe_exec_multi_queue.c
>index 288ef9ed8..1449fa94e 100644
>--- a/tests/intel/xe_exec_multi_queue.c
>+++ b/tests/intel/xe_exec_multi_queue.c
>@@ -268,6 +268,7 @@ __test_exec_sanity(int fd, struct
>drm_xe_engine_class_instance *eci, unsigned in
> 	};
> 	uint64_t ext = to_user_pointer(&multi_queue);
> 	bool preempt_mode = flags & PREEMPT_MODE;
>+	bool keep_active = flags & KEEP_ACTIVE;
> 	int i;
>
> 	sync.flags = DRM_XE_SYNC_FLAG_SIGNAL;
>@@ -279,9 +280,13 @@ __test_exec_sanity(int fd, struct
>drm_xe_engine_class_instance *eci, unsigned in
> 		sync.handle = syncobj_create(fd, 0);
> 	}
>
>-	vm = xe_vm_create(fd, preempt_mode ?
>DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
>+	vm = xe_vm_create(fd, preempt_mode ?
>DRM_XE_VM_CREATE_FLAG_LR_MODE |
>+			  DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0, 0);
> 	bo_size = xe_bb_size(fd, sizeof(struct xe_spin));
>
>+	if (keep_active)
>+		multi_queue.value |= DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
>+
> 	for (i = 0; i < NUM_QUEUES; i++) {
> 		bo[i] = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd,
>eci[0].gt_id),
>
>DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
>@@ -329,14 +334,27 @@ __test_exec_sanity(int fd, struct
>drm_xe_engine_class_instance *eci, unsigned in
> 	/* Destroy primary queue */
> 	xe_exec_queue_destroy(fd, exec_queues[0]);
>
>-	/* Validate submission on secondary queues fail after destroying the
>primary */
>+	/* Validate submission on secondary queues after destroying the
>+primary */
> 	xe_spin_init_opts(spin[1], .addr = addr[1]);
> 	if (preempt_mode)
> 		sync.addr = addr[1] + (char *)&spin[1]->exec_sync - (char
>*)spin[1];
>
> 	exec.exec_queue_id = exec_queues[1];
> 	exec.address = addr[1];
>-	igt_assert_eq(__xe_exec(fd, &exec), -ECANCELED);
>+
>+	if (keep_active) {
>+		xe_exec(fd, &exec);
>+		xe_spin_wait_started(spin[1]);
>+		xe_spin_end(spin[1]);
>+		if (preempt_mode) {
>+			xe_wait_ufence(fd, &spin[1]->exec_sync,
>USER_FENCE_VALUE, exec_queues[1], fence_timeout);
>+		} else {
>+			igt_assert(syncobj_wait(fd, &sync.handle, 1, INT64_MAX,
>0, NULL));
>+			syncobj_reset(fd, &sync.handle, 1);
>+		}
>+	} else {
>+		igt_assert_eq(__xe_exec(fd, &exec), -ECANCELED);
>+	}
>
> 	if (preempt_mode)
> 		sync.addr = to_user_pointer(&vm_sync); @@ -376,6 +394,8 @@
>test_exec_sanity(int fd, struct drm_xe_engine_class_instance *eci)  {
> 	__test_exec_sanity(fd, eci, 0);
> 	__test_exec_sanity(fd, eci, PREEMPT_MODE);
>+	__test_exec_sanity(fd, eci, KEEP_ACTIVE);
>+	__test_exec_sanity(fd, eci, PREEMPT_MODE | KEEP_ACTIVE);
> }
LGTM
Reviewed-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> static void
>--
>2.43.0

Re: [PATCH v2 18/19] tests/intel/xe_exec_multi_queue: Keep group active in exec-sanity

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> In exec-sanity subtest, validate that job can be submitted
> on secondary queue after closing the primary queue if the
> user specifies the KEEP_ACTIVE flag while creating the group.
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> ---
>  tests/intel/xe_exec_multi_queue.c | 26 +++++++++++++++++++++++---
>  1 file changed, 23 insertions(+), 3 deletions(-)
> 
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index 288ef9ed8..1449fa94e 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -268,6 +268,7 @@ __test_exec_sanity(int fd, struct
> drm_xe_engine_class_instance *eci, unsigned in
>         };
>         uint64_t ext = to_user_pointer(&multi_queue);
>         bool preempt_mode = flags & PREEMPT_MODE;
> +       bool keep_active = flags & KEEP_ACTIVE;
>         int i;
>  
>         sync.flags = DRM_XE_SYNC_FLAG_SIGNAL;
> @@ -279,9 +280,13 @@ __test_exec_sanity(int fd, struct
> drm_xe_engine_class_instance *eci, unsigned in
>                 sync.handle = syncobj_create(fd, 0);
>         }
>  
> -       vm = xe_vm_create(fd, preempt_mode ?
> DRM_XE_VM_CREATE_FLAG_LR_MODE : 0, 0);
> +       vm = xe_vm_create(fd, preempt_mode ?
> DRM_XE_VM_CREATE_FLAG_LR_MODE |
> +                         DRM_XE_VM_CREATE_FLAG_FAULT_MODE : 0, 0);
>         bo_size = xe_bb_size(fd, sizeof(struct xe_spin));
>  
> +       if (keep_active)
> +               multi_queue.value |= DRM_XE_MULTI_GROUP_KEEP_ACTIVE;
> +
>         for (i = 0; i < NUM_QUEUES; i++) {
>                 bo[i] = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
>                                     
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> @@ -329,14 +334,27 @@ __test_exec_sanity(int fd, struct
> drm_xe_engine_class_instance *eci, unsigned in
>         /* Destroy primary queue */
>         xe_exec_queue_destroy(fd, exec_queues[0]);
>  
> -       /* Validate submission on secondary queues fail after
> destroying the primary */
> +       /* Validate submission on secondary queues after destroying
> the primary */
>         xe_spin_init_opts(spin[1], .addr = addr[1]);
>         if (preempt_mode)
>                 sync.addr = addr[1] + (char *)&spin[1]->exec_sync -
> (char *)spin[1];
>  
>         exec.exec_queue_id = exec_queues[1];
>         exec.address = addr[1];
> -       igt_assert_eq(__xe_exec(fd, &exec), -ECANCELED);
> +
> +       if (keep_active) {
> +               xe_exec(fd, &exec);
> +               xe_spin_wait_started(spin[1]);
> +               xe_spin_end(spin[1]);
> +               if (preempt_mode) {
> +                       xe_wait_ufence(fd, &spin[1]->exec_sync,
> USER_FENCE_VALUE, exec_queues[1], fence_timeout);
> +               } else {
> +                       igt_assert(syncobj_wait(fd, &sync.handle, 1,
> INT64_MAX, 0, NULL));
> +                       syncobj_reset(fd, &sync.handle, 1);
> +               }
> +       } else {
> +               igt_assert_eq(__xe_exec(fd, &exec), -ECANCELED);
> +       }
>  
>         if (preempt_mode)
>                 sync.addr = to_user_pointer(&vm_sync);
> @@ -376,6 +394,8 @@ test_exec_sanity(int fd, struct
> drm_xe_engine_class_instance *eci)
>  {
>         __test_exec_sanity(fd, eci, 0);
>         __test_exec_sanity(fd, eci, PREEMPT_MODE);
> +       __test_exec_sanity(fd, eci, KEEP_ACTIVE);
> +       __test_exec_sanity(fd, eci, PREEMPT_MODE | KEEP_ACTIVE);
>  }
>  
>  static void

[PATCH v2 19/19] tests/intel/xe_exec_queue_property: Update invalid-property test

[Niranjana Vishwanathapura]

Given we have new multi-queue exec_queue properties, update
the invalid-property test accordingly.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/intel/xe_exec_queue_property.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/intel/xe_exec_queue_property.c b/tests/intel/xe_exec_queue_property.c
index 4dfcf09e2..e1be1c9de 100644
--- a/tests/intel/xe_exec_queue_property.c
+++ b/tests/intel/xe_exec_queue_property.c
@@ -189,7 +189,7 @@ static void invalid_property(int xe)
 
 	/* This will fail as soon as a new property is introduced. It is
 	 * expected and the test will have to be updated. */
-	for (int i = 3; i < 16; i++ ) {
+	for (int i = 5; i < 16; i++ ) {
 		ext.property = i;
 		igt_assert_eq(__xe_exec_queue_create(xe, vm, 1, 1, &instance,
 						     to_user_pointer(&ext), &exec_queue_id), -EINVAL);
-- 
2.43.0

Re: [PATCH v2 19/19] tests/intel/xe_exec_queue_property: Update invalid-property test

[Summers, Stuart]

On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Given we have new multi-queue exec_queue properties, update
> the invalid-property test accordingly.
> 
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

I don't like that this is all hard coded. But also we aren't doing
anything revolutionary here.

> ---
>  tests/intel/xe_exec_queue_property.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tests/intel/xe_exec_queue_property.c
> b/tests/intel/xe_exec_queue_property.c
> index 4dfcf09e2..e1be1c9de 100644
> --- a/tests/intel/xe_exec_queue_property.c
> +++ b/tests/intel/xe_exec_queue_property.c
> @@ -189,7 +189,7 @@ static void invalid_property(int xe)
>  
>         /* This will fail as soon as a new property is introduced. It
> is
>          * expected and the test will have to be updated. */
> -       for (int i = 3; i < 16; i++ ) {
> +       for (int i = 5; i < 16; i++ ) {
>                 ext.property = i;
>                 igt_assert_eq(__xe_exec_queue_create(xe, vm, 1, 1,
> &instance,
>                                                     
> to_user_pointer(&ext), &exec_queue_id), -EINVAL);

Re: [PATCH v2 19/19] tests/intel/xe_exec_queue_property: Update invalid-property test

[Niranjana Vishwanathapura]

On Thu, Dec 04, 2025 at 11:25:21AM -0800, Summers, Stuart wrote:
>On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
>> Given we have new multi-queue exec_queue properties, update
>> the invalid-property test accordingly.
>>
>> Signed-off-by: Niranjana Vishwanathapura
>> <niranjana.vishwanathapura@intel.com>
>
>Reviewed-by: Stuart Summers <stuart.summers@intel.com>
>
>I don't like that this is all hard coded. But also we aren't doing
>anything revolutionary here.

The below patch removed hard coding.
tests/intel/xe_exec_queue_property: Use single invalid property

So, we no loner need this patch. Will remove it in next revision.

Niranjana

>
>> ---
>>  tests/intel/xe_exec_queue_property.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/tests/intel/xe_exec_queue_property.c
>> b/tests/intel/xe_exec_queue_property.c
>> index 4dfcf09e2..e1be1c9de 100644
>> --- a/tests/intel/xe_exec_queue_property.c
>> +++ b/tests/intel/xe_exec_queue_property.c
>> @@ -189,7 +189,7 @@ static void invalid_property(int xe)
>>  
>>         /* This will fail as soon as a new property is introduced. It
>> is
>>          * expected and the test will have to be updated. */
>> -       for (int i = 3; i < 16; i++ ) {
>> +       for (int i = 5; i < 16; i++ ) {
>>                 ext.property = i;
>>                 igt_assert_eq(__xe_exec_queue_create(xe, vm, 1, 1,
>> &instance,
>>                                                     
>> to_user_pointer(&ext), &exec_queue_id), -EINVAL);
>

✓ Xe.CI.BAT: success for Multi Queue feature validation support (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2359 bytes --]

== Series Details ==

Series: Multi Queue feature validation support (rev2)
URL   : https://patchwork.freedesktop.org/series/156866/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8636_BAT -> XEIGTPW_14091_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_14091_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@abstime:
    - bat-dg2-oem2:       [PASS][1] -> [TIMEOUT][2] ([Intel XE#6506])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/bat-dg2-oem2/igt@xe_waitfence@abstime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/bat-dg2-oem2/igt@xe_waitfence@abstime.html

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [PASS][3] -> [FAIL][4] ([Intel XE#6520])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
#### Possible fixes ####

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [FAIL][5] ([Intel XE#6519]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
  [Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * IGT: IGT_8636 -> IGTPW_14091
  * Linux: xe-4134-13909978d70fc4ded88b778a313b68ad86ba881a -> xe-4135-3d718db04a365cc44a3bc81ffa4db7bbd2e645d7

  IGTPW_14091: 14091
  IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4134-13909978d70fc4ded88b778a313b68ad86ba881a: 13909978d70fc4ded88b778a313b68ad86ba881a
  xe-4135-3d718db04a365cc44a3bc81ffa4db7bbd2e645d7: 3d718db04a365cc44a3bc81ffa4db7bbd2e645d7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/index.html

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✓ i915.CI.BAT: success for Multi Queue feature validation support (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2853 bytes --]

== Series Details ==

Series: Multi Queue feature validation support (rev2)
URL   : https://patchwork.freedesktop.org/series/156866/
State : success

== Summary ==

CI Bug Log - changes from IGT_8636 -> IGTPW_14091
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/index.html

Participating hosts (45 -> 43)
------------------------------

  Missing    (2): fi-glk-j4005 fi-snb-2520m 

Known issues
------------

  Here are the changes found in IGTPW_14091 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [DMESG-FAIL][1] ([i915#12061]) -> [PASS][2] +1 other test pass
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8636/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/bat-arlh-3/igt@i915_selftest@live@workarounds.html
    - bat-dg2-11:         [DMESG-FAIL][3] ([i915#12061]) -> [PASS][4] +1 other test pass
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8636/bat-dg2-11/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/bat-dg2-11/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [DMESG-FAIL][5] ([i915#12061] / [i915#13929]) -> [DMESG-FAIL][6] ([i915#12061] / [i915#14204])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8636/bat-atsm-1/igt@i915_selftest@live.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/bat-atsm-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [DMESG-FAIL][7] ([i915#13929]) -> [DMESG-FAIL][8] ([i915#14204])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8636/bat-atsm-1/igt@i915_selftest@live@mman.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8636 -> IGTPW_14091
  * Linux: CI_DRM_17575 -> CI_DRM_17576

  CI-20190529: 20190529
  CI_DRM_17575: 13909978d70fc4ded88b778a313b68ad86ba881a @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_17576: 3d718db04a365cc44a3bc81ffa4db7bbd2e645d7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_14091: 14091
  IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/index.html

[-- Attachment #2: Type: text/html, Size: 3893 bytes --]

✗ Xe.CI.Full: failure for Multi Queue feature validation support (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 59627 bytes --]

== Series Details ==

Series: Multi Queue feature validation support (rev2)
URL   : https://patchwork.freedesktop.org/series/156866/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8636_FULL -> XEIGTPW_14091_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_14091_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_14091_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 3)
------------------------------

  Missing    (1): shard-adlp 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_14091_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][1] -> [TIMEOUT][2] +1 other test timeout
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-dg2-433/igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-463/igt@kms_hdr@static-toggle-suspend@pipe-a-dp-4.html

  * {igt@xe_exec_multi_queue@many-queues-preempt-mode-userptr} (NEW):
    - shard-lnl:          NOTRUN -> [SKIP][3] +174 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-8/igt@xe_exec_multi_queue@many-queues-preempt-mode-userptr.html

  * {igt@xe_exec_multi_queue@one-queue-close-fd-smem} (NEW):
    - shard-dg2-set2:     NOTRUN -> [SKIP][4] +157 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-466/igt@xe_exec_multi_queue@one-queue-close-fd-smem.html

  
New tests
---------

  New tests have been introduced between XEIGT_8636_FULL and XEIGTPW_14091_FULL:

### New IGT tests (184) ###

  * igt@xe_exec_multi_queue@exec-sanity:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-close-fd:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-basic:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-dyn-priority:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-priority:
    - Statuses :
    - Exec time: [None] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-priority:
    - Statuses :
    - Exec time: [None] s

  * igt@xe_exec_multi_queue@few-execs-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@few-execs-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-dyn-priority:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-basic:
    - Statuses :
    - Exec time: [None] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-priority-smem:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-priority-smem:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-execs-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-basic:
    - Statuses :
    - Exec time: [None] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-dyn-priority-smem:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-priority-smem:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-userptr-invalidate:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@many-queues-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-basic-smem:
    - Statuses :
    - Exec time: [None] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-close-fd-smem:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-userptr-invalidate:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-userptr:
    - Statuses :
    - Exec time: [None] s

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@max-queues-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-basic:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-dyn-priority-smem:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@one-queue-userptr:
    - Statuses :
    - Exec time: [None] s

  * igt@xe_exec_multi_queue@one-queue-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@sanity:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-close-fd-smem:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-dyn-priority:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-close-fd:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-basic:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-basic-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-close-fd:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-close-fd-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-priority-smem:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-priority:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-priority-smem:
    - Statuses :
    - Exec time: [None] s

  * igt@xe_exec_multi_queue@two-queues-userptr:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@two-queues-userptr-invalidate:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@xe_exec_multi_queue@virtual:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_14091_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1:
    - shard-lnl:          [PASS][5] -> [FAIL][6] ([Intel XE#5993]) +3 other tests fail
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-1/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] ([Intel XE#316]) +2 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-434/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1407]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-8/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1124]) +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-4/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#1124]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#2191])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-2/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#1512])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-2/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][13] ([Intel XE#367])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-434/igt@kms_bw@linear-tiling-3-displays-1920x1080p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#787]) +27 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-466/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-c-dp-4.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-466/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#3432])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#2887]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-5/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][18] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#6168])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][19] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][20] -> [INCOMPLETE][21] ([Intel XE#6168])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][22] -> [DMESG-WARN][23] ([Intel XE#1727] / [Intel XE#3113])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][24] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html

  * igt@kms_chamelium_hpd@vga-hpd:
    - shard-dg2-set2:     NOTRUN -> [SKIP][25] ([Intel XE#373]) +5 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-433/igt@kms_chamelium_hpd@vga-hpd.html
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#373]) +3 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-1/igt@kms_chamelium_hpd@vga-hpd.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#6507])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-463/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#307])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-433/igt@kms_content_protection@dp-mst-lic-type-1.html
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#307])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-1/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_cursor_crc@cursor-random-32x10:
    - shard-dg2-set2:     NOTRUN -> [SKIP][30] ([Intel XE#455]) +4 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-466/igt@kms_cursor_crc@cursor-random-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#1424])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-2/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#309]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#2244])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-7/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_feature_discovery@display-3x:
    - shard-dg2-set2:     NOTRUN -> [SKIP][34] ([Intel XE#703])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-436/igt@kms_feature_discovery@display-3x.html

  * igt@kms_flip@2x-wf_vblank-ts-check:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#1421])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-5/igt@kms_flip@2x-wf_vblank-ts-check.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#1401] / [Intel XE#1745])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#1401])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-pri-indfb-multidraw:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#651]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#656]) +5 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][40] ([Intel XE#6312]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render.html
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#6312])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-plflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][42] ([Intel XE#651]) +7 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#653]) +10 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#2763]) +3 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-7/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][45] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-466/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@fbc-psr2-dpms@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#1406] / [Intel XE#4609])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-7/igt@kms_psr@fbc-psr2-dpms@edp-1.html

  * igt@kms_psr@pr-sprite-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][47] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +4 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-433/igt@kms_psr@pr-sprite-blt.html
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#1406]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-2/igt@kms_psr@pr-sprite-blt.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#1406] / [Intel XE#2939])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-436/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#3414] / [Intel XE#3904])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#3414])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][52] -> [FAIL][53] ([Intel XE#4459]) +1 other test fail
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-4/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@xe_configfs@survivability-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][54] ([Intel XE#6010])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-463/igt@xe_configfs@survivability-mode.html

  * igt@xe_copy_basic@mem-set-linear-0x3fff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#1126])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0x3fff.html

  * igt@xe_eu_stall@unprivileged-access:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#5626])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-464/igt@xe_eu_stall@unprivileged-access.html

  * igt@xe_eudebug@basic-vm-bind-extended-discovery:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#4837]) +3 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-1/igt@xe_eudebug@basic-vm-bind-extended-discovery.html

  * igt@xe_eudebug@vm-bind-clear-faultable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][58] ([Intel XE#4837]) +5 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-435/igt@xe_eudebug@vm-bind-clear-faultable.html

  * igt@xe_evict@evict-small-multi-vm-cm:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#688]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-7/igt@xe_evict@evict-small-multi-vm-cm.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#1392])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][61] ([Intel XE#288]) +6 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-433/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch.html

  * igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][62] ([Intel XE#6299])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-436/igt@xe_exec_reset@long-spin-comp-reuse-many-preempt-threads.html

  * igt@xe_exec_system_allocator@many-64k-mmap-new-huge-nomemset:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#5007])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-2/igt@xe_exec_system_allocator@many-64k-mmap-new-huge-nomemset.html

  * igt@xe_exec_system_allocator@many-stride-malloc-prefetch-madvise:
    - shard-lnl:          NOTRUN -> [WARN][64] ([Intel XE#5786])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-2/igt@xe_exec_system_allocator@many-stride-malloc-prefetch-madvise.html

  * igt@xe_exec_system_allocator@process-many-execqueues-free-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][65] ([Intel XE#4915]) +139 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-432/igt@xe_exec_system_allocator@process-many-execqueues-free-race.html

  * igt@xe_exec_system_allocator@process-many-stride-mmap-new-huge-nomemset:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#4943]) +2 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-1/igt@xe_exec_system_allocator@process-many-stride-mmap-new-huge-nomemset.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][67] ([Intel XE#5893])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-463/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html

  * igt@xe_mmap@pci-membarrier-parallel:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#5100])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-1/igt@xe_mmap@pci-membarrier-parallel.html

  * igt@xe_module_load@force-load:
    - shard-dg2-set2:     NOTRUN -> [SKIP][69] ([Intel XE#378])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-464/igt@xe_module_load@force-load.html
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#378])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-3/igt@xe_module_load@force-load.html

  * igt@xe_oa@disabled-read-error:
    - shard-dg2-set2:     NOTRUN -> [SKIP][71] ([Intel XE#3573]) +6 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-432/igt@xe_oa@disabled-read-error.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#579])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-464/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_compute0:
    - shard-lnl:          [PASS][73] -> [FAIL][74] ([Intel XE#6251]) +3 other tests fail
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-lnl-2/igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_compute0.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_compute0.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq:
    - shard-dg2-set2:     NOTRUN -> [SKIP][75] ([Intel XE#4733]) +1 other test skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-434/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html

  * igt@xe_query@multigpu-query-topology-l3-bank-mask:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#944]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-8/igt@xe_query@multigpu-query-topology-l3-bank-mask.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#944]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-435/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  * igt@xe_render_copy@render-stress-1-copies:
    - shard-dg2-set2:     NOTRUN -> [SKIP][78] ([Intel XE#4814])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-434/igt@xe_render_copy@render-stress-1-copies.html

  * igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#4130])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-432/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html

  * igt@xe_sriov_scheduling@nonpreempt-engine-resets:
    - shard-dg2-set2:     NOTRUN -> [SKIP][80] ([Intel XE#4351])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-463/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#4351])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-8/igt@xe_sriov_scheduling@nonpreempt-engine-resets.html

  
#### Possible fixes ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][82] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#6014]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [FAIL][84] ([Intel XE#718]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-lnl-4/igt@kms_pm_dc@dc5-psr.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-1/igt@kms_pm_dc@dc5-psr.html

  * igt@xe_pm_residency@idle-residency:
    - shard-dg2-set2:     [FAIL][86] ([Intel XE#6362]) -> [PASS][87] +1 other test pass
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-dg2-432/igt@xe_pm_residency@idle-residency.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-432/igt@xe_pm_residency@idle-residency.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0:
    - shard-lnl:          [FAIL][88] ([Intel XE#6251]) -> [PASS][89] +1 other test pass
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_compute0.html

  
#### Warnings ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][90] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345]) -> [INCOMPLETE][91] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) +1 other test incomplete
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2-set2:     [SKIP][92] ([Intel XE#362]) -> [FAIL][93] ([Intel XE#1729])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][94] ([Intel XE#1500]) -> [SKIP][95] ([Intel XE#362])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-dg2-435/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([DMESG-WARN][96], [DMESG-WARN][97], [DMESG-WARN][98], [DMESG-WARN][99], [DMESG-WARN][100], [DMESG-WARN][101], [DMESG-WARN][102], [DMESG-WARN][103], [DMESG-WARN][104], [DMESG-WARN][105], [DMESG-WARN][106], [DMESG-WARN][107], [DMESG-WARN][108], [DMESG-WARN][109], [DMESG-WARN][110], [DMESG-WARN][111], [DMESG-WARN][112], [DMESG-WARN][113], [DMESG-WARN][114], [INCOMPLETE][115], [DMESG-WARN][116], [DMESG-WARN][117], [DMESG-WARN][118], [DMESG-WARN][119], [DMESG-WARN][120]) ([Intel XE#1727] / [Intel XE#6659]) -> ([DMESG-WARN][121], [DMESG-WARN][122], [DMESG-WARN][123], [DMESG-WARN][124], [DMESG-WARN][125], [DMESG-WARN][126], [DMESG-WARN][127], [DMESG-WARN][128], [DMESG-WARN][129], [DMESG-WARN][130], [DMESG-WARN][131], [DMESG-WARN][132], [DMESG-WARN][133], [DMESG-WARN][134], [DMESG-WARN][135], [DMESG-WARN][136], [DMESG-WARN][137], [DMESG-WARN][138], [DMESG-WARN][139], [DMESG-WARN][140], [DMESG-WARN][141], [DMESG-WARN][142], [DMESG-WARN][143], [DMESG-WARN][144], [DMESG-WARN][145]) ([Intel XE#6659])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-5/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-2/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-2/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-4/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-4/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-4/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-2/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-2/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-8/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-8/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-8/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-1/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-7/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-7/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-7/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-7/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-1/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-1/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-6/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-6/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-3/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-3/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-3/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-5/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8636/shard-bmg-5/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-5/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-5/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-3/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-5/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-2/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-2/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-2/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-3/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-3/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-6/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-6/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-6/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-4/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-4/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-4/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-7/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-7/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-7/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-7/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-8/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-8/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-8/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-1/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-1/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/shard-bmg-1/igt@xe_module_load@load.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#5893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5893
  [Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
  [Intel XE#6010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6010
  [Intel XE#6014]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6014
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6299
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6362
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6659
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8636 -> IGTPW_14091
  * Linux: xe-4134-13909978d70fc4ded88b778a313b68ad86ba881a -> xe-4135-3d718db04a365cc44a3bc81ffa4db7bbd2e645d7

  IGTPW_14091: 14091
  IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4134-13909978d70fc4ded88b778a313b68ad86ba881a: 13909978d70fc4ded88b778a313b68ad86ba881a
  xe-4135-3d718db04a365cc44a3bc81ffa4db7bbd2e645d7: 3d718db04a365cc44a3bc81ffa4db7bbd2e645d7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_14091/index.html

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✗ i915.CI.Full: failure for Multi Queue feature validation support (rev2)

[Patchwork]

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== Series Details ==

Series: Multi Queue feature validation support (rev2)
URL   : https://patchwork.freedesktop.org/series/156866/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17576_full -> IGTPW_14091_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_14091_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_14091_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/index.html

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_14091_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-rkl:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1.html

  
New tests
---------

  New tests have been introduced between CI_DRM_17576_full and IGTPW_14091_full:

### New IGT tests (3) ###

  * igt@kms_dirtyfb@default-dirtyfb-ioctl@a-hdmi-a-1:
    - Statuses : 2 pass(s)
    - Exec time: [1.21, 1.35] s

  * igt@kms_dirtyfb@default-dirtyfb-ioctl@a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [1.32] s

  * igt@kms_dirtyfb@default-dirtyfb-ioctl@a-hdmi-a-3:
    - Statuses : 1 pass(s)
    - Exec time: [1.42] s

  

Known issues
------------

  Here are the changes found in IGTPW_14091_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@object-reloc-keep-cache:
    - shard-mtlp:         NOTRUN -> [SKIP][4] ([i915#8411])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-6/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@device_reset@cold-reset-bound:
    - shard-tglu-1:       NOTRUN -> [SKIP][5] ([i915#11078])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@device_reset@cold-reset-bound.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-rkl:          NOTRUN -> [SKIP][6] ([i915#11078])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_basic@multigpu-create-close:
    - shard-mtlp:         NOTRUN -> [SKIP][7] ([i915#7697])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-3/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-tglu-1:       NOTRUN -> [SKIP][8] ([i915#3555] / [i915#9323])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-tglu:         NOTRUN -> [SKIP][9] ([i915#13008])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-6/igt@gem_ccs@large-ctrl-surf-copy.html
    - shard-mtlp:         NOTRUN -> [SKIP][10] ([i915#13008])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-6/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-rkl:          NOTRUN -> [SKIP][11] ([i915#9323])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@gem_ccs@suspend-resume.html

  * igt@gem_ctx_persistence@hang:
    - shard-dg2:          NOTRUN -> [SKIP][12] ([i915#8555])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-11/igt@gem_ctx_persistence@hang.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-tglu:         NOTRUN -> [SKIP][13] ([i915#280])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-7/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_exec_balancer@parallel:
    - shard-rkl:          NOTRUN -> [SKIP][14] ([i915#4525]) +2 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-tglu:         NOTRUN -> [SKIP][15] ([i915#4525]) +2 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-4/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_capture@capture-invisible:
    - shard-glk10:        NOTRUN -> [SKIP][16] ([i915#6334]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk10/igt@gem_exec_capture@capture-invisible.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-rkl:          NOTRUN -> [SKIP][17] ([i915#6344])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_fence@submit3:
    - shard-mtlp:         NOTRUN -> [SKIP][18] ([i915#4812])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-2/igt@gem_exec_fence@submit3.html

  * igt@gem_exec_fence@submit67:
    - shard-dg2:          NOTRUN -> [SKIP][19] ([i915#4812])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-3/igt@gem_exec_fence@submit67.html

  * igt@gem_exec_reloc@basic-gtt-read:
    - shard-dg2:          NOTRUN -> [SKIP][20] ([i915#3281]) +6 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-3/igt@gem_exec_reloc@basic-gtt-read.html

  * igt@gem_exec_reloc@basic-wc:
    - shard-rkl:          NOTRUN -> [SKIP][21] ([i915#3281]) +4 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-3/igt@gem_exec_reloc@basic-wc.html

  * igt@gem_exec_reloc@basic-wc-gtt-noreloc:
    - shard-dg1:          NOTRUN -> [SKIP][22] ([i915#3281])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-12/igt@gem_exec_reloc@basic-wc-gtt-noreloc.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-dg2:          [PASS][23] -> [INCOMPLETE][24] ([i915#13356]) +2 other tests incomplete
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-4/igt@gem_exec_suspend@basic-s0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-6/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_fence_thrash@bo-write-verify-x:
    - shard-mtlp:         NOTRUN -> [SKIP][25] ([i915#4860])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-7/igt@gem_fence_thrash@bo-write-verify-x.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglu:         NOTRUN -> [SKIP][26] ([i915#2190])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-5/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-rkl:          NOTRUN -> [SKIP][27] ([i915#4613])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-3/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-glk:          NOTRUN -> [SKIP][28] ([i915#4613])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk6/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][29] ([i915#4613]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-rkl:          NOTRUN -> [SKIP][30] ([i915#14544] / [i915#4613])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_lmem_swapping@verify-random-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][31] ([i915#4613])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-2/igt@gem_lmem_swapping@verify-random-ccs.html

  * igt@gem_mmap@bad-offset:
    - shard-dg2:          NOTRUN -> [SKIP][32] ([i915#4083])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-4/igt@gem_mmap@bad-offset.html
    - shard-dg1:          NOTRUN -> [SKIP][33] ([i915#4083]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-18/igt@gem_mmap@bad-offset.html

  * igt@gem_mmap@bad-size:
    - shard-mtlp:         NOTRUN -> [SKIP][34] ([i915#4083]) +4 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-4/igt@gem_mmap@bad-size.html

  * igt@gem_pread@exhaustion:
    - shard-tglu:         NOTRUN -> [WARN][35] ([i915#2658])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-5/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@create-regular-context-1:
    - shard-dg2:          NOTRUN -> [SKIP][36] ([i915#4270])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-4/igt@gem_pxp@create-regular-context-1.html

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - shard-dg1:          NOTRUN -> [SKIP][37] ([i915#4270])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-19/igt@gem_pxp@reject-modify-context-protection-off-3.html

  * igt@gem_readwrite@beyond-eob:
    - shard-mtlp:         NOTRUN -> [SKIP][38] ([i915#3282])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-2/igt@gem_readwrite@beyond-eob.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
    - shard-glk:          NOTRUN -> [SKIP][39] +214 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk6/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][40] ([i915#8428]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-3/igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html

  * igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][41] ([i915#5190] / [i915#8428]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-7/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-rkl:          NOTRUN -> [SKIP][42] ([i915#8411]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-3/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_tiled_pread_basic:
    - shard-rkl:          NOTRUN -> [SKIP][43] ([i915#3282])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@gem_tiled_pread_basic.html

  * igt@gem_tiled_wb:
    - shard-dg2:          NOTRUN -> [SKIP][44] ([i915#4077]) +4 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-7/igt@gem_tiled_wb.html
    - shard-dg1:          NOTRUN -> [SKIP][45] ([i915#4077])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-13/igt@gem_tiled_wb.html
    - shard-mtlp:         NOTRUN -> [SKIP][46] ([i915#4077]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-6/igt@gem_tiled_wb.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-tglu-1:       NOTRUN -> [SKIP][47] ([i915#3297]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@forbidden-operations:
    - shard-mtlp:         NOTRUN -> [SKIP][48] ([i915#3282] / [i915#3297])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-4/igt@gem_userptr_blits@forbidden-operations.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-rkl:          NOTRUN -> [SKIP][49] ([i915#14544] / [i915#3297]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_userptr_blits@unsync-overlap.html
    - shard-tglu:         NOTRUN -> [SKIP][50] ([i915#3297]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-7/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gen3_render_tiledy_blits:
    - shard-mtlp:         NOTRUN -> [SKIP][51] +4 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-2/igt@gen3_render_tiledy_blits.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-tglu-1:       NOTRUN -> [SKIP][52] ([i915#2527] / [i915#2856]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-rkl:          NOTRUN -> [SKIP][53] ([i915#2527]) +2 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-tglu:         NOTRUN -> [SKIP][54] ([i915#2527] / [i915#2856]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-4/igt@gen9_exec_parse@bb-oversize.html
    - shard-mtlp:         NOTRUN -> [SKIP][55] ([i915#2856])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-8/igt@gen9_exec_parse@bb-oversize.html

  * igt@i915_drm_fdinfo@busy-idle@rcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][56] ([i915#14073]) +6 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-3/igt@i915_drm_fdinfo@busy-idle@rcs0.html

  * igt@i915_module_load@load:
    - shard-tglu:         ([PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78]) -> ([PASS][79], [SKIP][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98]) ([i915#14785])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-10/igt@i915_module_load@load.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-10/igt@i915_module_load@load.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-10/igt@i915_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-2/igt@i915_module_load@load.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-2/igt@i915_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-2/igt@i915_module_load@load.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-3/igt@i915_module_load@load.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-3/igt@i915_module_load@load.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-4/igt@i915_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-4/igt@i915_module_load@load.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-4/igt@i915_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-5/igt@i915_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-5/igt@i915_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-6/igt@i915_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-6/igt@i915_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-7/igt@i915_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-7/igt@i915_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-8/igt@i915_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-8/igt@i915_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-8/igt@i915_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-9/igt@i915_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-9/igt@i915_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-8/igt@i915_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-3/igt@i915_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-9/igt@i915_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-8/igt@i915_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-8/igt@i915_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-2/igt@i915_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-3/igt@i915_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-10/igt@i915_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-6/igt@i915_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-5/igt@i915_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-7/igt@i915_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-4/igt@i915_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-9/igt@i915_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-5/igt@i915_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-10/igt@i915_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-7/igt@i915_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-6/igt@i915_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-9/igt@i915_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-4/igt@i915_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-5/igt@i915_module_load@load.html

  * igt@i915_module_load@reload-no-display:
    - shard-snb:          [PASS][99] -> [DMESG-WARN][100] ([i915#14545])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-snb1/igt@i915_module_load@reload-no-display.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-snb7/igt@i915_module_load@reload-no-display.html

  * igt@i915_module_load@resize-bar:
    - shard-tglu:         NOTRUN -> [SKIP][101] ([i915#6412])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-2/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_freq_api@freq-basic-api:
    - shard-tglu:         NOTRUN -> [SKIP][102] ([i915#8399])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-8/igt@i915_pm_freq_api@freq-basic-api.html

  * igt@i915_pm_rc6_residency@media-rc6-accuracy:
    - shard-rkl:          NOTRUN -> [SKIP][103] ([i915#14544]) +1 other test skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@i915_pm_rc6_residency@media-rc6-accuracy.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglu:         NOTRUN -> [WARN][104] ([i915#13790] / [i915#2681]) +1 other test warn
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_query@hwconfig_table:
    - shard-tglu-1:       NOTRUN -> [SKIP][105] ([i915#6245])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@i915_query@hwconfig_table.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-glk:          NOTRUN -> [INCOMPLETE][106] ([i915#4817])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk5/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - shard-dg1:          NOTRUN -> [SKIP][107] ([i915#4212])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-15/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - shard-mtlp:         NOTRUN -> [SKIP][108] ([i915#4212])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-4/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - shard-dg2:          NOTRUN -> [SKIP][109] ([i915#4212])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-6/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  * igt@kms_atomic@atomic-plane-damage:
    - shard-glk10:        NOTRUN -> [SKIP][110] +99 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk10/igt@kms_atomic@atomic-plane-damage.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-glk:          NOTRUN -> [SKIP][111] ([i915#1769])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
    - shard-tglu:         NOTRUN -> [SKIP][112] ([i915#1769] / [i915#3555])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition:
    - shard-dg2:          [PASS][113] -> [FAIL][114] ([i915#5956])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-3/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-4/igt@kms_atomic_transition@plane-toggle-modeset-transition.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [FAIL][115] ([i915#5956])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-4/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][116] ([i915#5286]) +1 other test skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-tglu:         NOTRUN -> [SKIP][117] ([i915#5286]) +5 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-9/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][118] ([i915#14544] / [i915#5286])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
    - shard-dg1:          NOTRUN -> [SKIP][119] ([i915#4538] / [i915#5286])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-15/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][120] ([i915#5286]) +3 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
    - shard-mtlp:         [PASS][121] -> [FAIL][122] ([i915#5138])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][123] ([i915#3638])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-12/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-180:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#4538] / [i915#5190]) +1 other test skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-11/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-dg1:          NOTRUN -> [SKIP][125] +10 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-12/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
    - shard-mtlp:         NOTRUN -> [SKIP][126] ([i915#6187]) +1 other test skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-4/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][127] ([i915#10307] / [i915#10434] / [i915#6095])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-4/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][128] ([i915#10307] / [i915#6095]) +107 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-7/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][129] ([i915#12313]) +2 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-3/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
    - shard-mtlp:         NOTRUN -> [SKIP][130] ([i915#12313]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-2/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][131] ([i915#12313])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
    - shard-dg1:          NOTRUN -> [SKIP][132] ([i915#12313])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-15/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][133] ([i915#6095]) +14 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-3/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-d-edp-1.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][134] ([i915#6095]) +112 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-12/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][135] ([i915#12805])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][136] ([i915#6095]) +54 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-4/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][137] ([i915#6095]) +24 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#6095]) +7 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-4/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-glk:          NOTRUN -> [INCOMPLETE][139] ([i915#12796]) +1 other test incomplete
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk9/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][140] ([i915#6095]) +75 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][141] ([i915#14098] / [i915#6095]) +47 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][142] ([i915#14544] / [i915#6095]) +7 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][143] ([i915#14098] / [i915#14544] / [i915#6095]) +5 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][144] ([i915#13781]) +3 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-7/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_cdclk@plane-scaling:
    - shard-rkl:          NOTRUN -> [SKIP][145] ([i915#3742])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-3/igt@kms_cdclk@plane-scaling.html
    - shard-tglu-1:       NOTRUN -> [SKIP][146] ([i915#3742])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-mtlp:         NOTRUN -> [SKIP][147] ([i915#11151] / [i915#7828]) +1 other test skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-3/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-dg2:          NOTRUN -> [SKIP][148] +5 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-11/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-dg2:          NOTRUN -> [SKIP][149] ([i915#11151] / [i915#7828]) +2 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-4/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_chamelium_frames@hdmi-aspect-ratio:
    - shard-tglu:         NOTRUN -> [SKIP][150] ([i915#11151] / [i915#7828]) +6 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-3/igt@kms_chamelium_frames@hdmi-aspect-ratio.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
    - shard-tglu-1:       NOTRUN -> [SKIP][151] ([i915#11151] / [i915#7828]) +2 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_chamelium_frames@hdmi-crc-fast.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-rkl:          NOTRUN -> [SKIP][152] ([i915#11151] / [i915#7828]) +3 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_color@deep-color:
    - shard-tglu:         NOTRUN -> [SKIP][153] ([i915#3555] / [i915#9979])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-7/igt@kms_color@deep-color.html

  * igt@kms_content_protection@content-type-change:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#9424])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-1/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][155] ([i915#3116] / [i915#3299]) +1 other test skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-rkl:          NOTRUN -> [SKIP][156] ([i915#3116])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@type1:
    - shard-tglu:         NOTRUN -> [SKIP][157] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424]) +1 other test skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-10/igt@kms_content_protection@type1.html

  * igt@kms_content_protection@uevent:
    - shard-dg1:          NOTRUN -> [SKIP][158] ([i915#7116] / [i915#9424])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-13/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-tglu-1:       NOTRUN -> [SKIP][159] ([i915#3555]) +2 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-offscreen-64x21:
    - shard-mtlp:         NOTRUN -> [SKIP][160] ([i915#8814])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-7/igt@kms_cursor_crc@cursor-offscreen-64x21.html

  * igt@kms_cursor_crc@cursor-onscreen-128x42@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][161] ([i915#13566]) +1 other test fail
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@kms_cursor_crc@cursor-onscreen-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-onscreen-32x10:
    - shard-mtlp:         NOTRUN -> [SKIP][162] ([i915#3555] / [i915#8814]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-3/igt@kms_cursor_crc@cursor-onscreen-32x10.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-tglu-1:       NOTRUN -> [SKIP][163] ([i915#13049])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][164] ([i915#13049])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-1/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
    - shard-rkl:          NOTRUN -> [SKIP][165] ([i915#13049]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
    - shard-dg1:          NOTRUN -> [SKIP][166] ([i915#13049])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-14/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
    - shard-tglu:         NOTRUN -> [SKIP][167] ([i915#13049])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-2/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
    - shard-mtlp:         NOTRUN -> [SKIP][168] ([i915#13049])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-8/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][169] ([i915#13046] / [i915#5354]) +2 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-8/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][170] ([i915#4103] / [i915#4213]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - shard-rkl:          NOTRUN -> [SKIP][171] ([i915#4103]) +1 other test skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - shard-tglu-1:       NOTRUN -> [SKIP][172] ([i915#4103])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - shard-dg1:          NOTRUN -> [SKIP][173] ([i915#4103] / [i915#4213])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-18/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - shard-mtlp:         NOTRUN -> [SKIP][174] ([i915#4213])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
    - shard-mtlp:         NOTRUN -> [SKIP][175] ([i915#9809])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          NOTRUN -> [FAIL][176] ([i915#2346])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-rkl:          NOTRUN -> [SKIP][177] ([i915#13691])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@kms_display_modes@extended-mode-basic.html
    - shard-tglu:         NOTRUN -> [SKIP][178] ([i915#13691])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-10/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][179] ([i915#3804])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-tglu:         NOTRUN -> [SKIP][180] ([i915#13749])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-9/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-dg2:          [PASS][181] -> [SKIP][182] ([i915#13707])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-11/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-8/igt@kms_dp_linktrain_fallback@dp-fallback.html
    - shard-tglu-1:       NOTRUN -> [SKIP][183] ([i915#13707])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-tglu:         NOTRUN -> [SKIP][184] ([i915#3555] / [i915#3840])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-10/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglu:         [PASS][185] -> [ABORT][186] ([i915#14849] / [i915#14871])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-3/igt@kms_fbcon_fbt@fbc-suspend.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-10/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-dg2:          NOTRUN -> [SKIP][187] ([i915#9337])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-5/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr1:
    - shard-tglu:         NOTRUN -> [SKIP][188] ([i915#658])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-2/igt@kms_feature_discovery@psr1.html
    - shard-rkl:          NOTRUN -> [SKIP][189] ([i915#658])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
    - shard-tglu:         NOTRUN -> [SKIP][190] ([i915#3637] / [i915#9934]) +2 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-9/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-tglu-1:       NOTRUN -> [SKIP][191] ([i915#9934])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-tglu-1:       NOTRUN -> [SKIP][192] ([i915#3637] / [i915#9934]) +2 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-glk:          NOTRUN -> [INCOMPLETE][193] ([i915#12745] / [i915#4839])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk6/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][194] ([i915#4839])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk6/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-dg2:          NOTRUN -> [SKIP][195] ([i915#9934]) +3 other tests skip
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-11/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][196] ([i915#9934])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-15/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
    - shard-mtlp:         NOTRUN -> [SKIP][197] ([i915#3637] / [i915#9934])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
    - shard-rkl:          NOTRUN -> [SKIP][198] ([i915#14544] / [i915#9934])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][199] ([i915#9934]) +3 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@flip-vs-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][200] ([i915#8381])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-3/igt@kms_flip@flip-vs-fences.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-tglu:         NOTRUN -> [SKIP][201] ([i915#2672] / [i915#3555]) +4 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][202] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
    - shard-rkl:          NOTRUN -> [SKIP][203] ([i915#14544] / [i915#2672] / [i915#3555])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
    - shard-dg1:          NOTRUN -> [SKIP][204] ([i915#2587] / [i915#2672] / [i915#3555])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
    - shard-tglu:         NOTRUN -> [SKIP][205] ([i915#2587] / [i915#2672] / [i915#3555])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][206] ([i915#14544] / [i915#2672])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html
    - shard-dg1:          NOTRUN -> [SKIP][207] ([i915#2587] / [i915#2672])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][208] ([i915#2672]) +1 other test skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][209] ([i915#2672] / [i915#8813]) +2 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-mtlp:         NOTRUN -> [SKIP][210] ([i915#2672] / [i915#3555] / [i915#8813]) +4 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][211] ([i915#2587] / [i915#2672]) +5 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][212] ([i915#5354]) +8 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html
    - shard-rkl:          NOTRUN -> [SKIP][213] ([i915#14544] / [i915#1825]) +5 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][214] ([i915#8708]) +4 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][215] ([i915#8708]) +5 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
    - shard-tglu:         NOTRUN -> [SKIP][216] +57 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][217] ([i915#8708]) +4 other tests skip
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][218] ([i915#5439])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
    - shard-tglu:         NOTRUN -> [SKIP][219] ([i915#5439]) +1 other test skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-10/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-cpu:
    - shard-dg1:          NOTRUN -> [SKIP][220] ([i915#15102])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][221] ([i915#15104]) +1 other test skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][222] ([i915#15102] / [i915#3458]) +6 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][223] ([i915#1825]) +22 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite:
    - shard-mtlp:         NOTRUN -> [SKIP][224] ([i915#1825]) +11 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-tglu-1:       NOTRUN -> [SKIP][225] ([i915#9766])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][226] ([i915#15102])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][227] ([i915#15102] / [i915#3023]) +11 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html
    - shard-dg1:          NOTRUN -> [SKIP][228] ([i915#15102] / [i915#3458]) +1 other test skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-15/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
    - shard-tglu:         NOTRUN -> [SKIP][229] ([i915#15102]) +18 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-tglu-1:       NOTRUN -> [SKIP][230] +26 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-tglu-1:       NOTRUN -> [SKIP][231] ([i915#15102]) +9 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][232] ([i915#3555] / [i915#8228])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-7/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          [PASS][233] -> [SKIP][234] ([i915#3555] / [i915#8228]) +1 other test skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-11/igt@kms_hdr@static-toggle.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-6/igt@kms_hdr@static-toggle.html
    - shard-tglu:         NOTRUN -> [SKIP][235] ([i915#3555] / [i915#8228]) +1 other test skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-5/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][236] ([i915#3555] / [i915#8228])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-4/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-rkl:          [PASS][237] -> [SKIP][238] ([i915#3555] / [i915#8228]) +1 other test skip
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_hdr@static-toggle-suspend.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-4/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][239] ([i915#10656])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-4/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][240] ([i915#15283])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][241] ([i915#10656] / [i915#12388])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-10/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][242] ([i915#13522])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-xtiled:
    - shard-dg1:          [PASS][243] -> [DMESG-WARN][244] ([i915#4423]) +3 other tests dmesg-warn
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-18/igt@kms_pipe_stress@stress-xrgb8888-xtiled.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-16/igt@kms_pipe_stress@stress-xrgb8888-xtiled.html

  * igt@kms_plane_lowres@tiling-4:
    - shard-mtlp:         NOTRUN -> [SKIP][245] ([i915#10226] / [i915#11614] / [i915#3555] / [i915#8821])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-7/igt@kms_plane_lowres@tiling-4.html

  * igt@kms_plane_lowres@tiling-4@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][246] ([i915#11614] / [i915#3582]) +3 other tests skip
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-7/igt@kms_plane_lowres@tiling-4@pipe-c-edp-1.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-tglu:         NOTRUN -> [SKIP][247] ([i915#13958]) +2 other tests skip
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-9/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-rkl:          NOTRUN -> [SKIP][248] ([i915#13958] / [i915#14544])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-tglu-1:       NOTRUN -> [SKIP][249] ([i915#13958])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-rkl:          NOTRUN -> [SKIP][250] ([i915#5354])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-tglu:         NOTRUN -> [SKIP][251] ([i915#9685])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-10/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-tglu:         NOTRUN -> [SKIP][252] ([i915#3828])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-2/igt@kms_pm_dc@dc5-retention-flops.html
    - shard-mtlp:         NOTRUN -> [SKIP][253] ([i915#3828])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-8/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][254] ([i915#14104])
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-11/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][255] ([i915#15128])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-6/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][256] ([i915#3828])
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          [PASS][257] -> [SKIP][258] ([i915#15073]) +2 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-8/igt@kms_pm_rpm@dpms-lpsp.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-4/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-tglu-1:       NOTRUN -> [SKIP][259] ([i915#15073])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-dg2:          [PASS][260] -> [SKIP][261] ([i915#15073]) +1 other test skip
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-5/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-tglu:         NOTRUN -> [SKIP][262] ([i915#15073])
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-2/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@system-suspend-idle:
    - shard-dg2:          [PASS][263] -> [INCOMPLETE][264] ([i915#14419])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-11/igt@kms_pm_rpm@system-suspend-idle.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-3/igt@kms_pm_rpm@system-suspend-idle.html

  * igt@kms_prime@d3hot:
    - shard-tglu-1:       NOTRUN -> [SKIP][265] ([i915#6524])
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-tglu-1:       NOTRUN -> [SKIP][266] ([i915#11520]) +2 other tests skip
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][267] ([i915#11520]) +5 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk1/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-glk10:        NOTRUN -> [SKIP][268] ([i915#11520]) +4 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-glk10/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
    - shard-dg2:          NOTRUN -> [SKIP][269] ([i915#11520]) +3 other tests skip
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-rkl:          NOTRUN -> [SKIP][270] ([i915#11520]) +5 other tests skip
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
    - shard-snb:          NOTRUN -> [SKIP][271] ([i915#11520]) +1 other test skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-snb7/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
    - shard-mtlp:         NOTRUN -> [SKIP][272] ([i915#12316]) +1 other test skip
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-5/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-tglu:         NOTRUN -> [SKIP][273] ([i915#11520]) +8 other tests skip
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-10/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-rkl:          NOTRUN -> [SKIP][274] ([i915#9683])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-tglu-1:       NOTRUN -> [SKIP][275] ([i915#9683])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-primary-render:
    - shard-rkl:          NOTRUN -> [SKIP][276] ([i915#1072] / [i915#14544] / [i915#9732]) +2 other tests skip
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_psr@fbc-pr-primary-render.html
    - shard-dg1:          NOTRUN -> [SKIP][277] ([i915#1072] / [i915#9732]) +4 other tests skip
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-13/igt@kms_psr@fbc-pr-primary-render.html

  * igt@kms_psr@fbc-psr-primary-page-flip:
    - shard-rkl:          NOTRUN -> [SKIP][278] ([i915#1072] / [i915#9732]) +11 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@kms_psr@fbc-psr-primary-page-flip.html

  * igt@kms_psr@fbc-psr2-primary-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][279] ([i915#9732]) +19 other tests skip
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-3/igt@kms_psr@fbc-psr2-primary-mmap-gtt.html

  * igt@kms_psr@pr-cursor-plane-move:
    - shard-mtlp:         NOTRUN -> [SKIP][280] ([i915#9688]) +7 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-8/igt@kms_psr@pr-cursor-plane-move.html

  * igt@kms_psr@psr-cursor-render:
    - shard-dg2:          NOTRUN -> [SKIP][281] ([i915#1072] / [i915#9732]) +8 other tests skip
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-11/igt@kms_psr@psr-cursor-render.html

  * igt@kms_psr@psr-sprite-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][282] ([i915#9732]) +10 other tests skip
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_psr@psr-sprite-mmap-cpu.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][283] ([i915#5289])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-tglu:         NOTRUN -> [SKIP][284] ([i915#5289])
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg1:          NOTRUN -> [SKIP][285] ([i915#5289])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-14/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@sprite-rotation-270:
    - shard-mtlp:         NOTRUN -> [SKIP][286] ([i915#12755])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-7/igt@kms_rotation_crc@sprite-rotation-270.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-rkl:          NOTRUN -> [SKIP][287] ([i915#3555]) +3 other tests skip
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-tglu:         NOTRUN -> [SKIP][288] ([i915#3555]) +4 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-10/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-dg2:          NOTRUN -> [SKIP][289] ([i915#3555]) +1 other test skip
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-7/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
    - shard-dg1:          NOTRUN -> [SKIP][290] ([i915#3555]) +1 other test skip
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-12/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
    - shard-mtlp:         NOTRUN -> [SKIP][291] ([i915#3555] / [i915#8809])
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-6/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@kms_sharpness_filter@filter-scaler-upscale:
    - shard-dg2:          NOTRUN -> [SKIP][292] ([i915#15232])
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-3/igt@kms_sharpness_filter@filter-scaler-upscale.html

  * igt@kms_sharpness_filter@filter-strength:
    - shard-tglu:         NOTRUN -> [SKIP][293] ([i915#15232]) +2 other tests skip
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-3/igt@kms_sharpness_filter@filter-strength.html

  * igt@kms_sharpness_filter@invalid-filter-with-scaler:
    - shard-tglu-1:       NOTRUN -> [SKIP][294] ([i915#15232]) +1 other test skip
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_sharpness_filter@invalid-filter-with-scaler.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-rkl:          NOTRUN -> [SKIP][295] ([i915#8623]) +1 other test skip
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
    - shard-dg2:          NOTRUN -> [SKIP][296] ([i915#8623])
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-11/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][297] ([i915#15243] / [i915#3555])
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@kms_vrr@flip-dpms.html

  * igt@kms_vrr@negative-basic:
    - shard-dg2:          [PASS][298] -> [SKIP][299] ([i915#3555] / [i915#9906])
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-11/igt@kms_vrr@negative-basic.html
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-1/igt@kms_vrr@negative-basic.html
    - shard-tglu:         NOTRUN -> [SKIP][300] ([i915#3555] / [i915#9906])
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-3/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-tglu:         NOTRUN -> [SKIP][301] ([i915#9906])
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-3/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@kms_writeback@writeback-check-output:
    - shard-tglu:         NOTRUN -> [SKIP][302] ([i915#2437])
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-7/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-dg2:          NOTRUN -> [SKIP][303] ([i915#2437] / [i915#9412])
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-7/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-tglu-1:       NOTRUN -> [SKIP][304] ([i915#2437] / [i915#9412])
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-1/igt@kms_writeback@writeback-pixel-formats.html
    - shard-mtlp:         NOTRUN -> [SKIP][305] ([i915#2437] / [i915#9412])
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-5/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf@unprivileged-single-ctx-counters:
    - shard-rkl:          NOTRUN -> [SKIP][306] ([i915#2433])
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@perf@unprivileged-single-ctx-counters.html

  * igt@perf_pmu@event-wait@rcs0:
    - shard-rkl:          NOTRUN -> [SKIP][307] +15 other tests skip
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@perf_pmu@event-wait@rcs0.html

  * igt@prime_vgem@basic-fence-mmap:
    - shard-dg2:          NOTRUN -> [SKIP][308] ([i915#3708] / [i915#4077])
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-6/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][309] ([i915#3708] / [i915#4077])
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-15/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@basic-read:
    - shard-rkl:          NOTRUN -> [SKIP][310] ([i915#3291] / [i915#3708])
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - shard-dg2:          NOTRUN -> [SKIP][311] ([i915#3291] / [i915#3708])
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-6/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-mtlp:         NOTRUN -> [SKIP][312] ([i915#3708])
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-6/igt@prime_vgem@fence-flip-hang.html

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - shard-tglu:         NOTRUN -> [FAIL][313] ([i915#12910]) +9 other tests fail
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-8/igt@sriov_basic@enable-vfs-autoprobe-on.html
    - shard-mtlp:         NOTRUN -> [FAIL][314] ([i915#12910]) +9 other tests fail
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-mtlp-3/igt@sriov_basic@enable-vfs-autoprobe-on.html

  * igt@sysfs_heartbeat_interval@precise:
    - shard-snb:          NOTRUN -> [SKIP][315] +56 other tests skip
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-snb5/igt@sysfs_heartbeat_interval@precise.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3:
    - shard-rkl:          [INCOMPLETE][316] ([i915#13356]) -> [PASS][317] +1 other test pass
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@gem_ctx_isolation@preservation-s3.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@gem_ctx_isolation@preservation-s3.html

  * igt@gem_softpin@noreloc-s3:
    - shard-rkl:          [INCOMPLETE][318] ([i915#13809]) -> [PASS][319]
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-3/igt@gem_softpin@noreloc-s3.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@gem_softpin@noreloc-s3.html

  * igt@i915_module_load@reload-no-display:
    - shard-dg1:          [DMESG-WARN][320] ([i915#13029] / [i915#14545]) -> [PASS][321]
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-13/igt@i915_module_load@reload-no-display.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-17/igt@i915_module_load@reload-no-display.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-tglu:         [FAIL][322] ([i915#14857]) -> [PASS][323] +1 other test pass
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind:
    - shard-dg1:          [DMESG-WARN][324] ([i915#4423]) -> [PASS][325] +2 other tests pass
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-19/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-16/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-tglu:         [ABORT][326] ([i915#14849] / [i915#14871]) -> [PASS][327] +1 other test pass
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-2/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-tglu:         [INCOMPLETE][328] -> [PASS][329]
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-1.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-2/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-onscreen-64x21:
    - shard-rkl:          [FAIL][330] ([i915#13566]) -> [PASS][331] +1 other test pass
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-7/igt@kms_cursor_crc@cursor-onscreen-64x21.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@kms_cursor_crc@cursor-onscreen-64x21.html

  * igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1:
    - shard-tglu:         [FAIL][332] ([i915#13566]) -> [PASS][333] +1 other test pass
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-10/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-6/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-dg2:          [SKIP][334] ([i915#3555] / [i915#8228]) -> [PASS][335]
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-5/igt@kms_hdr@invalid-metadata-sizes.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-11/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-rkl:          [SKIP][336] ([i915#14544] / [i915#15073]) -> [PASS][337]
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp.html

  
#### Warnings ####

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-rkl:          [SKIP][338] ([i915#9323]) -> [SKIP][339] ([i915#14544] / [i915#9323])
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-5/igt@gem_ccs@block-multicopy-compressed.html
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-rkl:          [SKIP][340] ([i915#14544] / [i915#9323]) -> [SKIP][341] ([i915#9323])
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          [SKIP][342] ([i915#13008]) -> [SKIP][343] ([i915#13008] / [i915#14544])
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-2/igt@gem_ccs@large-ctrl-surf-copy.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          [SKIP][344] ([i915#7697]) -> [SKIP][345] ([i915#14544] / [i915#7697])
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-4/igt@gem_close_race@multigpu-basic-threads.html
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-rkl:          [SKIP][346] ([i915#14544] / [i915#280]) -> [SKIP][347] ([i915#280])
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@gem_ctx_sseu@invalid-sseu.html
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_exec_reloc@basic-gtt-read:
    - shard-rkl:          [SKIP][348] ([i915#3281]) -> [SKIP][349] ([i915#14544] / [i915#3281]) +5 other tests skip
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-3/igt@gem_exec_reloc@basic-gtt-read.html
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-read.html

  * igt@gem_exec_reloc@basic-write-read:
    - shard-rkl:          [SKIP][350] ([i915#14544] / [i915#3281]) -> [SKIP][351] ([i915#3281]) +5 other tests skip
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@gem_exec_reloc@basic-write-read.html
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-4/igt@gem_exec_reloc@basic-write-read.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-rkl:          [SKIP][352] ([i915#4613] / [i915#7582]) -> [SKIP][353] ([i915#14544] / [i915#4613] / [i915#7582])
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-5/igt@gem_lmem_evict@dontneed-evict-race.html
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-rkl:          [SKIP][354] ([i915#4613]) -> [SKIP][355] ([i915#14544] / [i915#4613]) +1 other test skip
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-7/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-rkl:          [SKIP][356] ([i915#14544] / [i915#4613]) -> [SKIP][357] ([i915#4613])
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@gem_lmem_swapping@parallel-random.html
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-rkl:          [SKIP][358] ([i915#14544] / [i915#3282]) -> [SKIP][359] ([i915#3282]) +3 other tests skip
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@gem_partial_pwrite_pread@reads-uncached.html
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-rkl:          [SKIP][360] ([i915#13717]) -> [SKIP][361] ([i915#13717] / [i915#14544])
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-3/igt@gem_pxp@hw-rejects-pxp-context.html
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-rkl:          [SKIP][362] ([i915#14544] / [i915#8411]) -> [SKIP][363] ([i915#8411])
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-4/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_set_tiling_vs_pwrite:
    - shard-rkl:          [SKIP][364] ([i915#3282]) -> [SKIP][365] ([i915#14544] / [i915#3282]) +3 other tests skip
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-1/igt@gem_set_tiling_vs_pwrite.html
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_set_tiling_vs_pwrite.html

  * igt@gem_softpin@evict-snoop:
    - shard-rkl:          [SKIP][366] ([i915#14544]) -> [SKIP][367] +9 other tests skip
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@gem_softpin@evict-snoop.html
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@gem_softpin@evict-snoop.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-rkl:          [SKIP][368] ([i915#3297]) -> [SKIP][369] ([i915#14544] / [i915#3297])
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-2/igt@gem_userptr_blits@coherency-sync.html
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-rkl:          [SKIP][370] ([i915#14544] / [i915#3297]) -> [SKIP][371] ([i915#3297]) +2 other tests skip
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@gem_userptr_blits@dmabuf-unsync.html
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@relocations:
    - shard-rkl:          [SKIP][372] ([i915#3281] / [i915#3297]) -> [SKIP][373] ([i915#14544] / [i915#3281] / [i915#3297])
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-5/igt@gem_userptr_blits@relocations.html
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gem_userptr_blits@relocations.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-rkl:          [SKIP][374] ([i915#14544] / [i915#2527]) -> [SKIP][375] ([i915#2527])
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@gen9_exec_parse@batch-invalid-length.html
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-rkl:          [SKIP][376] ([i915#2527]) -> [SKIP][377] ([i915#14544] / [i915#2527])
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-5/igt@gen9_exec_parse@secure-batches.html
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@gen9_exec_parse@secure-batches.html

  * igt@i915_power@sanity:
    - shard-rkl:          [SKIP][378] ([i915#14544] / [i915#7984]) -> [SKIP][379] ([i915#7984])
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@i915_power@sanity.html
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@i915_power@sanity.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - shard-rkl:          [SKIP][380] ([i915#5286]) -> [SKIP][381] ([i915#14544] / [i915#5286]) +3 other tests skip
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-2/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-dg1:          [SKIP][382] ([i915#4423] / [i915#4538] / [i915#5286]) -> [SKIP][383] ([i915#4538] / [i915#5286])
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-18/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-16/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - shard-dg1:          [SKIP][384] ([i915#4538] / [i915#5286]) -> [SKIP][385] ([i915#4423] / [i915#4538] / [i915#5286])
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-18/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-19/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-rkl:          [SKIP][386] ([i915#14544] / [i915#5286]) -> [SKIP][387] ([i915#5286]) +2 other tests skip
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-rkl:          [SKIP][388] ([i915#14544] / [i915#3638]) -> [SKIP][389] ([i915#3638]) +1 other test skip
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-rkl:          [SKIP][390] ([i915#3638]) -> [SKIP][391] ([i915#14544] / [i915#3638])
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-3/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][392] ([i915#6095]) -> [SKIP][393] ([i915#14544] / [i915#6095]) +9 other tests skip
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-1/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-2.html
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][394] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][395] ([i915#14098] / [i915#6095]) +15 other tests skip
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2.html
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][396] ([i915#12313]) -> [SKIP][397] ([i915#12313] / [i915#14544]) +2 other tests skip
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-7/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][398] ([i915#12313] / [i915#14544]) -> [SKIP][399] ([i915#12313])
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][400] ([i915#12805]) -> [SKIP][401] ([i915#12805] / [i915#14544])
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][402] ([i915#14098] / [i915#6095]) -> [SKIP][403] ([i915#14098] / [i915#14544] / [i915#6095]) +11 other tests skip
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-dg1:          [SKIP][404] ([i915#12313] / [i915#4423]) -> [SKIP][405] ([i915#12313])
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-16/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-15/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][406] ([i915#14544] / [i915#6095]) -> [SKIP][407] ([i915#6095]) +13 other tests skip
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-rkl:          [SKIP][408] ([i915#3742]) -> [SKIP][409] ([i915#14544] / [i915#3742])
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-2/igt@kms_cdclk@mode-transition-all-outputs.html
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-rkl:          [SKIP][410] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][411] ([i915#11151] / [i915#7828]) +2 other tests skip
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-3/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-dg1:          [SKIP][412] ([i915#11151] / [i915#7828]) -> [SKIP][413] ([i915#11151] / [i915#4423] / [i915#7828])
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-18/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-14/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
    - shard-rkl:          [SKIP][414] ([i915#11151] / [i915#7828]) -> [SKIP][415] ([i915#11151] / [i915#14544] / [i915#7828]) +4 other tests skip
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-4/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-rkl:          [SKIP][416] ([i915#14544] / [i915#3116]) -> [SKIP][417] ([i915#3116])
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_content_protection@dp-mst-lic-type-1.html
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-rkl:          [SKIP][418] ([i915#3116]) -> [SKIP][419] ([i915#14544] / [i915#3116])
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-3/igt@kms_content_protection@dp-mst-type-1.html
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          [FAIL][420] ([i915#7173]) -> [SKIP][421] ([i915#7118] / [i915#9424])
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-11/igt@kms_content_protection@legacy.html
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-8/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          [SKIP][422] ([i915#9424]) -> [SKIP][423] ([i915#9433])
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-17/igt@kms_content_protection@mei-interface.html
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-12/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@type1:
    - shard-dg2:          [SKIP][424] ([i915#7118] / [i915#9424]) -> [SKIP][425] ([i915#7118] / [i915#7162] / [i915#9424])
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-1/igt@kms_content_protection@type1.html
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-11/igt@kms_content_protection@type1.html

  * igt@kms_content_protection@uevent:
    - shard-dg2:          [FAIL][426] ([i915#1339] / [i915#7173]) -> [SKIP][427] ([i915#7118] / [i915#9424])
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-11/igt@kms_content_protection@uevent.html
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-7/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-rkl:          [SKIP][428] ([i915#14544] / [i915#3555]) -> [SKIP][429] ([i915#3555])
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-32x32.html
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-rkl:          [SKIP][430] ([i915#13049]) -> [SKIP][431] ([i915#13049] / [i915#14544])
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-2/igt@kms_cursor_crc@cursor-offscreen-512x512.html
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-offscreen-max-size:
    - shard-rkl:          [SKIP][432] ([i915#3555]) -> [SKIP][433] ([i915#14544] / [i915#3555]) +1 other test skip
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-5/igt@kms_cursor_crc@cursor-offscreen-max-size.html
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-max-size.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-rkl:          [SKIP][434] ([i915#13049] / [i915#14544]) -> [SKIP][435] ([i915#13049])
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_cursor_crc@cursor-random-512x170.html
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-3/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-rkl:          [SKIP][436] -> [SKIP][437] ([i915#14544]) +12 other tests skip
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-rkl:          [SKIP][438] ([i915#14544] / [i915#9067]) -> [SKIP][439] ([i915#9067])
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-rkl:          [SKIP][440] ([i915#4103]) -> [SKIP][441] ([i915#14544] / [i915#4103])
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-rkl:          [SKIP][442] ([i915#9723]) -> [SKIP][443] ([i915#14544] / [i915#9723])
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-8/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_aux_dev:
    - shard-rkl:          [SKIP][444] ([i915#1257] / [i915#14544]) -> [SKIP][445] ([i915#1257])
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_dp_aux_dev.html
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-2/igt@kms_dp_aux_dev.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-rkl:          [SKIP][446] ([i915#13748]) -> [SKIP][447] ([i915#13748] / [i915#14544])
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-7/igt@kms_dp_link_training@uhbr-sst.html
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-dg1:          [SKIP][448] ([i915#13707] / [i915#4423]) -> [SKIP][449] ([i915#13707])
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-18/igt@kms_dp_linktrain_fallback@dsc-fallback.html
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-12/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-rkl:          [SKIP][450] ([i915#14544] / [i915#3840]) -> [SKIP][451] ([i915#3840])
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp.html
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-rkl:          [SKIP][452] ([i915#3840]) -> [SKIP][453] ([i915#14544] / [i915#3840])
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_feature_discovery@display-2x:
    - shard-rkl:          [SKIP][454] ([i915#1839]) -> [SKIP][455] ([i915#14544] / [i915#1839])
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-5/igt@kms_feature_discovery@display-2x.html
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-rkl:          [SKIP][456] ([i915#9337]) -> [SKIP][457] ([i915#14544] / [i915#9337])
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-4/igt@kms_feature_discovery@dp-mst.html
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-rkl:          [SKIP][458] ([i915#9934]) -> [SKIP][459] ([i915#14544] / [i915#9934]) +3 other tests skip
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-5/igt@kms_flip@2x-absolute-wf_vblank.html
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible:
    - shard-rkl:          [SKIP][460] ([i915#14544] / [i915#9934]) -> [SKIP][461] ([i915#9934]) +4 other tests skip
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-rkl:          [SKIP][462] ([i915#14544] / [i915#2672] / [i915#3555]) -> [SKIP][463] ([i915#2672] / [i915#3555]) +2 other tests skip
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
    - shard-rkl:          [SKIP][464] ([i915#14544] / [i915#2672]) -> [SKIP][465] ([i915#2672]) +2 other tests skip
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
   [465]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-rkl:          [SKIP][466] ([i915#2672] / [i915#3555]) -> [SKIP][467] ([i915#14544] / [i915#2672] / [i915#3555]) +1 other test skip
   [466]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html
   [467]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
    - shard-rkl:          [SKIP][468] ([i915#2672]) -> [SKIP][469] ([i915#14544] / [i915#2672]) +1 other test skip
   [468]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
   [469]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][470] ([i915#1825]) -> [SKIP][471] ([i915#14544] / [i915#1825]) +22 other tests skip
   [470]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
   [471]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render:
    - shard-dg1:          [SKIP][472] ([i915#15102] / [i915#4423]) -> [SKIP][473] ([i915#15102])
   [472]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render.html
   [473]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt:
    - shard-rkl:          [SKIP][474] ([i915#15102]) -> [SKIP][475] ([i915#14544] / [i915#15102]) +4 other tests skip
   [474]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt.html
   [475]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-rkl:          [SKIP][476] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][477] ([i915#15102] / [i915#3023]) +5 other tests skip
   [476]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [477]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-dg1:          [SKIP][478] ([i915#15102] / [i915#3458]) -> [SKIP][479] ([i915#15102] / [i915#3458] / [i915#4423])
   [478]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-19/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [479]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move:
    - shard-rkl:          [SKIP][480] ([i915#15102] / [i915#3023]) -> [SKIP][481] ([i915#14544] / [i915#15102] / [i915#3023]) +6 other tests skip
   [480]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html
   [481]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
    - shard-dg1:          [SKIP][482] ([i915#4423]) -> [SKIP][483]
   [482]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
   [483]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-dg2:          [SKIP][484] ([i915#15102] / [i915#3458]) -> [SKIP][485] ([i915#10433] / [i915#15102] / [i915#3458]) +1 other test skip
   [484]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [485]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt:
    - shard-rkl:          [SKIP][486] ([i915#14544] / [i915#15102]) -> [SKIP][487] ([i915#15102]) +2 other tests skip
   [486]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html
   [487]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-dg2:          [SKIP][488] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][489] ([i915#15102] / [i915#3458]) +2 other tests skip
   [488]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
   [489]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
    - shard-dg1:          [SKIP][490] -> [SKIP][491] ([i915#4423])
   [490]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html
   [491]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][492] ([i915#14544] / [i915#1825]) -> [SKIP][493] ([i915#1825]) +18 other tests skip
   [492]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html
   [493]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-rkl:          [SKIP][494] ([i915#12713]) -> [SKIP][495] ([i915#1187] / [i915#12713])
   [494]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-4/igt@kms_hdr@brightness-with-hdr.html
   [495]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-3/igt@kms_hdr@brightness-with-hdr.html
    - shard-tglu:         [SKIP][496] ([i915#1187] / [i915#12713]) -> [SKIP][497] ([i915#12713])
   [496]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-tglu-2/igt@kms_hdr@brightness-with-hdr.html
   [497]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-tglu-5/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-hdr:
    - shard-rkl:          [SKIP][498] ([i915#3555] / [i915#8228]) -> [SKIP][499] ([i915#14544] / [i915#3555] / [i915#8228])
   [498]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-7/igt@kms_hdr@invalid-hdr.html
   [499]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-rkl:          [SKIP][500] ([i915#10656] / [i915#14544]) -> [SKIP][501] ([i915#10656])
   [500]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_joiner@invalid-modeset-big-joiner.html
   [501]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          [SKIP][502] ([i915#6301]) -> [SKIP][503] ([i915#14544] / [i915#6301])
   [502]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-1/igt@kms_panel_fitting@legacy.html
   [503]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_stress@stress-xrgb8888-4tiled:
    - shard-rkl:          [SKIP][504] ([i915#14712]) -> [SKIP][505] ([i915#14544] / [i915#14712])
   [504]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-4/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html
   [505]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-rkl:          [SKIP][506] ([i915#13958]) -> [SKIP][507] ([i915#13958] / [i915#14544])
   [506]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-5/igt@kms_plane_multiple@2x-tiling-none.html
   [507]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-rkl:          [SKIP][508] ([i915#14259] / [i915#14544]) -> [SKIP][509] ([i915#14259])
   [508]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_plane_multiple@tiling-yf.html
   [509]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a:
    - shard-rkl:          [SKIP][510] ([i915#12247]) -> [SKIP][511] ([i915#12247] / [i915#14544]) +3 other tests skip
   [510]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-1/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html
   [511]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-rkl:          [SKIP][512] ([i915#5354]) -> [SKIP][513] ([i915#14544] / [i915#5354])
   [512]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-3/igt@kms_pm_backlight@basic-brightness.html
   [513]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-dg1:          [SKIP][514] ([i915#12343]) -> [SKIP][515] ([i915#12343] / [i915#4423])
   [514]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-14/igt@kms_pm_backlight@brightness-with-dpms.html
   [515]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-13/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-rkl:          [SKIP][516] ([i915#14544] / [i915#5354]) -> [SKIP][517] ([i915#5354])
   [516]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_pm_backlight@fade-with-dpms.html
   [517]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-5/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg1:          [SKIP][518] ([i915#15073]) -> [SKIP][519] ([i915#15073] / [i915#4423])
   [518]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-13/igt@kms_pm_rpm@dpms-lpsp.html
   [519]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-15/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-rkl:          [SKIP][520] ([i915#14544] / [i915#15073]) -> [SKIP][521] ([i915#15073])
   [520]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [521]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-rkl:          [SKIP][522] ([i915#11520]) -> [SKIP][523] ([i915#11520] / [i915#14544]) +5 other tests skip
   [522]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-8/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html
   [523]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
    - shard-rkl:          [SKIP][524] ([i915#11520] / [i915#14544]) -> [SKIP][525] ([i915#11520]) +4 other tests skip
   [524]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
   [525]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-8/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-rkl:          [SKIP][526] ([i915#9683]) -> [SKIP][527] ([i915#14544] / [i915#9683])
   [526]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-7/igt@kms_psr2_su@page_flip-p010.html
   [527]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-pr-cursor-plane-move:
    - shard-rkl:          [SKIP][528] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][529] ([i915#1072] / [i915#9732]) +6 other tests skip
   [528]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_psr@fbc-pr-cursor-plane-move.html
   [529]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-3/igt@kms_psr@fbc-pr-cursor-plane-move.html

  * igt@kms_psr@pr-cursor-render:
    - shard-rkl:          [SKIP][530] ([i915#1072] / [i915#9732]) -> [SKIP][531] ([i915#1072] / [i915#14544] / [i915#9732]) +7 other tests skip
   [530]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-5/igt@kms_psr@pr-cursor-render.html
   [531]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_psr@pr-cursor-render.html

  * igt@kms_psr@psr-primary-render:
    - shard-dg1:          [SKIP][532] ([i915#1072] / [i915#9732]) -> [SKIP][533] ([i915#1072] / [i915#4423] / [i915#9732])
   [532]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-17/igt@kms_psr@psr-primary-render.html
   [533]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-14/igt@kms_psr@psr-primary-render.html

  * igt@kms_psr@psr2-no-drrs:
    - shard-dg1:          [SKIP][534] ([i915#1072] / [i915#4423] / [i915#9732]) -> [SKIP][535] ([i915#1072] / [i915#9732])
   [534]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-dg1-16/igt@kms_psr@psr2-no-drrs.html
   [535]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-dg1-17/igt@kms_psr@psr2-no-drrs.html

  * igt@kms_sharpness_filter@filter-dpms:
    - shard-rkl:          [SKIP][536] ([i915#15232]) -> [SKIP][537] ([i915#14544] / [i915#15232]) +1 other test skip
   [536]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-1/igt@kms_sharpness_filter@filter-dpms.html
   [537]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_sharpness_filter@filter-dpms.html

  * igt@kms_sharpness_filter@invalid-filter-with-scaler:
    - shard-rkl:          [SKIP][538] ([i915#14544] / [i915#15232]) -> [SKIP][539] ([i915#15232])
   [538]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@kms_sharpness_filter@invalid-filter-with-scaler.html
   [539]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-3/igt@kms_sharpness_filter@invalid-filter-with-scaler.html

  * igt@kms_vrr@negative-basic:
    - shard-rkl:          [SKIP][540] ([i915#3555] / [i915#9906]) -> [SKIP][541] ([i915#14544] / [i915#3555] / [i915#9906])
   [540]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-3/igt@kms_vrr@negative-basic.html
   [541]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@kms_vrr@negative-basic.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-rkl:          [SKIP][542] ([i915#2435]) -> [SKIP][543] ([i915#14544] / [i915#2435])
   [542]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-7/igt@perf@per-context-mode-unprivileged.html
   [543]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-6/igt@perf@per-context-mode-unprivileged.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each:
    - shard-rkl:          [SKIP][544] ([i915#14544] / [i915#9917]) -> [SKIP][545] ([i915#9917])
   [544]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17576/shard-rkl-6/igt@sriov_basic@enable-vfs-bind-unbind-each.html
   [545]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/shard-rkl-7/igt@sriov_basic@enable-vfs-bind-unbind-each.html

  
  [i915#10226]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10226
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11614]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11614
  [i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12796]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12796
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13029
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
  [i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13790
  [i915#13809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13809
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14104
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14419]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14419
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14545
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#14785]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14785
  [i915#14849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14849
  [i915#14857]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14857
  [i915#14871]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14871
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
  [i915#15128]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15128
  [i915#15232]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15232
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15283]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15283
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
  [i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3582
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6187
  [i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7162
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
  [i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
  [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
  [i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
  [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
  [i915#9979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9979


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8636 -> IGTPW_14091
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_17576: 3d718db04a365cc44a3bc81ffa4db7bbd2e645d7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_14091: 14091
  IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_14091/index.html

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