PATCH: Fixup comment about alignment for BLT in Mesa

PATCH: Fixup comment about alignment for BLT in Mesa

[Peter Clifton]

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-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)

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>From 18072c138b7cca626f8b45dfae2c6cb29a91aaf8 Mon Sep 17 00:00:00 2001
From: Peter Clifton <pcjc2@cam.ac.uk>
Date: Tue, 9 Nov 2010 21:45:23 +0000
Subject: [PATCH] drm/intel: Add assert check for blitting alignment.

Also fixup code comment to reflect that the GPU requires DWORD alignment,
but in this case does not actually pass the value "in DWORDs" as I
previously stated.
---
 src/mesa/drivers/dri/intel/intel_blit.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 7118898..c2917e9 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -483,8 +483,8 @@ intel_emit_linear_blit(struct intel_context *intel,
    /* Blits are in a different ringbuffer so we don't use them. */
    assert(intel->gen < 6);
 
-   /* The pitch hits the GPU as a is a signed value, IN DWORDs.
-    * But we want width to match pitch. Max width is (1 << 15 - 1),
+   /* The pitch given to the GPU must be DWORD aligned, and
+    * we want width to match pitch. Max width is (1 << 15 - 1),
     * rounding that down to the nearest DWORD is 1 << 15 - 4
     */
    pitch = MIN2(size, (1 << 15) - 4);
@@ -502,6 +502,7 @@ intel_emit_linear_blit(struct intel_context *intel,
    dst_offset += pitch * height;
    size -= pitch * height;
    assert (size < (1 << 15));
+   assert ((size & 3) == 0); /* Pitch must be DWORD aligned */
    if (size != 0) {
       ok = intelEmitCopyBlit(intel, 1,
 			     size, src_bo, src_offset, I915_TILING_NONE,
-- 
1.7.1


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