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From: Ben Widawsky <ben@bwidawsk.net>
To: intel-gfx@lists.freedesktop.org
Cc: Ben Widawsky <ben@bwidawsk.net>
Subject: [PATCH 3/4] drm/i915: ILK also needs that last fix
Date: Wed,  3 Oct 2012 19:34:23 -0700	[thread overview]
Message-ID: <1349318064-22051-3-git-send-email-ben@bwidawsk.net> (raw)
In-Reply-To: <1349318064-22051-1-git-send-email-ben@bwidawsk.net>

That fix was the disable render deptch cache pipeline flush

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f1800ca..8aafa45 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3338,6 +3338,8 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(WM2_LP_ILK, 0);
 	I915_WRITE(WM1_LP_ILK, 0);
 
+	I915_WRITE(CACHE_MODE_0,
+		   _MASKED_BIT_ENABLE(CM0_RC_PIPELINE_FLUSH_DISABLE));
 	/*
 	 * Based on the document from hardware guys the following bits
 	 * should be set unconditionally in order to enable FBC.
-- 
1.7.12.2

  parent reply	other threads:[~2012-10-04  2:35 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-04  2:34 [PATCH 1/4] drm/i915: Remove duplicate cache workaround Ben Widawsky
2012-10-04  2:34 ` [PATCH 2/4] drm/i915: Disable render depth cache pipeline flush Ben Widawsky
2012-10-04  2:34 ` Ben Widawsky [this message]
2012-10-15 18:59   ` [PATCH 3/4] drm/i915: ILK also needs that last fix Daniel Vetter
2012-10-16  3:21     ` Ben Widawsky
2012-10-16  7:16       ` Daniel Vetter
2012-10-04  2:34 ` [PATCH 4/4] drm/i915: Fix GT_MODE default value Ben Widawsky
2012-10-04 11:25   ` Daniel Vetter
2012-10-04  7:01 ` [PATCH 1/4] drm/i915: Remove duplicate cache workaround Daniel Vetter
2012-10-04 14:55   ` Ben Widawsky
2012-10-05  0:14   ` Ben Widawsky

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