From: Daniel Vetter <daniel@ffwll.ch>
To: Ben Widawsky <ben@bwidawsk.net>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/4] drm/i915: Fix GT_MODE default value
Date: Thu, 4 Oct 2012 13:25:08 +0200 [thread overview]
Message-ID: <20121004112508.GE5661@phenom.ffwll.local> (raw)
In-Reply-To: <1349318064-22051-4-git-send-email-ben@bwidawsk.net>
On Wed, Oct 03, 2012 at 07:34:24PM -0700, Ben Widawsky wrote:
> I can't even find how I figured this might be needed anymore. But sure
> enough, the value I'm reading back on platforms doesn't match what the
> docs recommends.
>
> It seemed to fix Chris' GT1 in limited testing as well.
>
> Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Merged to -fixes, with the missing sob line forged.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 37e62e0..4c1f461 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -531,6 +531,9 @@
> # define VS_TIMER_DISPATCH (1 << 6)
> # define MI_FLUSH_ENABLE (1 << 12)
>
> +#define GEN6_GT_MODE 0x20d0
> +#define GEN6_GT_MODE_HI (1 << 9)
> +
> #define GFX_MODE 0x02520
> #define GFX_MODE_GEN7 0x0229c
> #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8aafa45..e0574f9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3446,6 +3446,11 @@ static void gen6_init_clock_gating(struct drm_device *dev)
> DISPPLANE_TRICKLE_FEED_DISABLE);
> intel_flush_display_plane(dev_priv, pipe);
> }
> +
> + /* The default value should be 0x200 according to docs, but the two
> + * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
> + I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
> + I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
> }
>
> static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
> --
> 1.7.12.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2012-10-04 11:24 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-04 2:34 [PATCH 1/4] drm/i915: Remove duplicate cache workaround Ben Widawsky
2012-10-04 2:34 ` [PATCH 2/4] drm/i915: Disable render depth cache pipeline flush Ben Widawsky
2012-10-04 2:34 ` [PATCH 3/4] drm/i915: ILK also needs that last fix Ben Widawsky
2012-10-15 18:59 ` Daniel Vetter
2012-10-16 3:21 ` Ben Widawsky
2012-10-16 7:16 ` Daniel Vetter
2012-10-04 2:34 ` [PATCH 4/4] drm/i915: Fix GT_MODE default value Ben Widawsky
2012-10-04 11:25 ` Daniel Vetter [this message]
2012-10-04 7:01 ` [PATCH 1/4] drm/i915: Remove duplicate cache workaround Daniel Vetter
2012-10-04 14:55 ` Ben Widawsky
2012-10-05 0:14 ` Ben Widawsky
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