From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 01/14] drm/i915: add TRANSCODER_EDP
Date: Thu, 18 Oct 2012 18:21:31 -0300 [thread overview]
Message-ID: <1350595304-18237-2-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1350595304-18237-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Before Haswell we used to have the CPU pipes and the PCH transcoders.
We had the same amount of pipes and transcoders, and there was a 1:1
mapping between them. After Haswell what we used to call CPU pipe was
split into CPU pipe and CPU transcoder. So now we have 3 CPU pipes (A,
B and C), 4 CPU transcoders (A, B, C and EDP) and 1 PCH transcoder
(only used for VGA).
For all the outputs except for EDP we have an 1:1 mapping on the CPU
pipes and CPU transcoders, so if you're using CPU pipe A you have to
use CPU transcoder A. When have an eDP output you have to use
transcoder EDP and you can attach this CPU transcoder to any of the 3
CPU pipes. When using VGA you need to select a pair of matching CPU
pipes/transcoders (A/A, B/B, C/C) and you also need to enable/use the
PCH transcoder.
For now we're just creating the cpu_transcoder definitions and setting
cpu_transcoder to TRANSCODER_EDP on DDI eDP code, but none of the
registers was ported to use transcoder instead of pipe. The goal is to
keep the code backwards-compatible since on all cases except when
using eDP we must have pipe == cpu_transcoder.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
4 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4728d30..922ab8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -58,6 +58,14 @@ enum pipe {
};
#define pipe_name(p) ((p) + 'A')
+enum transcoder {
+ TRANSCODER_A = 0,
+ TRANSCODER_B,
+ TRANSCODER_C,
+ TRANSCODER_EDP = 0xF,
+};
+#define transcoder_name(t) ((t) + 'A')
+
enum plane {
PLANE_A = 0,
PLANE_B,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c31ee5b..c3fd536 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,6 +26,7 @@
#define _I915_REG_H_
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c2c219b..6bf5ea8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -927,6 +927,15 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
return true;
}
+enum transcoder pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ return intel_crtc->cpu_transcoder;
+}
+
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3336,6 +3345,9 @@ static void ironlake_crtc_off(struct drm_crtc *crtc)
static void haswell_crtc_off(struct drm_crtc *crtc)
{
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ intel_crtc->cpu_transcoder = intel_crtc->pipe;
intel_ddi_put_crtc_pll(crtc);
}
@@ -5212,6 +5224,11 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
num_connectors++;
}
+ if (is_cpu_edp)
+ intel_crtc->cpu_transcoder = TRANSCODER_EDP;
+ else
+ intel_crtc->cpu_transcoder = pipe;
+
/* We are not sure yet this won't happen. */
WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
INTEL_PCH_TYPE(dev));
@@ -7770,6 +7787,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
/* Swap pipes & planes for FBC on pre-965 */
intel_crtc->pipe = pipe;
intel_crtc->plane = pipe;
+ intel_crtc->cpu_transcoder = pipe;
if (IS_MOBILE(dev) && IS_GEN3(dev)) {
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
intel_crtc->plane = !pipe;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 95cbd67..8f6eee5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -185,6 +185,7 @@ struct intel_crtc {
struct drm_crtc base;
enum pipe pipe;
enum plane plane;
+ enum transcoder cpu_transcoder;
u8 lut_r[256], lut_g[256], lut_b[256];
/*
* Whether the crtc and the connected output pipeline is active. Implies
@@ -491,6 +492,8 @@ extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
struct drm_crtc *crtc);
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+extern enum transcoder pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
+ enum pipe pipe);
extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
--
1.7.11.4
next prev parent reply other threads:[~2012-10-18 21:22 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-18 21:21 [PATCH 00/14] Haswell eDP enablement Paulo Zanoni
2012-10-18 21:21 ` Paulo Zanoni [this message]
2012-10-18 22:00 ` [PATCH 01/14] drm/i915: add TRANSCODER_EDP Daniel Vetter
2012-10-18 21:21 ` [PATCH 02/14] drm/i915: convert PIPE_CLK_SEL to transcoder Paulo Zanoni
2012-10-18 21:21 ` [PATCH 03/14] drm/i915: convert DDI_FUNC_CTL " Paulo Zanoni
2012-10-18 21:21 ` [PATCH 04/14] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state Paulo Zanoni
2012-10-18 22:02 ` Daniel Vetter
2012-10-19 19:30 ` Paulo Zanoni
2012-10-18 21:21 ` [PATCH 05/14] drm/i915: convert PIPECONF to use transcoder instead of pipe Paulo Zanoni
2012-10-18 22:23 ` Daniel Vetter
2012-10-19 18:36 ` Paulo Zanoni
2012-10-18 21:21 ` [PATCH 06/14] drm/i915: convert PIPE_MSA_MISC to transcoder Paulo Zanoni
2012-10-18 21:21 ` [PATCH 07/14] drm/i915: convert CPU M/N timings " Paulo Zanoni
2012-10-18 22:25 ` Daniel Vetter
2012-10-18 21:21 ` [PATCH 08/14] drm/i915: convert pipe timing definitions " Paulo Zanoni
2012-10-18 22:29 ` Daniel Vetter
2012-10-18 21:21 ` [PATCH 09/14] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP Paulo Zanoni
2012-10-18 21:21 ` [PATCH 10/14] drm/i915: select the correct pipe " Paulo Zanoni
2012-10-18 21:21 ` [PATCH 11/14] drm/i915: set the correct eDP aux channel clock divider on DDI Paulo Zanoni
2012-10-18 21:21 ` [PATCH 12/14] drm/i915: set/unset the DDI eDP backlight Paulo Zanoni
2012-10-18 21:21 ` [PATCH 13/14] drm/i915: turn the eDP DDI panel on/off Paulo Zanoni
2012-10-18 21:21 ` [PATCH 14/14] drm/i915: enable DDI eDP Paulo Zanoni
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