* [PATCH v2] drm/i915: Fix pipe enabled mask for pipe C in WM calculations @ 2013-03-21 9:41 ville.syrjala 2013-03-21 9:52 ` Chris Wilson 0 siblings, 1 reply; 6+ messages in thread From: ville.syrjala @ 2013-03-21 9:41 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Fix the incorrect enabled pipes mask for pipe C in the WM calculations. Additionally, in an effort to make the code easier to understand, populate the mask with 1 << PIPE_[ABC] instead of raw numbers. v2: Use 1 << PIPE_[ABC] (ickle/danvet) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8a3d89e..0bff282 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1305,13 +1305,13 @@ static void valleyview_update_wm(struct drm_device *dev) &valleyview_wm_info, latency_ns, &valleyview_cursor_wm_info, latency_ns, &planea_wm, &cursora_wm)) - enabled |= 1; + enabled |= 1 << PIPE_A; if (g4x_compute_wm0(dev, 1, &valleyview_wm_info, latency_ns, &valleyview_cursor_wm_info, latency_ns, &planeb_wm, &cursorb_wm)) - enabled |= 2; + enabled |= 1 << PIPE_B; if (single_plane_enabled(enabled) && g4x_compute_srwm(dev, ffs(enabled) - 1, @@ -1361,13 +1361,13 @@ static void g4x_update_wm(struct drm_device *dev) &g4x_wm_info, latency_ns, &g4x_cursor_wm_info, latency_ns, &planea_wm, &cursora_wm)) - enabled |= 1; + enabled |= 1 << PIPE_A; if (g4x_compute_wm0(dev, 1, &g4x_wm_info, latency_ns, &g4x_cursor_wm_info, latency_ns, &planeb_wm, &cursorb_wm)) - enabled |= 2; + enabled |= 1 << PIPE_B; if (single_plane_enabled(enabled) && g4x_compute_srwm(dev, ffs(enabled) - 1, @@ -1727,7 +1727,7 @@ static void ironlake_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe A -" " plane %d, " "cursor: %d\n", plane_wm, cursor_wm); - enabled |= 1; + enabled |= 1 << PIPE_A; } if (g4x_compute_wm0(dev, 1, @@ -1741,7 +1741,7 @@ static void ironlake_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe B -" " plane %d, cursor: %d\n", plane_wm, cursor_wm); - enabled |= 2; + enabled |= 1 << PIPE_B; } /* @@ -1812,7 +1812,7 @@ static void sandybridge_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe A -" " plane %d, " "cursor: %d\n", plane_wm, cursor_wm); - enabled |= 1; + enabled |= 1 << PIPE_A; } if (g4x_compute_wm0(dev, 1, @@ -1826,7 +1826,7 @@ static void sandybridge_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe B -" " plane %d, cursor: %d\n", plane_wm, cursor_wm); - enabled |= 2; + enabled |= 1 << PIPE_B; } /* @@ -1915,7 +1915,7 @@ static void ivybridge_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe A -" " plane %d, " "cursor: %d\n", plane_wm, cursor_wm); - enabled |= 1; + enabled |= 1 << PIPE_A; } if (g4x_compute_wm0(dev, 1, @@ -1929,7 +1929,7 @@ static void ivybridge_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe B -" " plane %d, cursor: %d\n", plane_wm, cursor_wm); - enabled |= 2; + enabled |= 1 << PIPE_B; } if (g4x_compute_wm0(dev, 2, @@ -1943,7 +1943,7 @@ static void ivybridge_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe C -" " plane %d, cursor: %d\n", plane_wm, cursor_wm); - enabled |= 3; + enabled |= 1 << PIPE_C; } /* -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915: Fix pipe enabled mask for pipe C in WM calculations 2013-03-21 9:41 [PATCH v2] drm/i915: Fix pipe enabled mask for pipe C in WM calculations ville.syrjala @ 2013-03-21 9:52 ` Chris Wilson 2013-03-21 11:10 ` [PATCH v3] " ville.syrjala 0 siblings, 1 reply; 6+ messages in thread From: Chris Wilson @ 2013-03-21 9:52 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Thu, Mar 21, 2013 at 11:41:45AM +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Fix the incorrect enabled pipes mask for pipe C in the WM calculations. > > Additionally, in an effort to make the code easier to understand, > populate the mask with 1 << PIPE_[ABC] instead of raw numbers. > > v2: Use 1 << PIPE_[ABC] (ickle/danvet) > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 8a3d89e..0bff282 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1305,13 +1305,13 @@ static void valleyview_update_wm(struct drm_device *dev) > &valleyview_wm_info, latency_ns, > &valleyview_cursor_wm_info, latency_ns, > &planea_wm, &cursora_wm)) > - enabled |= 1; > + enabled |= 1 << PIPE_A; > > if (g4x_compute_wm0(dev, 1, ^ PIPE_B :) > &valleyview_wm_info, latency_ns, > &valleyview_cursor_wm_info, latency_ns, > &planeb_wm, &cursorb_wm)) > - enabled |= 2; > + enabled |= 1 << PIPE_B; -Chris -- Chris Wilson, Intel Open Source Technology Centre ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3] drm/i915: Fix pipe enabled mask for pipe C in WM calculations 2013-03-21 9:52 ` Chris Wilson @ 2013-03-21 11:10 ` ville.syrjala 2013-03-21 11:32 ` Chris Wilson 2013-05-01 18:43 ` Chris Wilson 0 siblings, 2 replies; 6+ messages in thread From: ville.syrjala @ 2013-03-21 11:10 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Fix the incorrect enabled pipes mask for pipe C in the WM calculations. Additionally, in an effort to make the code easier to understand, populate the mask with 1 << PIPE_[ABC] instead of raw numbers. v2: Use 1 << PIPE_[ABC] (ickle/danvet) v3: Pass PIPE_[ABC] to g4x_compute_wm0() (ickle) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 44 ++++++++++++++++++++--------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8a3d89e..d47f354 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1301,17 +1301,17 @@ static void valleyview_update_wm(struct drm_device *dev) vlv_update_drain_latency(dev); - if (g4x_compute_wm0(dev, 0, + if (g4x_compute_wm0(dev, PIPE_A, &valleyview_wm_info, latency_ns, &valleyview_cursor_wm_info, latency_ns, &planea_wm, &cursora_wm)) - enabled |= 1; + enabled |= 1 << PIPE_A; - if (g4x_compute_wm0(dev, 1, + if (g4x_compute_wm0(dev, PIPE_B, &valleyview_wm_info, latency_ns, &valleyview_cursor_wm_info, latency_ns, &planeb_wm, &cursorb_wm)) - enabled |= 2; + enabled |= 1 << PIPE_B; if (single_plane_enabled(enabled) && g4x_compute_srwm(dev, ffs(enabled) - 1, @@ -1357,17 +1357,17 @@ static void g4x_update_wm(struct drm_device *dev) int plane_sr, cursor_sr; unsigned int enabled = 0; - if (g4x_compute_wm0(dev, 0, + if (g4x_compute_wm0(dev, PIPE_A, &g4x_wm_info, latency_ns, &g4x_cursor_wm_info, latency_ns, &planea_wm, &cursora_wm)) - enabled |= 1; + enabled |= 1 << PIPE_A; - if (g4x_compute_wm0(dev, 1, + if (g4x_compute_wm0(dev, PIPE_B, &g4x_wm_info, latency_ns, &g4x_cursor_wm_info, latency_ns, &planeb_wm, &cursorb_wm)) - enabled |= 2; + enabled |= 1 << PIPE_B; if (single_plane_enabled(enabled) && g4x_compute_srwm(dev, ffs(enabled) - 1, @@ -1716,7 +1716,7 @@ static void ironlake_update_wm(struct drm_device *dev) unsigned int enabled; enabled = 0; - if (g4x_compute_wm0(dev, 0, + if (g4x_compute_wm0(dev, PIPE_A, &ironlake_display_wm_info, ILK_LP0_PLANE_LATENCY, &ironlake_cursor_wm_info, @@ -1727,10 +1727,10 @@ static void ironlake_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe A -" " plane %d, " "cursor: %d\n", plane_wm, cursor_wm); - enabled |= 1; + enabled |= 1 << PIPE_A; } - if (g4x_compute_wm0(dev, 1, + if (g4x_compute_wm0(dev, PIPE_B, &ironlake_display_wm_info, ILK_LP0_PLANE_LATENCY, &ironlake_cursor_wm_info, @@ -1741,7 +1741,7 @@ static void ironlake_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe B -" " plane %d, cursor: %d\n", plane_wm, cursor_wm); - enabled |= 2; + enabled |= 1 << PIPE_B; } /* @@ -1801,7 +1801,7 @@ static void sandybridge_update_wm(struct drm_device *dev) unsigned int enabled; enabled = 0; - if (g4x_compute_wm0(dev, 0, + if (g4x_compute_wm0(dev, PIPE_A, &sandybridge_display_wm_info, latency, &sandybridge_cursor_wm_info, latency, &plane_wm, &cursor_wm)) { @@ -1812,10 +1812,10 @@ static void sandybridge_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe A -" " plane %d, " "cursor: %d\n", plane_wm, cursor_wm); - enabled |= 1; + enabled |= 1 << PIPE_A; } - if (g4x_compute_wm0(dev, 1, + if (g4x_compute_wm0(dev, PIPE_B, &sandybridge_display_wm_info, latency, &sandybridge_cursor_wm_info, latency, &plane_wm, &cursor_wm)) { @@ -1826,7 +1826,7 @@ static void sandybridge_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe B -" " plane %d, cursor: %d\n", plane_wm, cursor_wm); - enabled |= 2; + enabled |= 1 << PIPE_B; } /* @@ -1904,7 +1904,7 @@ static void ivybridge_update_wm(struct drm_device *dev) unsigned int enabled; enabled = 0; - if (g4x_compute_wm0(dev, 0, + if (g4x_compute_wm0(dev, PIPE_A, &sandybridge_display_wm_info, latency, &sandybridge_cursor_wm_info, latency, &plane_wm, &cursor_wm)) { @@ -1915,10 +1915,10 @@ static void ivybridge_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe A -" " plane %d, " "cursor: %d\n", plane_wm, cursor_wm); - enabled |= 1; + enabled |= 1 << PIPE_A; } - if (g4x_compute_wm0(dev, 1, + if (g4x_compute_wm0(dev, PIPE_B, &sandybridge_display_wm_info, latency, &sandybridge_cursor_wm_info, latency, &plane_wm, &cursor_wm)) { @@ -1929,10 +1929,10 @@ static void ivybridge_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe B -" " plane %d, cursor: %d\n", plane_wm, cursor_wm); - enabled |= 2; + enabled |= 1 << PIPE_B; } - if (g4x_compute_wm0(dev, 2, + if (g4x_compute_wm0(dev, PIPE_C, &sandybridge_display_wm_info, latency, &sandybridge_cursor_wm_info, latency, &plane_wm, &cursor_wm)) { @@ -1943,7 +1943,7 @@ static void ivybridge_update_wm(struct drm_device *dev) DRM_DEBUG_KMS("FIFO watermarks For pipe C -" " plane %d, cursor: %d\n", plane_wm, cursor_wm); - enabled |= 3; + enabled |= 1 << PIPE_C; } /* -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3] drm/i915: Fix pipe enabled mask for pipe C in WM calculations 2013-03-21 11:10 ` [PATCH v3] " ville.syrjala @ 2013-03-21 11:32 ` Chris Wilson 2013-05-01 18:43 ` Chris Wilson 1 sibling, 0 replies; 6+ messages in thread From: Chris Wilson @ 2013-03-21 11:32 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Thu, Mar 21, 2013 at 01:10:44PM +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Fix the incorrect enabled pipes mask for pipe C in the WM calculations. > > Additionally, in an effort to make the code easier to understand, > populate the mask with 1 << PIPE_[ABC] instead of raw numbers. > > v2: Use 1 << PIPE_[ABC] (ickle/danvet) > v3: Pass PIPE_[ABC] to g4x_compute_wm0() (ickle) > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris -- Chris Wilson, Intel Open Source Technology Centre ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3] drm/i915: Fix pipe enabled mask for pipe C in WM calculations 2013-03-21 11:10 ` [PATCH v3] " ville.syrjala 2013-03-21 11:32 ` Chris Wilson @ 2013-05-01 18:43 ` Chris Wilson 2013-05-01 19:18 ` Daniel Vetter 1 sibling, 1 reply; 6+ messages in thread From: Chris Wilson @ 2013-05-01 18:43 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Thu, Mar 21, 2013 at 01:10:44PM +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Fix the incorrect enabled pipes mask for pipe C in the WM calculations. > > Additionally, in an effort to make the code easier to understand, > populate the mask with 1 << PIPE_[ABC] instead of raw numbers. > > v2: Use 1 << PIPE_[ABC] (ickle/danvet) > v3: Pass PIPE_[ABC] to g4x_compute_wm0() (ickle) > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Pokey poke. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris -- Chris Wilson, Intel Open Source Technology Centre ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3] drm/i915: Fix pipe enabled mask for pipe C in WM calculations 2013-05-01 18:43 ` Chris Wilson @ 2013-05-01 19:18 ` Daniel Vetter 0 siblings, 0 replies; 6+ messages in thread From: Daniel Vetter @ 2013-05-01 19:18 UTC (permalink / raw) To: Chris Wilson, ville.syrjala, intel-gfx On Wed, May 01, 2013 at 07:43:41PM +0100, Chris Wilson wrote: > On Thu, Mar 21, 2013 at 01:10:44PM +0200, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Fix the incorrect enabled pipes mask for pipe C in the WM calculations. > > > > Additionally, in an effort to make the code easier to understand, > > populate the mask with 1 << PIPE_[ABC] instead of raw numbers. > > > > v2: Use 1 << PIPE_[ABC] (ickle/danvet) > > v3: Pass PIPE_[ABC] to g4x_compute_wm0() (ickle) > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Pokey poke. > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Oops, sorry. Picked up for -fixes, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-05-01 19:15 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-03-21 9:41 [PATCH v2] drm/i915: Fix pipe enabled mask for pipe C in WM calculations ville.syrjala 2013-03-21 9:52 ` Chris Wilson 2013-03-21 11:10 ` [PATCH v3] " ville.syrjala 2013-03-21 11:32 ` Chris Wilson 2013-05-01 18:43 ` Chris Wilson 2013-05-01 19:18 ` Daniel Vetter
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