* [PATCH igt 1/2] tools/quick_dump: Update Baytrail DPIO names to reflect to the driver change.
@ 2013-12-04 12:44 Chon Ming Lee
2013-12-04 12:44 ` [PATCH igt 2/2] Update dpio read/write to take in extra PHY parameter Chon Ming Lee
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Chon Ming Lee @ 2013-12-04 12:44 UTC (permalink / raw)
To: intel-gfx
DPIO name still using old name. Change it according to the driver name.
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
---
tools/quick_dump/vlv_dpio.txt | 104 +++++++++++++++++++++---------------------
1 file changed, 51 insertions(+), 53 deletions(-)
diff --git a/tools/quick_dump/vlv_dpio.txt b/tools/quick_dump/vlv_dpio.txt
index 28626da..2942d37 100644
--- a/tools/quick_dump/vlv_dpio.txt
+++ b/tools/quick_dump/vlv_dpio.txt
@@ -1,54 +1,52 @@
('DPIO_CTL', '0x182110', '')
-('DPIO_TX3_SWING_CTL4_A', '0x690', 'DPIO')
-('DPIO_TX3_SWING_CTL4_B', '0x2a90', 'DPIO')
-('DPIO_DIV_A', '0x800c', 'DPIO')
-('DPIO_DIV_B', '0x802c', 'DPIO')
-('DPIO_REFSFR_A', '0x8014', 'DPIO')
-('DPIO_REFSFR_B', '0x8034', 'DPIO')
-('DPIO_CORE_CLK_A', '0x801c', 'DPIO')
-('DPIO_CORE_CLK_B', '0x803c', 'DPIO')
-('DPIO_IREF_CTL_A', '0x8040', 'DPIO')
-('DPIO_IREF_CTL_B', '0x8060', 'DPIO')
-('DPIO_IREF_BCAST', '0xc044', 'DPIO')
-('DPIO_IREF_A', '0x8044', 'DPIO')
-('DPIO_IREF_B', '0x8064', 'DPIO')
-('DPIO_PLL_CML_A', '0x804c', 'DPIO')
-('DPIO_PLL_CML_B', '0x806c', 'DPIO')
-('DPIO_LPF_COEFF_A', '0x8048', 'DPIO')
-('DPIO_LPF_COEFF_B', '0x8068', 'DPIO')
-('DPIO_CALIBRATION', '0x80ac', 'DPIO')
-('DPIO_FASTCLK_DISABLE', '0x8100', 'DPIO')
-('DPIO_PCS_TX_0', '0x8200', 'DPIO')
-('DPIO_PCS_TX_1', '0x8400', 'DPIO')
-('DPIO_PCS_CLK_0', '0x8204', 'DPIO')
-('DPIO_PCS_CLK_1', '0x8404', 'DPIO')
-('DPIO_PCS_CTL_OVR1_A', '0x8224', 'DPIO')
-('DPIO_PCS_CTL_OVR1_B', '0x8424', 'DPIO')
-('DPIO_PCS_STAGGER0_A', '0x822c', 'DPIO')
-('DPIO_PCS_STAGGER0_B', '0x842c', 'DPIO')
-('DPIO_PCS_STAGGER1_A', '0x8230', 'DPIO')
-('DPIO_PCS_STAGGER1_B', '0x8430', 'DPIO')
-('DPIO_PCS_CLOCKBUF0_A', '0x8238', 'DPIO')
-('DPIO_PCS_CLOCKBUF0_B', '0x8438', 'DPIO')
-('DPIO_PCS_CLOCKBUF8_A', '0x825c', 'DPIO')
-('DPIO_PCS_CLOCKBUF8_B', '0x845c', 'DPIO')
-('DPIO_TX_SWING_CTL2_A', '0x8288', 'DPIO')
-('DPIO_TX_SWING_CTL2_B', '0x8488', 'DPIO')
-('DPIO_TX_SWING_CTL3_A', '0x828c', 'DPIO')
-('DPIO_TX_SWING_CTL3_B', '0x848c', 'DPIO')
-('DPIO_TX_SWING_CTL4_A', '0x8290', 'DPIO')
-('DPIO_TX_SWING_CTL4_B', '0x8490', 'DPIO')
-('DPIO_TX_OCALINIT_0', '0x8294', 'DPIO')
-('DPIO_TX_OCALINIT_1', '0x8494', 'DPIO')
-('DPIO_TX_CTL_0', '0x82ac', 'DPIO')
-('DPIO_TX_CTL_1', '0x84ac', 'DPIO')
-('DPIO_TX_LANE_0', '0x82b8', 'DPIO')
-('DPIO_TX_LANE_1', '0x84b8', 'DPIO')
-('DPIO_DATA_CHANNEL1', '0x8220', 'DPIO')
-('DPIO_DATA_CHANNEL2', '0x8420', 'DPIO')
-('DPIO_PORT0_PCS0', '0x0220', 'DPIO')
-('DPIO_PORT0_PCS1', '0x0420', 'DPIO')
-('DPIO_PORT1_PCS2', '0x2620', 'DPIO')
-('DPIO_PORT1_PCS3', '0x2820', 'DPIO')
-('DPIO_DATA_CHANNEL1', '0x8220', 'DPIO')
-('DPIO_DATA_CHANNEL2', '0x8420', 'DPIO')
+('DPIO_TX3_DW4_CH0', '0x690', 'DPIO')
+('DPIO_TX3_DW4_CH1', '0x2a90', 'DPIO')
+('DPIO_PLL_DW3_CH0', '0x800c', 'DPIO')
+('DPIO_PLL_DW3_CH1', '0x802c', 'DPIO')
+('DPIO_PLL_DW5_CH0', '0x8014', 'DPIO')
+('DPIO_PLL_DW5_CH1', '0x8034', 'DPIO')
+('DPIO_PLL_DW7_CH0', '0x801c', 'DPIO')
+('DPIO_PLL_DW7_CH1', '0x803c', 'DPIO')
+('DPIO_PLL_DW8_CH0', '0x8040', 'DPIO')
+('DPIO_PLL_DW8_CH1', '0x8060', 'DPIO')
+('DPIO_PLL_DW9_BCAST', '0xc044', 'DPIO')
+('DPIO_PLL_DW9_CH0', '0x8044', 'DPIO')
+('DPIO_PLL_DW9_CH1', '0x8064', 'DPIO')
+('DPIO_PLL_DW10_CH0', '0x8048', 'DPIO')
+('DPIO_PLL_DW10_CH1', '0x8068', 'DPIO')
+('DPIO_PLL_DW11_CH0', '0x804c', 'DPIO')
+('DPIO_PLL_DW11_CH1', '0x806c', 'DPIO')
+('DPIO_REF_DW13', '0x80ac', 'DPIO')
+('DPIO_CMN_DW0', '0x8100', 'DPIO')
+('DPIO_PCS_DW0_CH0', '0x8200', 'DPIO')
+('DPIO_PCS_DW0_CH1', '0x8400', 'DPIO')
+('DPIO_PCS_DW1_CH0', '0x8204', 'DPIO')
+('DPIO_PCS_DW1_CH1', '0x8404', 'DPIO')
+('DPIO_PCS01_DW8_CH0', '0x0220', 'DPIO')
+('DPIO_PCS23_DW8_CH0', '0x0420', 'DPIO')
+('DPIO_PCS01_DW8_CH1', '0x2620', 'DPIO')
+('DPIO_PCS23_DW8_CH1', '0x2820', 'DPIO')
+('DPIO_PCS_DW8_CH0', '0x8220', 'DPIO')
+('DPIO_PCS_DW8_CH1', '0x8420', 'DPIO')
+('DPIO_PCS_DW9_CH0', '0x8224', 'DPIO')
+('DPIO_PCS_DW9_CH1', '0x8424', 'DPIO')
+('DPIO_PCS_DW11_CH0', '0x822c', 'DPIO')
+('DPIO_PCS_DW11_CH1', '0x842c', 'DPIO')
+('DPIO_PCS_DW12_CH0', '0x8230', 'DPIO')
+('DPIO_PCS_DW12_CH1', '0x8430', 'DPIO')
+('DPIO_PCS_DW14_CH0', '0x8238', 'DPIO')
+('DPIO_PCS_DW14_CH1', '0x8438', 'DPIO')
+('DPIO_PCS_DW23_CH0', '0x825c', 'DPIO')
+('DPIO_PCS_DW23_CH1', '0x845c', 'DPIO')
+('DPIO_TX_DW2_CH0', '0x8288', 'DPIO')
+('DPIO_TX_DW2_CH1', '0x8488', 'DPIO')
+('DPIO_TX_DW3_CH0', '0x828c', 'DPIO')
+('DPIO_TX_DW3_CH1', '0x848c', 'DPIO')
+('DPIO_TX_DW4_CH0', '0x8290', 'DPIO')
+('DPIO_TX_DW4_CH1', '0x8490', 'DPIO')
+('DPIO_TX_DW5_CH0', '0x8294', 'DPIO')
+('DPIO_TX_DW5_CH1', '0x8494', 'DPIO')
+('DPIO_TX_DW11_CH0', '0x82ac', 'DPIO')
+('DPIO_TX_DW11_CH1', '0x84ac', 'DPIO')
+('DPIO_TX_DW14_CH0', '0x82b8', 'DPIO')
+('DPIO_TX_DW14_CH1', '0x84b8', 'DPIO')
--
1.8.3.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH igt 2/2] Update dpio read/write to take in extra PHY parameter.
2013-12-04 12:44 [PATCH igt 1/2] tools/quick_dump: Update Baytrail DPIO names to reflect to the driver change Chon Ming Lee
@ 2013-12-04 12:44 ` Chon Ming Lee
2013-12-05 11:09 ` [PATCH igt 1/2] tools/quick_dump: Update Baytrail DPIO names to reflect to the driver change Ville Syrjälä
2013-12-05 13:11 ` Ville Syrjälä
2 siblings, 0 replies; 4+ messages in thread
From: Chon Ming Lee @ 2013-12-04 12:44 UTC (permalink / raw)
To: intel-gfx
The extra parameter is for future platform.
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
---
lib/intel_dpio.c | 19 +++++++++++++++----
lib/intel_gpu_tools.h | 4 ++--
tools/intel_dpio_read.c | 2 +-
tools/intel_dpio_write.c | 2 +-
tools/quick_dump/chipset.i | 4 ++--
tools/quick_dump/quick_dump.py | 2 +-
tools/quick_dump/reg_access.py | 6 ++++--
7 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/lib/intel_dpio.c b/lib/intel_dpio.c
index acfd201..7e22095 100644
--- a/lib/intel_dpio.c
+++ b/lib/intel_dpio.c
@@ -50,12 +50,23 @@ static void intel_display_reg_write(uint32_t reg, uint32_t val)
*ptr = val;
}
+static int get_dpio_port(int phy) {
+
+ struct pci_device *dev = intel_get_pci_device();
+ int dpio_port;
+
+ if (IS_VALLEYVIEW(dev->device_id))
+ dpio_port = DPIO_PORTID;
+
+ return dpio_port;
+}
+
/*
* In SoCs like Valleyview some of the PLL & Lane control registers
* can be accessed only through IO side band fabric called DPIO
*/
uint32_t
-intel_dpio_reg_read(uint32_t reg)
+intel_dpio_reg_read(uint32_t reg, int phy)
{
/* Check whether the side band fabric is ready to accept commands */
do {
@@ -64,7 +75,7 @@ intel_dpio_reg_read(uint32_t reg)
intel_display_reg_write(DPIO_REG, reg);
intel_display_reg_write(DPIO_PKT, DPIO_RID |
- DPIO_OP_READ | DPIO_PORTID | DPIO_BYTE);
+ DPIO_OP_READ | get_dpio_port(phy) | DPIO_BYTE);
do {
usleep(1);
} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
@@ -77,7 +88,7 @@ intel_dpio_reg_read(uint32_t reg)
* can be accessed only through IO side band fabric called DPIO
*/
void
-intel_dpio_reg_write(uint32_t reg, uint32_t val)
+intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
{
/* Check whether the side band fabric is ready to accept commands */
do {
@@ -87,7 +98,7 @@ intel_dpio_reg_write(uint32_t reg, uint32_t val)
intel_display_reg_write(DPIO_DATA, val);
intel_display_reg_write(DPIO_REG, reg);
intel_display_reg_write(DPIO_PKT, DPIO_RID |
- DPIO_OP_WRITE | DPIO_PORTID | DPIO_BYTE);
+ DPIO_OP_WRITE | get_dpio_port(phy) | DPIO_BYTE);
do {
usleep(1);
} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
diff --git a/lib/intel_gpu_tools.h b/lib/intel_gpu_tools.h
index 412e465..b242243 100644
--- a/lib/intel_gpu_tools.h
+++ b/lib/intel_gpu_tools.h
@@ -48,8 +48,8 @@ void intel_register_write(uint32_t reg, uint32_t val);
int intel_register_access_needs_fakewake(void);
/* Following functions are relevant only for SoCs like Valleyview */
-uint32_t intel_dpio_reg_read(uint32_t reg);
-void intel_dpio_reg_write(uint32_t reg, uint32_t val);
+uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
+void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy);
int intel_punit_read(uint8_t addr, uint32_t *val);
int intel_punit_write(uint8_t addr, uint32_t val);
diff --git a/tools/intel_dpio_read.c b/tools/intel_dpio_read.c
index c0c904a..6202ad9 100644
--- a/tools/intel_dpio_read.c
+++ b/tools/intel_dpio_read.c
@@ -56,7 +56,7 @@ int main(int argc, char** argv)
intel_register_access_init(dev, 0);
- val = intel_dpio_reg_read(reg);
+ val = intel_dpio_reg_read(reg, 0);
printf("Read DPIO register: 0x%x - Value : 0x%x\n", reg, val);
diff --git a/tools/intel_dpio_write.c b/tools/intel_dpio_write.c
index f842999..3d2f297 100644
--- a/tools/intel_dpio_write.c
+++ b/tools/intel_dpio_write.c
@@ -57,7 +57,7 @@ int main(int argc, char** argv)
intel_register_access_init(dev, 0);
- intel_dpio_reg_write(reg, val);
+ intel_dpio_reg_write(reg, val, 0);
intel_register_access_fini();
diff --git a/tools/quick_dump/chipset.i b/tools/quick_dump/chipset.i
index f1cc368..c5f4b56 100644
--- a/tools/quick_dump/chipset.i
+++ b/tools/quick_dump/chipset.i
@@ -16,7 +16,7 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val);
extern void intel_register_access_fini();
extern int intel_register_access_needs_fakewake();
extern unsigned short pcidev_to_devid(struct pci_device *pci_dev);
-extern uint32_t intel_dpio_reg_read(uint32_t reg);
+extern uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
%}
extern int is_sandybridge(unsigned short pciid);
@@ -30,4 +30,4 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val);
extern void intel_register_access_fini();
extern int intel_register_access_needs_fakewake();
extern unsigned short pcidev_to_devid(struct pci_device *pci_dev);
-extern uint32_t intel_dpio_reg_read(uint32_t reg);
+extern uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
index ff151d1..77744d4 100644
--- a/tools/quick_dump/quick_dump.py
+++ b/tools/quick_dump/quick_dump.py
@@ -21,7 +21,7 @@ def parse_file(file):
for line in file:
register = ast.literal_eval(line)
if register[2] == 'DPIO':
- val = reg.dpio_read(register[1])
+ val = reg.dpio_read(register[1], 0)
else:
val = reg.read(register[1])
intreg = int(register[1], 16)
diff --git a/tools/quick_dump/reg_access.py b/tools/quick_dump/reg_access.py
index 113a3cf..cf6e0a4 100755
--- a/tools/quick_dump/reg_access.py
+++ b/tools/quick_dump/reg_access.py
@@ -27,9 +27,11 @@ def get_wake():
mt_forcewake_get()
vlv_forcewake_get()
-def dpio_read(reg):
+def dpio_read(reg, phy):
reg = int(reg, 16)
- val = chipset.intel_dpio_reg_read(reg)
+ phy = int(phy)
+
+ val = chipset.intel_dpio_reg_read(reg, phy)
return val
--
1.8.3.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH igt 1/2] tools/quick_dump: Update Baytrail DPIO names to reflect to the driver change.
2013-12-04 12:44 [PATCH igt 1/2] tools/quick_dump: Update Baytrail DPIO names to reflect to the driver change Chon Ming Lee
2013-12-04 12:44 ` [PATCH igt 2/2] Update dpio read/write to take in extra PHY parameter Chon Ming Lee
@ 2013-12-05 11:09 ` Ville Syrjälä
2013-12-05 13:11 ` Ville Syrjälä
2 siblings, 0 replies; 4+ messages in thread
From: Ville Syrjälä @ 2013-12-05 11:09 UTC (permalink / raw)
To: Chon Ming Lee; +Cc: intel-gfx
On Wed, Dec 04, 2013 at 08:44:32PM +0800, Chon Ming Lee wrote:
> DPIO name still using old name. Change it according to the driver name.
>
> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Thanks. Both patches pushed.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH igt 1/2] tools/quick_dump: Update Baytrail DPIO names to reflect to the driver change.
2013-12-04 12:44 [PATCH igt 1/2] tools/quick_dump: Update Baytrail DPIO names to reflect to the driver change Chon Ming Lee
2013-12-04 12:44 ` [PATCH igt 2/2] Update dpio read/write to take in extra PHY parameter Chon Ming Lee
2013-12-05 11:09 ` [PATCH igt 1/2] tools/quick_dump: Update Baytrail DPIO names to reflect to the driver change Ville Syrjälä
@ 2013-12-05 13:11 ` Ville Syrjälä
2 siblings, 0 replies; 4+ messages in thread
From: Ville Syrjälä @ 2013-12-05 13:11 UTC (permalink / raw)
To: Chon Ming Lee; +Cc: intel-gfx
On Wed, Dec 04, 2013 at 08:44:32PM +0800, Chon Ming Lee wrote:
...
> +('DPIO_TX3_DW4_CH0', '0x690', 'DPIO')
> +('DPIO_TX3_DW4_CH1', '0x2a90', 'DPIO')
...
> +('DPIO_TX_DW4_CH0', '0x8290', 'DPIO')
> +('DPIO_TX_DW4_CH1', '0x8490', 'DPIO')
One thing I've been wondering is what answer do we get when we read a
register using group or broadcast access, but the actual registers have
different values? I don't remember seeing an answer in any spec. Anyone
else know the answer? I was thinking I should try it next time a VLV
crosses my desk.
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2013-12-05 13:11 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-12-04 12:44 [PATCH igt 1/2] tools/quick_dump: Update Baytrail DPIO names to reflect to the driver change Chon Ming Lee
2013-12-04 12:44 ` [PATCH igt 2/2] Update dpio read/write to take in extra PHY parameter Chon Ming Lee
2013-12-05 11:09 ` [PATCH igt 1/2] tools/quick_dump: Update Baytrail DPIO names to reflect to the driver change Ville Syrjälä
2013-12-05 13:11 ` Ville Syrjälä
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox