From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Cc: "Bruno Prémont" <bonbons@linux-vserver.org>
Subject: [PATCH 1/5] drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel
Date: Mon, 9 Dec 2013 18:54:13 +0200 [thread overview]
Message-ID: <1386608057-20866-2-git-send-email-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <1386608057-20866-1-git-send-email-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to determine the correct p2 divider for LVDS on gen2,
we need to check the CLKB mode from the LVDS port register to
determine if we're dealing with single or dual channel LVDS.
Cc: Bruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af3717a..0d63f57 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7939,12 +7939,17 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
else
i9xx_clock(refclk, &clock);
} else {
- bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
+ u32 lvds = I915_READ(LVDS);
+ bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
if (is_lvds) {
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
DPLL_FPA01_P1_POST_DIV_SHIFT);
- clock.p2 = 14;
+
+ if (lvds & LVDS_CLKB_POWER_UP)
+ clock.p2 = 7;
+ else
+ clock.p2 = 14;
} else {
if (dpll & PLL_P1_DIVIDE_BY_TWO)
clock.p1 = 2;
--
1.8.3.2
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next prev parent reply other threads:[~2013-12-09 16:54 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-09 16:54 [PATCH 0/5] drm/i915: Gen2 PLL fixes ville.syrjala
2013-12-09 16:54 ` ville.syrjala [this message]
2013-12-09 16:54 ` [PATCH 2/5] drm/i915: Change N divider minimum from 3 to 2 for gen2 ville.syrjala
2013-12-09 16:54 ` [PATCH 3/5] drm/i915: Increase gen2 vco frequency limit to 1512 MHz ville.syrjala
2013-12-09 16:54 ` [PATCH 4/5] drm/i915: Fix 66 MHz LVDS SSC freq for gen2 ville.syrjala
2013-12-09 16:54 ` [PATCH 5/5] drm/i915: Decrease gen2 vco frequency minimum to 908 MHz ville.syrjala
2013-12-10 11:52 ` [PATCH 0/5] drm/i915: Gen2 PLL fixes Bruno Prémont
2013-12-10 12:19 ` Ville Syrjälä
2013-12-10 12:33 ` Bruno Prémont
2013-12-10 12:47 ` Ville Syrjälä
2013-12-11 10:12 ` Daniel Vetter
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