Re: [PATCH 0/5] drm/i915: Gen2 PLL fixes

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, Dec 10, 2013 at 01:33:01PM +0100, Bruno Prémont wrote:
> Hi Ville,
> 
> On Tue, 10 December 2013 Ville Syrjälä wrote:
> > On Tue, Dec 10, 2013 at 12:52:27PM +0100, Bruno Prémont wrote:
> > > On Mon, 09 December 2013 Ville Syrjälä wrote:
> > > > There appear to be some gen2 machines that don't really like the current PLL
> > > > limits we have. We also have some accuracy problems with the PLL calculations.
> > > > This series aims to eliminate those problems, and at least my 855 machine
> > > > seems happier with these patches.
> > > > 
> > > > Ville Syrjälä (5):
> > > >       drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel
> > > >       drm/i915: Change N divider minimum from 3 to 2 for gen2
> > > >       drm/i915: Increase gen2 vco frequency limit to 1512 MHz
> > > >       drm/i915: Fix 66 MHz LVDS SSC freq for gen2
> > > >       drm/i915: Decrease gen2 vco frequency minimum to 908 MHz
> > > > 
> > > >  drivers/gpu/drm/i915/intel_bios.c    |  8 ++++----
> > > >  drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++---------------
> > > >  2 files changed, 23 insertions(+), 19 deletions(-)
> > > 
> > > Here is my dmesg with the 5 patches applied (on top of 3.13-rc3 and
> > > the PLL debug patch).
> > > 
> > > The WARN() are not hit anymore.
> > > 
> > <snip>
> > > [   46.584578] [drm:intel_dump_pipe_config], DPLL = 0x0
> > > [   46.584581] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
> > > [   46.584583] [drm:intel_dump_pipe_config], FP0 = 0x0
> > > [   46.584586] [drm:intel_dump_pipe_config], FP1 = 0x0
> > 
> > OK, so I think the problem got fixed, but my debug patch wasn't
> > all that good since it doesn't dump the values we computed unless
> > the clock is off.
> > 
> > Can you still run this (as root) when the LVDS output is active:
> > # intel_reg_read 0x6014 0x6018 0x6040 0x6044 0x6048 0x604c
> > 
> > intel_reg_read is part of intel-gpu-tools.
> 
> Here are the results (when already running under X since previous
> my mail):
> 
> # intel_reg_read 0x6014 0x6018 0x6040 0x6044 0x6048 0x604c
> 0x6014 : 0x0
> 0x6018 : 0x90020000
> 0x6040 : 0x2140E
> 0x6044 : 0x2140E
> 0x6048 : 0x2140E
> 0x604C : 0x2140E

Thanks. That's what the BIOS had, so it seems we're good. Now I suppose
we just need to figure out if we dare change the PLL limits for all gen2,
or if we should limit the changes to a more narrow set of platforms.

-- 
Ville Syrjälä
Intel OTC