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From: Akash Goel <akash.goel@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3] drm/i915: Added write-enable pte bit support
Date: Sun, 18 May 2014 11:27:00 +0530	[thread overview]
Message-ID: <1400392620.24345.12.camel@akashgoe-desktop> (raw)
In-Reply-To: <20140514081440.GA8790@phenom.ffwll.local>

On Wed, 2014-05-14 at 10:14 +0200, Daniel Vetter wrote:
> On Tue, May 13, 2014 at 03:43:12PM -0700, Jesse Barnes wrote:
> > On Wed, 14 May 2014 00:30:34 +0200
> > Daniel Vetter <daniel@ffwll.ch> wrote:
> > 
> > > On Tue, May 13, 2014 at 03:05:24PM -0700, Jesse Barnes wrote:
> > > > On Tue, 11 Feb 2014 14:19:03 +0530
> > > > akash.goel@intel.com wrote:
> > > > 
> > > > > @@ -810,6 +815,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
> > > > >  		pt_vaddr[act_pte] =
> > > > >  			vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
> > > > >  				       cache_level, true);
> > > > > +
> > > > >  		if (++act_pte == I915_PPGTT_PT_ENTRIES) {
> > > > >  			kunmap_atomic(pt_vaddr);
> > > > >  			pt_vaddr = NULL;
> > > > 
> > > > Some extra whitespace here.

Thanks, will remove this.

> > > > 
> > > > Otherwise:
> > > > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > 
> > > Hm, looking at the patch again encoding this into the cache_level enum is
> > > fraught with fun. And due to IS_VLV aliasing chv this will blow up on chv
> > > very likely. My old idea was to eventually add a pte_flags param all over
> > > for this stuff with additional bits.
> > 
> > That works too; and yeah CHV is all different here isn't it.  But won't
> > it go through the gen8 paths anyway?
> 
> Yes, but we have a switch on the cache_level in the gen8 pte encode
> function. Since the bit31 gets or'ed in for VLV, it'll hit also chv and
> wreak havoc in that specific switch - we'll hit the default case when we
> don't expect to.
> 
> cache_level = functional behaviour relevant for the kernel's clflushing
> code
> 

As the 'IS_VALLEYVIEW' check will alias with CHV also, can I just update
the condition here, to include 'GEN7' also (IS_GEN7) in the check.

> > Ack on the cache_level abuse though; it's an implementation detail that
> > should be changed if/when this is properly exposed to userspace (or
> > maybe we shouldn't bother and just use CHV/BDW stuff going forward,
> > supporting a proper mprotect ioctl).
> 
> Not talking about exposing to userspace, but adding pte_flags to the
> low-level platform pte encode functions to prevent the above bugs. I'm ok
> with keeping obj->gt_ro.
> -Daniel

  reply	other threads:[~2014-05-18  5:54 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-11  8:49 [PATCH v3] drm/i915: Added write-enable pte bit support akash.goel
2014-04-24  9:44 ` Goel, Akash
2014-05-13 22:05 ` Jesse Barnes
2014-05-13 22:30   ` Daniel Vetter
2014-05-13 22:43     ` Jesse Barnes
2014-05-14  8:14       ` Daniel Vetter
2014-05-18  5:57         ` Akash Goel [this message]
2014-05-19  6:56           ` Daniel Vetter
2014-05-19  7:33             ` Akash Goel
2014-06-01  6:42               ` Akash Goel
2014-06-02  8:19                 ` Daniel Vetter
2014-06-04  4:46                   ` Akash Goel
2014-06-09  3:06                   ` [PATCH v4] " akash.goel
2014-06-16 19:50                     ` Imre Deak
2014-06-17  5:29                       ` [PATCH v5] " akash.goel
2014-06-17  7:22                         ` Daniel Vetter

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