Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Gupta, Sourab" <sourab.gupta@intel.com>
To: "Lespiau, Damien" <damien.lespiau@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Goel, Akash" <akash.goel@intel.com>
Subject: Re: [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
Date: Mon, 26 May 2014 10:33:48 +0000	[thread overview]
Message-ID: <1401100479.9396.93.camel@sourabgu-desktop> (raw)
In-Reply-To: <1397471017.9396.8.camel@sourabgu-desktop>

On Mon, 2014-04-14 at 10:22 +0000, Gupta, Sourab wrote:
> On Tue, 2014-04-01 at 10:53 +0530, sourab gupta wrote:
> > On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote:
> > > On Mon, 2014-03-24 at 17:56 +0000, Lespiau, Damien wrote:
> > > > On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gupta@intel.com wrote:
> > > > > From: Akash Goel <akash.goel@intel.com>
> > > > > 
> > > > > For disabling L3 clock gating we need to set bit 25 of MMIO
> > > > > register 940c. Earlier this was being done by just writing 1
> > > > > into bit 25 and resetting all other bits.
> > > > > This patch modifies the routine to read-modify-write of the
> > > > > register, so that the values of other bits are not destroyed.
> > > > > 
> > > > > v2: Modifying the comments and the patch commit message (Chris)
> > > > 
> > > > This patch commit message lacks the most important information: which
> > > > bit are we setting back to 0 and we shouldn't, and why is that
> > > > important? We do direct writes to other registers in that function (for
> > > > instance (MI_ARB_VLV just below).
> > > > 
> > > Hi Damien,
> > > The reset value of the register is 0x00F80003. Therefore, if we directly
> > > set only bit 25 to 1, without caring about other bits, the following reg
> > > bits will be affected (bits 1:0, bits 23:19).
> > > This doesn't seem to be the case with other regs where we are writing
> > > directly (MI_ARB_VLV ) whose default value is 0.
> > > So, by this commit we're just trying to set only the bit which we really
> > > want to change.
> > > 
> > > Regards,
> > > Sourab
> > > 
> > > 
> > Hi Damien,
> > Please provide your comments on the above explanation. I'll add more
> > information to the commit message regarding the same, if it is okay.
> > 
> > Thanks,
> > Sourab
> > 
> Hi Damien,
> 
> Waiting for feedback on the patch and the explanation. Can you please
> let us know if the explained reason is good enough for the patch to be
> considered. If so, it can be added to the commit message.
> 
> Regards,
> Sourab
> 
Hi,
Can you please review this patch. Waiting for the feedback.
Thanks,
Sourab

  reply	other threads:[~2014-05-26 10:34 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-24 17:30 [PATCH 0/6] Rendering Specific HW Workarounds for VLV sourab.gupta
2014-03-24 17:30 ` [PATCH v4 1/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' sourab.gupta
2014-03-24 17:30 ` [PATCH v4 2/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' sourab.gupta
2014-04-08  4:41   ` Gupta, Sourab
2014-04-14  9:45     ` [PATCH v5 " sourab.gupta
2014-05-28  9:57       ` Gupta, Sourab
2014-06-05  5:44         ` Gupta, Sourab
2014-03-24 17:30 ` [PATCH v2 3/6] drm/i915: Enabling the TLB invalidate bit in GFX Mode register sourab.gupta
2014-04-01  5:01   ` Gupta, Sourab
2014-04-02 11:34   ` Ville Syrjälä
2014-04-02 11:55     ` Daniel Vetter
2014-03-24 17:30 ` [PATCH 4/6] drm/i915/vlv: Remove the enabling of VS_TIMER_DISPATCH bit in MI MODE reg sourab.gupta
2014-03-24 17:47   ` Chris Wilson
2014-03-24 17:55     ` Gupta, Sourab
2014-03-24 18:01       ` Chris Wilson
2014-03-24 18:28         ` [PATCH v2 " sourab.gupta
2014-03-25 11:33           ` Ville Syrjälä
2014-03-25 12:31             ` [PATCH v3 4/6] drm/i915: " sourab.gupta
2014-03-25 13:11               ` Ville Syrjälä
2014-03-25 15:41                 ` Daniel Vetter
2014-03-24 17:30 ` [PATCH v2 5/6] drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush' sourab.gupta
2014-04-01 10:51   ` Ville Syrjälä
2014-04-03  4:42     ` [PATCH v3 " sourab.gupta
2014-04-04 11:17       ` Ville Syrjälä
2014-04-04 11:44         ` [PATCH v4 " sourab.gupta
2014-04-04 15:24           ` Chris Wilson
2014-04-04 15:35             ` Ville Syrjälä
2014-04-04 15:59               ` Chris Wilson
2014-04-04 15:59             ` Daniel Vetter
2014-03-24 17:30 ` [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv sourab.gupta
2014-03-24 17:56   ` Damien Lespiau
2014-03-25  6:52     ` Gupta, Sourab
2014-04-01  5:22       ` Gupta, Sourab
2014-04-14 10:22         ` Gupta, Sourab
2014-05-26 10:33           ` Gupta, Sourab [this message]
2014-05-27 14:27   ` Damien Lespiau
2014-05-27 16:54     ` Daniel Vetter

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1401100479.9396.93.camel@sourabgu-desktop \
    --to=sourab.gupta@intel.com \
    --cc=akash.goel@intel.com \
    --cc=damien.lespiau@intel.com \
    --cc=daniel.vetter@ffwll.ch \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox