From: "Shankar, Uma" <uma.shankar@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [v9 10/12] drm/i915/lspcon: Create separate infoframe_enabled helper
Date: Thu, 26 Nov 2020 07:45:30 +0000 [thread overview]
Message-ID: <14107607883147a3ba4c9265688619ad@intel.com> (raw)
In-Reply-To: <20201125165604.GY6112@intel.com>
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Wednesday, November 25, 2020 10:26 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v9 10/12] drm/i915/lspcon: Create separate infoframe_enabled
> helper
>
> On Tue, Nov 03, 2020 at 08:58:32PM +0530, Uma Shankar wrote:
> > Lspcon has Infoframes as well as DIP for HDR metadata(DRM Infoframe).
> > Create a separate mechanism for lspcon compared to HDMI in order to
> > address the same and ensure future scalability.
> >
> > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++---
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_lspcon.h | 2 ++
> > 3 files changed, 27 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 19b16517a502..d50dd1f1292a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4402,6 +4402,7 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > u32 temp, flags = 0;
> >
> > /* XXX: DSI transcoder paranoia */
> > @@ -4482,9 +4483,12 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> > pipe_config->fec_enable);
> > }
> >
> > - pipe_config->infoframes.enable |=
> > - intel_hdmi_infoframes_enabled(encoder, pipe_config);
> > -
> > + if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
> > + pipe_config->infoframes.enable |=
> > + intel_lspcon_infoframes_enabled(encoder,
> pipe_config);
> > + else
> > + pipe_config->infoframes.enable |=
> > + intel_hdmi_infoframes_enabled(encoder,
> pipe_config);
> > break;
> > case TRANS_DDI_MODE_SELECT_DP_MST:
> > pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); diff -
> -git
> > a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index 8a4fd8ca8016..9c8dfd2fb949 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -30,6 +30,7 @@
> > #include "intel_display_types.h"
> > #include "intel_dp.h"
> > #include "intel_lspcon.h"
> > +#include "intel_hdmi.h"
> >
> > /* LSPCON OUI Vendor ID(signatures) */ #define
> > LSPCON_VENDOR_PARADE_OUI 0x001CF8 @@ -667,6 +668,23 @@ bool
> > lspcon_init(struct intel_digital_port *dig_port)
> > return true;
> > }
> >
> > +u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *pipe_config) {
> > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > + u32 val, enabled = 0;
> > +
> > + val = dig_port->infoframes_enabled(encoder, pipe_config);
> > +
> > + if (val & VIDEO_DIP_ENABLE_AVI_HSW)
>
> So this is the function I figured should allow us to not to pretend to use the
> video DIP bits.
>
> I ttink the actual lspcon infoframes_enabled() could just directly use
> intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI) etc. instead of
> doing this extra remapping here.
Thanks Ville for the review and the highly useful suggestions and feedback.
I have addressed the same and sent the next version, please help review.
On colorspace, I have kept BT2020 for HDR as default as of now. Will send a follow
up fixing that appropriately.
I have checked the series on pcon and the series works fine with HDR monitor on a
KBL nuc.
Regards,
Uma Shankar
>
> > + enabled |=
> intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
> > +
> > + if (val & VIDEO_DIP_ENABLE_GMP_HSW)
> > + enabled |=
> > +intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> > +
> > + return enabled;
> > +}
> > +
> > void lspcon_resume(struct intel_digital_port *dig_port) {
> > struct intel_lspcon *lspcon = &dig_port->lspcon; diff --git
> > a/drivers/gpu/drm/i915/display/intel_lspcon.h
> > b/drivers/gpu/drm/i915/display/intel_lspcon.h
> > index d622156d0c4e..e92735408443 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
> > @@ -41,5 +41,7 @@ void hsw_read_infoframe(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state,
> > unsigned int type,
> > void *frame, ssize_t len);
> > +u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *pipe_config);
> >
> > #endif /* __INTEL_LSPCON_H__ */
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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next prev parent reply other threads:[~2020-11-26 7:45 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-03 15:28 [Intel-gfx] [v9 00/12] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-11-03 15:28 ` [Intel-gfx] [v9 01/12] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
2020-11-25 16:30 ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 02/12] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
2020-11-25 16:37 ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 03/12] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
2020-11-04 7:30 ` [Intel-gfx] [v10 " Uma Shankar
2020-11-25 16:36 ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 04/12] drm/i915/display: Attach content type property for LSPCON Uma Shankar
2020-11-25 16:29 ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 05/12] drm/i915/display: Nuke bogus lspcon check Uma Shankar
2020-11-25 16:29 ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 06/12] drm/i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
2020-11-25 16:40 ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 07/12] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
2020-11-25 16:42 ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 08/12] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
2020-11-25 16:46 ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 09/12] drm/i915/display: Implement DRM infoframe read " Uma Shankar
2020-11-25 16:50 ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 10/12] drm/i915/lspcon: Create separate infoframe_enabled helper Uma Shankar
2020-11-25 16:56 ` Ville Syrjälä
2020-11-26 7:45 ` Shankar, Uma [this message]
2020-11-03 15:28 ` [Intel-gfx] [v9 11/12] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks Uma Shankar
2020-11-03 15:28 ` [Intel-gfx] [v9 12/12] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
2020-11-03 15:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev9) Patchwork
2020-11-03 15:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-03 16:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-11-04 7:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev10) Patchwork
2020-11-04 7:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-04 7:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-04 9:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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