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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Uma Shankar <uma.shankar@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [v9 02/12] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
Date: Wed, 25 Nov 2020 18:37:04 +0200	[thread overview]
Message-ID: <20201125163704.GT6112@intel.com> (raw)
In-Reply-To: <20201103152834.12727-3-uma.shankar@intel.com>

On Tue, Nov 03, 2020 at 08:58:24PM +0530, Uma Shankar wrote:
> Gen9 hardware supports HDMI2.0 through LSPCON chips.
> Extending HDR support for MCA LSPCON based GEN9 devices.
> 
> SOC will drive LSPCON as DP and send HDR metadata as standard
> DP SDP packets. LSPCON will be set to operate in PCON mode,
> will receive the metadata and create Dynamic Range and
> Mastering Infoframe (DRM packets) and send it to HDR capable
> HDMI sink devices.
> 
> v2: Re-used hsw infoframe write implementation for HDR metadata
> for LSPCON as per Ville's suggestion.
> 
> v3: Addressed Jani Nikula's review comments.
> 
> v4: Addressed Ville's review comments, removed redundant wrapper
> and checks, passed arguments instead of hardcodings.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_hdmi.c   |  8 +++---
>  drivers/gpu/drm/i915/display/intel_lspcon.c | 31 ++++++++++++---------
>  drivers/gpu/drm/i915/display/intel_lspcon.h |  4 +++
>  3 files changed, 26 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f90838bc74fb..8e4b820b715a 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -518,10 +518,10 @@ static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
>  		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
>  }
>  
> -static void hsw_write_infoframe(struct intel_encoder *encoder,
> -				const struct intel_crtc_state *crtc_state,
> -				unsigned int type,
> -				const void *frame, ssize_t len)
> +void hsw_write_infoframe(struct intel_encoder *encoder,
> +			 const struct intel_crtc_state *crtc_state,
> +			 unsigned int type,
> +			 const void *frame, ssize_t len)
>  {
>  	const u32 *data = frame;
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index 076b21885a30..46565ae555b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -446,27 +446,32 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
>  			    unsigned int type,
>  			    const void *frame, ssize_t len)
>  {
> -	bool ret;
> +	bool ret = true;
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
>  
> -	/* LSPCON only needs AVI IF */
> -	if (type != HDMI_INFOFRAME_TYPE_AVI)
> +	switch (type) {
> +	case HDMI_INFOFRAME_TYPE_AVI:
> +		if (lspcon->vendor == LSPCON_VENDOR_MCA)
> +			ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
> +							      frame, len);
> +		else
> +			ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
> +								 frame, len);
> +		break;
> +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
> +		drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n");
> +		/* It uses the legacy hsw implementation for the same */
> +		hsw_write_infoframe(encoder, crtc_state, type, frame, len);
> +		break;
> +	default:
>  		return;
> -
> -	if (lspcon->vendor == LSPCON_VENDOR_MCA)
> -		ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
> -						      frame, len);
> -	else
> -		ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
> -							 frame, len);
> +	}
>  
>  	if (!ret) {
> -		DRM_ERROR("Failed to write AVI infoframes\n");
> +		DRM_ERROR("Failed to write infoframes\n");
>  		return;
>  	}
> -
> -	DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
>  }
>  
>  void lspcon_read_infoframe(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
> index a19b3564c635..98043ba50dd4 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.h
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
> @@ -32,5 +32,9 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
>  			   const struct drm_connector_state *conn_state);
>  u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *pipe_config);
> +void hsw_write_infoframe(struct intel_encoder *encoder,
> +			 const struct intel_crtc_state *crtc_state,
> +			 unsigned int type,
> +			 const void *frame, ssize_t len);
>  
>  #endif /* __INTEL_LSPCON_H__ */
> -- 
> 2.26.2

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2020-11-25 16:37 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03 15:28 [Intel-gfx] [v9 00/12] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-11-03 15:28 ` [Intel-gfx] [v9 01/12] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
2020-11-25 16:30   ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 02/12] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
2020-11-25 16:37   ` Ville Syrjälä [this message]
2020-11-03 15:28 ` [Intel-gfx] [v9 03/12] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
2020-11-04  7:30   ` [Intel-gfx] [v10 " Uma Shankar
2020-11-25 16:36     ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 04/12] drm/i915/display: Attach content type property for LSPCON Uma Shankar
2020-11-25 16:29   ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 05/12] drm/i915/display: Nuke bogus lspcon check Uma Shankar
2020-11-25 16:29   ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 06/12] drm/i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
2020-11-25 16:40   ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 07/12] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
2020-11-25 16:42   ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 08/12] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
2020-11-25 16:46   ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 09/12] drm/i915/display: Implement DRM infoframe read " Uma Shankar
2020-11-25 16:50   ` Ville Syrjälä
2020-11-03 15:28 ` [Intel-gfx] [v9 10/12] drm/i915/lspcon: Create separate infoframe_enabled helper Uma Shankar
2020-11-25 16:56   ` Ville Syrjälä
2020-11-26  7:45     ` Shankar, Uma
2020-11-03 15:28 ` [Intel-gfx] [v9 11/12] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks Uma Shankar
2020-11-03 15:28 ` [Intel-gfx] [v9 12/12] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
2020-11-03 15:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev9) Patchwork
2020-11-03 15:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-03 16:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-11-04  7:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev10) Patchwork
2020-11-04  7:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-04  7:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-04  9:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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