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From: Damien Lespiau <damien.lespiau@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 4/4] drm/i915/skl: Read out crtl1 for eDP/DPLL0
Date: Fri, 14 Nov 2014 17:24:35 +0000	[thread overview]
Message-ID: <1415985875-7485-5-git-send-email-damien.lespiau@intel.com> (raw)
In-Reply-To: <1415985875-7485-1-git-send-email-damien.lespiau@intel.com>

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b5a279a..924f1ec 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -767,12 +767,20 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
 
 	pipe_config->port_clock = link_clock;
 
+	/*
+	 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part of the
+	 * shared DPLL framework and thus needs to be read out separately
+	 */
+	if (encoder->type == INTEL_OUTPUT_EDP)
+		pipe_config->dpll_hw_state.ctrl1 = (dpll_ctl1 >> (dpll * 6)) & 0x3f;
+
 	if (pipe_config->has_dp_encoder)
 		pipe_config->adjusted_mode.crtc_clock =
 			intel_dotclock_calculate(pipe_config->port_clock,
 						 &pipe_config->dp_m_n);
 	else
 		pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
+
 }
 
 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
-- 
1.8.3.1

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  parent reply	other threads:[~2014-11-14 17:24 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-14 17:24 [PATCH 0/4] SKL eDP clocks Damien Lespiau
2014-11-14 17:24 ` [PATCH 1/4] drm/i915/skl: Remove spurious warn in get_ddi_pll() Damien Lespiau
2014-11-17 12:40   ` Paulo Zanoni
2014-11-14 17:24 ` [PATCH 2/4] drm/i915/skl: Set the eDP link rate on DPLL0 Damien Lespiau
2014-11-17 18:24   ` Daniel Vetter
2014-11-14 17:24 ` [PATCH 3/4] drm/i915/skl: Use the pipe config DPLL tracking to query the link clock Damien Lespiau
2014-11-14 17:24 ` Damien Lespiau [this message]
2014-11-15  5:28   ` [PATCH 4/4] drm/i915/skl: Read out crtl1 for eDP/DPLL0 shuang.he
2014-11-15 10:54     ` Damien Lespiau
2014-11-17 15:03       ` Daniel Vetter
2014-11-18  8:14         ` He, Shuang
2014-11-18  8:11       ` He, Shuang
2014-11-17 18:28   ` Daniel Vetter
2014-11-18  8:18     ` Daniel Vetter
2014-11-21 16:00     ` [PATCH v2] " Damien Lespiau
2014-11-21 16:14       ` [PATCH v3] " Damien Lespiau
2014-11-21 17:46         ` Daniel Vetter
2014-11-17 17:04 ` [PATCH 0/4] SKL eDP clocks Paulo Zanoni
2014-11-17 17:08   ` Damien Lespiau

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