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* [PATCH 1/5] drm/i915: Make IS_GENx macros work on a mask
@ 2016-05-10  9:57 Tvrtko Ursulin
  2016-05-10  9:57 ` [PATCH 2/5] drm/i915: Promote IS_BROADWELL to a simple macro Tvrtko Ursulin
                   ` (4 more replies)
  0 siblings, 5 replies; 10+ messages in thread
From: Tvrtko Ursulin @ 2016-05-10  9:57 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

If instead of numerical comparison me make these test a
bitmask, we enable the compiler to optimize all instances
of IS_GENx || IS_GENy.

v2: Make bit zero of gen mask mean gen 1.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_dma.c     |  3 +++
 drivers/gpu/drm/i915/i915_drv.h     | 17 +++++++++--------
 drivers/gpu/drm/i915/intel_uncore.c |  4 ++--
 3 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 46ac1da64a09..ef2e91d52c5e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1072,6 +1072,9 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 	memcpy(device_info, info, sizeof(dev_priv->info));
 	device_info->device_id = dev->pdev->device;
 
+	BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
+	device_info->gen_mask = BIT(device_info->gen - 1);
+
 	spin_lock_init(&dev_priv->irq_lock);
 	spin_lock_init(&dev_priv->gpu_error.lock);
 	mutex_init(&dev_priv->backlight_lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 26e7de415966..a7db2841d705 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -760,6 +760,7 @@ struct intel_device_info {
 	u8 num_pipes:3;
 	u8 num_sprites[I915_MAX_PIPES];
 	u8 gen;
+	u16 gen_mask;
 	u8 ring_mask; /* Rings supported by the HW */
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
 	/* Register offsets for the various display pipes and transcoders */
@@ -2620,14 +2621,14 @@ struct drm_i915_cmd_table {
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
-#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
-#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
-#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
-#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
-#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
-#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen == 8)
-#define IS_GEN9(dev)	(INTEL_INFO(dev)->gen == 9)
+#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen_mask & BIT(1))
+#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen_mask & BIT(2))
+#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen_mask & BIT(3))
+#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen_mask & BIT(4))
+#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen_mask & BIT(5))
+#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen_mask & BIT(6))
+#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen_mask & BIT(7))
+#define IS_GEN9(dev)	(INTEL_INFO(dev)->gen_mask & BIT(8))
 
 #define RENDER_RING		(1<<RCS)
 #define BSD_RING		(1<<VCS)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 4ea2bf2c2a4a..b7b8a299fd0a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1398,7 +1398,7 @@ void intel_uncore_fini(struct drm_device *dev)
 	intel_uncore_forcewake_reset(dev, false);
 }
 
-#define GEN_RANGE(l, h) GENMASK(h, l)
+#define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
 
 static const struct register_whitelist {
 	i915_reg_t offset_ldw, offset_udw;
@@ -1423,7 +1423,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
 
 	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
 		if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
-		    (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
+		    (INTEL_INFO(dev)->gen_mask & entry->gen_bitmask))
 			break;
 	}
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH 0/5] IS_GENx and related code shrinkage
@ 2016-05-06 15:20 Tvrtko Ursulin
  2016-05-06 15:20 ` [PATCH 2/5] drm/i915: Promote IS_BROADWELL to a simple macro Tvrtko Ursulin
  2016-05-09 13:00 ` [PATCH 1/5] drm/i915: Make IS_GENx macros work on a mask Tvrtko Ursulin
  0 siblings, 2 replies; 10+ messages in thread
From: Tvrtko Ursulin @ 2016-05-06 15:20 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Our huge amount of "what hardware I am" checks during runtime is somewhat
distasteful but to deeply ingrained to be easily fixable.

Instead we can make them more efficient by spotting a few easy ways of helping
the compiler optimize some common idioms.

Five patches below save approx. 1.5kB of text in my test build for not a lot of
source code churn.

Tvrtko Ursulin (5):
  drm/i915: Make IS_GENx macros work on a mask
  drm/i915: Promote IS_BROADWELL to a simple macro
  drm/i915: Replace "INTEL_INFO->gen == x" checks with IS_GENx
  drm/i915: Introduce INTEL_GEN_RANGE macro
  drm/i915: Do not use a bitfield for INTEL_INFO->num_pipes

 drivers/gpu/drm/i915/i915_debugfs.c     |  4 ++--
 drivers/gpu/drm/i915/i915_dma.c         |  7 +++++--
 drivers/gpu/drm/i915/i915_drv.c         |  6 +++++-
 drivers/gpu/drm/i915/i915_drv.h         | 25 ++++++++++++++-----------
 drivers/gpu/drm/i915/i915_gem.c         |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c     |  2 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c  |  2 +-
 drivers/gpu/drm/i915/i915_gem_tiling.c  |  2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c   |  2 +-
 drivers/gpu/drm/i915/i915_irq.c         |  4 ++--
 drivers/gpu/drm/i915/intel_display.c    |  2 +-
 drivers/gpu/drm/i915/intel_fbc.c        |  2 +-
 drivers/gpu/drm/i915/intel_lrc.c        |  4 ++--
 drivers/gpu/drm/i915/intel_lvds.c       |  2 +-
 drivers/gpu/drm/i915/intel_pm.c         |  4 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +++++++-------
 drivers/gpu/drm/i915/intel_uncore.c     |  4 ++--
 17 files changed, 49 insertions(+), 39 deletions(-)

-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2016-05-11 11:17 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-05-10  9:57 [PATCH 1/5] drm/i915: Make IS_GENx macros work on a mask Tvrtko Ursulin
2016-05-10  9:57 ` [PATCH 2/5] drm/i915: Promote IS_BROADWELL to a simple macro Tvrtko Ursulin
2016-05-10  9:57 ` [PATCH 3/5] drm/i915: Replace "INTEL_INFO->gen == x" checks with IS_GENx Tvrtko Ursulin
2016-05-10  9:57 ` [PATCH 4/5] drm/i915: Do not use a bitfield for INTEL_INFO->num_pipes Tvrtko Ursulin
2016-05-10  9:57 ` [PATCH 5/5] drm/i915: Introduce IS_GEN macro Tvrtko Ursulin
2016-05-11 11:10   ` Joonas Lahtinen
2016-05-10 19:53 ` ✓ Ro.CI.BAT: success for series starting with [1/5] drm/i915: Make IS_GENx macros work on a mask Patchwork
2016-05-11 10:59   ` Tvrtko Ursulin
  -- strict thread matches above, loose matches on Subject: below --
2016-05-06 15:20 [PATCH 0/5] IS_GENx and related code shrinkage Tvrtko Ursulin
2016-05-06 15:20 ` [PATCH 2/5] drm/i915: Promote IS_BROADWELL to a simple macro Tvrtko Ursulin
2016-05-09 13:00 ` [PATCH 1/5] drm/i915: Make IS_GENx macros work on a mask Tvrtko Ursulin
2016-05-09 13:00   ` [PATCH 2/5] drm/i915: Promote IS_BROADWELL to a simple macro Tvrtko Ursulin

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