[RFC 0/7] Introduce dynamic PPAT managment for GVT-g

[RFC 0/7] Introduce dynamic PPAT managment for GVT-g

[Zhi Wang]

This patchset introduces dynamic PPAT managment for GVT-g.

Since different VM can have different PPAT configurations, GVT-g needs
to map the virtual private PAT configuration into the physical private
PAT between different VMs.

More background of this patchset can be found at:
https://lists.freedesktop.org/archives/intel-gfx/2017-August/135415.html

Zhi Wang (7):
  drm/i915: Introduce a bitmap to indicate available PPAT entries
  drm/i915/gvt: Introduce GEN8 private PAT ops
  drm/i915: Introduce GEN8 {set, get} private PAT index ops
  drm/i915: Introduce dynamic private PAT management
  drm/i915/gvt: Introduce functions for retiring all shadow PPGTTs of a
    vGPU
  drm/i915/gvt: Introduce virtual private PAT support
  drm/i915/gvt: Translate virtual PPAT indexes

 drivers/gpu/drm/i915/gvt/gtt.c      | 291 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/gtt.h      |  23 ++-
 drivers/gpu/drm/i915/gvt/handlers.c |  16 +-
 drivers/gpu/drm/i915/i915_drv.h     |   3 +
 drivers/gpu/drm/i915/i915_gem_gtt.c |  13 +-
 5 files changed, 342 insertions(+), 4 deletions(-)

-- 
2.7.4

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✓ Fi.CI.BAT: success for Introduce dynamic PPAT managment for GVT-g

[Patchwork]

== Series Details ==

Series: Introduce dynamic PPAT managment for GVT-g
URL   : https://patchwork.freedesktop.org/series/28804/
State : success

== Summary ==

Series 28804v1 Introduce dynamic PPAT managment for GVT-g
https://patchwork.freedesktop.org/api/1.0/series/28804/revisions/1/mbox/

Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-snb-2600) fdo#100215

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:455s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:431s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:355s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:547s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:519s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:523s
fi-byt-n2820     total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  time:514s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:606s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:441s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:421s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:418s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:507s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:477s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:470s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:585s
fi-kbl-r         total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:604s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:520s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:464s
fi-skl-6700k     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:472s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:486s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:440s
fi-skl-x1585l    total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:484s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:546s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:413s

e9e3e14eac496233479315b19a738b8848a54584 drm-tip: 2017y-08m-15d-12h-31m-09s UTC integration manifest
38d8fdda1012 drm/i915/gvt: Translate virtual PPAT indexes
a56c7d454c16 drm/i915/gvt: Introduce virtual private PAT support
1e55b2dbc52d drm/i915/gvt: Introduce functions for retiring all shadow PPGTTs of a vGPU
058594140f55 drm/i915: Introduce dynamic private PAT management
7dec0fbac3fd drm/i915: Introduce GEN8 {set, get} private PAT index ops
89d07087616c drm/i915/gvt: Introduce GEN8 private PAT ops
4e147e24e97a drm/i915: Introduce a bitmap to indicate available PPAT entries

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5402/
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[RFC 1/7] drm/i915: Introduce a bitmap to indicate available PPAT entries

[Zhi Wang]

To introduce the dynamic private PAT management in GVT-g, the host i915
is required to tell GVT-g the unused PAT entries. The available PPAT
entries are showed in a bitmap. For platforms which don't have private
PAT, the bitmap is set to "empty", so GVT-g will not enable private PAT
management function.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h     |  3 +++
 drivers/gpu/drm/i915/i915_gem_gtt.c | 13 ++++++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 768a92b..79fc680 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2302,6 +2302,9 @@ struct drm_i915_private {
 	DECLARE_HASHTABLE(mm_structs, 7);
 	struct mutex mm_lock;
 
+#define MAX_PPAT_INDEX 8
+	DECLARE_BITMAP(avail_ppat_bitmap, MAX_PPAT_INDEX);
+
 	/* Kernel Modesetting */
 
 	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 090ceb7..b9665b7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2758,7 +2758,7 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
 	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
 	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
 
-	if (!USES_PPGTT(dev_priv))
+	if (!USES_PPGTT(dev_priv)) {
 		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
 		 * so RTL will always use the value corresponding to
 		 * pat_sel = 000".
@@ -2774,6 +2774,17 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
 		 */
 		pat = GEN8_PPAT(0, GEN8_PPAT_UC);
 
+		set_bit(1, dev_priv->avail_ppat_bitmap);
+		set_bit(2, dev_priv->avail_ppat_bitmap);
+		set_bit(3, dev_priv->avail_ppat_bitmap);
+	}
+
+	/* PPAT entries 4 - 7 are unused, mark them available */
+	set_bit(4, dev_priv->avail_ppat_bitmap);
+	set_bit(5, dev_priv->avail_ppat_bitmap);
+	set_bit(6, dev_priv->avail_ppat_bitmap);
+	set_bit(7, dev_priv->avail_ppat_bitmap);
+
 	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
 	 * write would work. */
 	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
-- 
2.7.4

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[RFC 2/7] drm/i915/gvt: Introduce GEN8 private PAT ops

[Zhi Wang]

This patch introduces private PAT operations for GEN8.

The "get_pat_value" operation offers an API to get a PPAT entry from the
virtual or physical PPAT MMIO registers. Similar with the "get_pat_value",
the "set_pat_value" operation offers the API to write a PPAT entry back to
PPAT MMIO registers. The caller doesn't need to care about the PPAT MMIO
layout, since the layout is different between different GENs.

The "match_pat_value" will try to compare two PAT entries and give a score
to indicate how perfect they match with each other. The most important
attribute is "cache attribute", which affects the correctness and has to
be matched. Other attributes gain different scores by the their
importance in a partial match.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c | 81 ++++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/gtt.h |  9 +++++
 2 files changed, 90 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index e6dfc33..16bfca9 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -402,6 +402,80 @@ DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
 DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
 DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
 
+static unsigned int gen8_pat_get_value(u32 *mem, unsigned int index,
+				       struct intel_gvt *gvt)
+{
+	struct drm_i915_private *dev_priv = gvt->dev_priv;
+	int reg_index = index / 4;
+	u32 buf[2];
+
+	if (WARN_ON(reg_index >= 2))
+		return 0;
+
+	if (!mem) {
+		mem = buf;
+		mem[reg_index] = reg_index ? I915_READ(GEN8_PRIVATE_PAT_HI) :
+				 I915_READ(GEN8_PRIVATE_PAT_LO);
+	}
+
+	index -= reg_index * 4;
+	return (mem[reg_index] >> (index * 8)) & 0x3f;
+}
+
+static void gen8_pat_set_value(u32 *mem, unsigned int index, unsigned int value,
+			       struct intel_gvt *gvt)
+{
+	struct drm_i915_private *dev_priv = gvt->dev_priv;
+	int reg_index = index / 4;
+	u32 buf[2];
+	bool writeback = false;
+
+	if (WARN_ON(reg_index >= 2))
+		return;
+
+	if (!mem) {
+		mem = buf;
+		writeback = true;
+		mem[reg_index] = reg_index ? I915_READ(GEN8_PRIVATE_PAT_HI) :
+				 I915_READ(GEN8_PRIVATE_PAT_LO);
+	}
+
+	index -= reg_index * 4;
+
+	mem[reg_index] &= ~(0xff << (index * 8));
+	mem[reg_index] |= ((value & 0x3f) << (index * 8));
+
+	if (writeback) {
+		if (reg_index)
+			I915_WRITE(GEN8_PRIVATE_PAT_LO, mem[1]);
+		else
+			I915_WRITE(GEN8_PRIVATE_PAT_LO, mem[0]);
+	}
+}
+
+#define gen8_pat_ca(v) ((v) & 0x3)
+#define gen8_pat_tc(v) ((v) >> 2 & 0x3)
+#define gen8_pat_age(v) ((v) >> 4 & 0x3)
+
+static unsigned int gen8_pat_match_value(unsigned int src, unsigned int dst)
+{
+	unsigned int score = 0;
+
+	if (gen8_pat_ca(src) != gen8_pat_ca(dst))
+		return 0;
+
+	if (gen8_pat_age(src) == gen8_pat_age(dst))
+		score += 1;
+
+	if (gen8_pat_tc(src) == gen8_pat_tc(dst))
+		score += 2;
+
+	if (score == 3)
+		return ~0;
+
+	return score;
+}
+
 static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
 	.get_entry = gtt_get_entry64,
 	.set_entry = gtt_set_entry64,
@@ -421,6 +495,12 @@ static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
 	.gma_to_pml4_index = gen8_gma_to_pml4_index,
 };
 
+static struct intel_gvt_gtt_pat_ops gen8_pat_ops = {
+	.get_pat_value = gen8_pat_get_value,
+	.set_pat_value = gen8_pat_set_value,
+	.match_pat_value = gen8_pat_match_value,
+};
+
 static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p,
 		struct intel_gvt_gtt_entry *m)
 {
@@ -2267,6 +2347,7 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
 		|| IS_KABYLAKE(gvt->dev_priv)) {
 		gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
 		gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
+		gvt->gtt.pat_ops = &gen8_pat_ops;
 		gvt->gtt.mm_alloc_page_table = gen8_mm_alloc_page_table;
 		gvt->gtt.mm_free_page_table = gen8_mm_free_page_table;
 	} else {
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 30a4c8d..7a9eb05 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -77,9 +77,18 @@ struct intel_gvt_gtt_gma_ops {
 	unsigned long (*gma_to_pml4_index)(unsigned long gma);
 };
 
+struct intel_gvt_gtt_pat_ops {
+	unsigned int (*get_pat_value)(u32 *mem, unsigned int index,
+				      struct intel_gvt *gvt);
+	void (*set_pat_value)(u32 *mem, unsigned int index, unsigned int value,
+			      struct intel_gvt *gvt);
+	unsigned int (*match_pat_value)(unsigned int src, unsigned int dst);
+};
+
 struct intel_gvt_gtt {
 	struct intel_gvt_gtt_pte_ops *pte_ops;
 	struct intel_gvt_gtt_gma_ops *gma_ops;
+	struct intel_gvt_gtt_pat_ops *pat_ops;
 	int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
 	void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
 	struct list_head oos_page_use_list_head;
-- 
2.7.4

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Re: [RFC 2/7] drm/i915/gvt: Introduce GEN8 private PAT ops

[Zhenyu Wang]

[-- Attachment #1.1: Type: text/plain, Size: 5677 bytes --]

On 2017.08.16 05:31:10 +0800, Zhi Wang wrote:
> This patch introduces private PAT operations for GEN8.
> 
> The "get_pat_value" operation offers an API to get a PPAT entry from the
> virtual or physical PPAT MMIO registers. Similar with the "get_pat_value",
> the "set_pat_value" operation offers the API to write a PPAT entry back to
> PPAT MMIO registers. The caller doesn't need to care about the PPAT MMIO
> layout, since the layout is different between different GENs.
> 
> The "match_pat_value" will try to compare two PAT entries and give a score
> to indicate how perfect they match with each other. The most important
> attribute is "cache attribute", which affects the correctness and has to
> be matched. Other attributes gain different scores by the their
> importance in a partial match.
> 
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/gtt.c | 81 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/gvt/gtt.h |  9 +++++
>  2 files changed, 90 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index e6dfc33..16bfca9 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -402,6 +402,80 @@ DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
>  DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
>  DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
>  
> +static unsigned int gen8_pat_get_value(u32 *mem, unsigned int index,
> +				       struct intel_gvt *gvt)
> +{

Really dislike to provide many kinds of usage interfaces for one function,
it's easy to cause confusion and mostly unnecessary, although we have lot
in gtt.c...and better to put driver struct as first parameter to align with
other function conversion.

> +	struct drm_i915_private *dev_priv = gvt->dev_priv;
> +	int reg_index = index / 4;
> +	u32 buf[2];
> +
> +	if (WARN_ON(reg_index >= 2))
> +		return 0;
> +
> +	if (!mem) {
> +		mem = buf;
> +		mem[reg_index] = reg_index ? I915_READ(GEN8_PRIVATE_PAT_HI) :
> +				 I915_READ(GEN8_PRIVATE_PAT_LO);
> +	}
> +
> +	index -= reg_index * 4;
> +	return (mem[reg_index] >> (index * 8)) & 0x3f;
> +}
> +
> +static void gen8_pat_set_value(u32 *mem, unsigned int index, unsigned int value,
> +			       struct intel_gvt *gvt)
> +{
> +	struct drm_i915_private *dev_priv = gvt->dev_priv;
> +	int reg_index = index / 4;
> +	u32 buf[2];
> +	bool writeback = false;
> +
> +	if (WARN_ON(reg_index >= 2))
> +		return;
> +
> +	if (!mem) {
> +		mem = buf;
> +		writeback = true;
> +		mem[reg_index] = reg_index ? I915_READ(GEN8_PRIVATE_PAT_HI) :
> +				 I915_READ(GEN8_PRIVATE_PAT_LO);
> +	}
> +
> +	index -= reg_index * 4;
> +
> +	mem[reg_index] &= ~(0xff << (index * 8));
> +	mem[reg_index] |= ((value & 0x3f) << (index * 8));
> +
> +	if (writeback) {
> +		if (reg_index)
> +			I915_WRITE(GEN8_PRIVATE_PAT_LO, mem[1]);
> +		else
> +			I915_WRITE(GEN8_PRIVATE_PAT_LO, mem[0]);
> +	}
> +}
> +
> +#define gen8_pat_ca(v) ((v) & 0x3)
> +#define gen8_pat_tc(v) ((v) >> 2 & 0x3)
> +#define gen8_pat_age(v) ((v) >> 4 & 0x3)
> +
> +static unsigned int gen8_pat_match_value(unsigned int src, unsigned int dst)
> +{
> +	unsigned int score = 0;
> +
> +	if (gen8_pat_ca(src) != gen8_pat_ca(dst))
> +		return 0;
> +
> +	if (gen8_pat_age(src) == gen8_pat_age(dst))
> +		score += 1;
> +
> +	if (gen8_pat_tc(src) == gen8_pat_tc(dst))
> +		score += 2;
> +
> +	if (score == 3)
> +		return ~0;
> +
> +	return score;
> +}
> +
>  static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
>  	.get_entry = gtt_get_entry64,
>  	.set_entry = gtt_set_entry64,
> @@ -421,6 +495,12 @@ static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
>  	.gma_to_pml4_index = gen8_gma_to_pml4_index,
>  };
>  
> +static struct intel_gvt_gtt_pat_ops gen8_pat_ops = {
> +	.get_pat_value = gen8_pat_get_value,
> +	.set_pat_value = gen8_pat_set_value,
> +	.match_pat_value = gen8_pat_match_value,
> +};
> +
>  static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p,
>  		struct intel_gvt_gtt_entry *m)
>  {
> @@ -2267,6 +2347,7 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
>  		|| IS_KABYLAKE(gvt->dev_priv)) {
>  		gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
>  		gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
> +		gvt->gtt.pat_ops = &gen8_pat_ops;
>  		gvt->gtt.mm_alloc_page_table = gen8_mm_alloc_page_table;
>  		gvt->gtt.mm_free_page_table = gen8_mm_free_page_table;
>  	} else {
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
> index 30a4c8d..7a9eb05 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.h
> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
> @@ -77,9 +77,18 @@ struct intel_gvt_gtt_gma_ops {
>  	unsigned long (*gma_to_pml4_index)(unsigned long gma);
>  };
>  
> +struct intel_gvt_gtt_pat_ops {
> +	unsigned int (*get_pat_value)(u32 *mem, unsigned int index,
> +				      struct intel_gvt *gvt);
> +	void (*set_pat_value)(u32 *mem, unsigned int index, unsigned int value,
> +			      struct intel_gvt *gvt);
> +	unsigned int (*match_pat_value)(unsigned int src, unsigned int dst);
> +};
> +
>  struct intel_gvt_gtt {
>  	struct intel_gvt_gtt_pte_ops *pte_ops;
>  	struct intel_gvt_gtt_gma_ops *gma_ops;
> +	struct intel_gvt_gtt_pat_ops *pat_ops;
>  	int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
>  	void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
>  	struct list_head oos_page_use_list_head;
> -- 
> 2.7.4
> 

-- 
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Re: [RFC 2/7] drm/i915/gvt: Introduce GEN8 private PAT ops

[Zhi Wang]

It's OK. I can split it. :)

On 08/16/17 13:12, Zhenyu Wang wrote:
> On 2017.08.16 05:31:10 +0800, Zhi Wang wrote:
>> This patch introduces private PAT operations for GEN8.
>>
>> The "get_pat_value" operation offers an API to get a PPAT entry from the
>> virtual or physical PPAT MMIO registers. Similar with the "get_pat_value",
>> the "set_pat_value" operation offers the API to write a PPAT entry back to
>> PPAT MMIO registers. The caller doesn't need to care about the PPAT MMIO
>> layout, since the layout is different between different GENs.
>>
>> The "match_pat_value" will try to compare two PAT entries and give a score
>> to indicate how perfect they match with each other. The most important
>> attribute is "cache attribute", which affects the correctness and has to
>> be matched. Other attributes gain different scores by the their
>> importance in a partial match.
>>
>> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gvt/gtt.c | 81 ++++++++++++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/gvt/gtt.h |  9 +++++
>>   2 files changed, 90 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
>> index e6dfc33..16bfca9 100644
>> --- a/drivers/gpu/drm/i915/gvt/gtt.c
>> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
>> @@ -402,6 +402,80 @@ DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
>>   DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
>>   DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
>>   
>> +static unsigned int gen8_pat_get_value(u32 *mem, unsigned int index,
>> +				       struct intel_gvt *gvt)
>> +{
> 
> Really dislike to provide many kinds of usage interfaces for one function,
> it's easy to cause confusion and mostly unnecessary, although we have lot
> in gtt.c...and better to put driver struct as first parameter to align with
> other function conversion.
> 
>> +	struct drm_i915_private *dev_priv = gvt->dev_priv;
>> +	int reg_index = index / 4;
>> +	u32 buf[2];
>> +
>> +	if (WARN_ON(reg_index >= 2))
>> +		return 0;
>> +
>> +	if (!mem) {
>> +		mem = buf;
>> +		mem[reg_index] = reg_index ? I915_READ(GEN8_PRIVATE_PAT_HI) :
>> +				 I915_READ(GEN8_PRIVATE_PAT_LO);
>> +	}
>> +
>> +	index -= reg_index * 4;
>> +	return (mem[reg_index] >> (index * 8)) & 0x3f;
>> +}
>> +
>> +static void gen8_pat_set_value(u32 *mem, unsigned int index, unsigned int value,
>> +			       struct intel_gvt *gvt)
>> +{
>> +	struct drm_i915_private *dev_priv = gvt->dev_priv;
>> +	int reg_index = index / 4;
>> +	u32 buf[2];
>> +	bool writeback = false;
>> +
>> +	if (WARN_ON(reg_index >= 2))
>> +		return;
>> +
>> +	if (!mem) {
>> +		mem = buf;
>> +		writeback = true;
>> +		mem[reg_index] = reg_index ? I915_READ(GEN8_PRIVATE_PAT_HI) :
>> +				 I915_READ(GEN8_PRIVATE_PAT_LO);
>> +	}
>> +
>> +	index -= reg_index * 4;
>> +
>> +	mem[reg_index] &= ~(0xff << (index * 8));
>> +	mem[reg_index] |= ((value & 0x3f) << (index * 8));
>> +
>> +	if (writeback) {
>> +		if (reg_index)
>> +			I915_WRITE(GEN8_PRIVATE_PAT_LO, mem[1]);
>> +		else
>> +			I915_WRITE(GEN8_PRIVATE_PAT_LO, mem[0]);
>> +	}
>> +}
>> +
>> +#define gen8_pat_ca(v) ((v) & 0x3)
>> +#define gen8_pat_tc(v) ((v) >> 2 & 0x3)
>> +#define gen8_pat_age(v) ((v) >> 4 & 0x3)
>> +
>> +static unsigned int gen8_pat_match_value(unsigned int src, unsigned int dst)
>> +{
>> +	unsigned int score = 0;
>> +
>> +	if (gen8_pat_ca(src) != gen8_pat_ca(dst))
>> +		return 0;
>> +
>> +	if (gen8_pat_age(src) == gen8_pat_age(dst))
>> +		score += 1;
>> +
>> +	if (gen8_pat_tc(src) == gen8_pat_tc(dst))
>> +		score += 2;
>> +
>> +	if (score == 3)
>> +		return ~0;
>> +
>> +	return score;
>> +}
>> +
>>   static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
>>   	.get_entry = gtt_get_entry64,
>>   	.set_entry = gtt_set_entry64,
>> @@ -421,6 +495,12 @@ static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
>>   	.gma_to_pml4_index = gen8_gma_to_pml4_index,
>>   };
>>   
>> +static struct intel_gvt_gtt_pat_ops gen8_pat_ops = {
>> +	.get_pat_value = gen8_pat_get_value,
>> +	.set_pat_value = gen8_pat_set_value,
>> +	.match_pat_value = gen8_pat_match_value,
>> +};
>> +
>>   static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p,
>>   		struct intel_gvt_gtt_entry *m)
>>   {
>> @@ -2267,6 +2347,7 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
>>   		|| IS_KABYLAKE(gvt->dev_priv)) {
>>   		gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
>>   		gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
>> +		gvt->gtt.pat_ops = &gen8_pat_ops;
>>   		gvt->gtt.mm_alloc_page_table = gen8_mm_alloc_page_table;
>>   		gvt->gtt.mm_free_page_table = gen8_mm_free_page_table;
>>   	} else {
>> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
>> index 30a4c8d..7a9eb05 100644
>> --- a/drivers/gpu/drm/i915/gvt/gtt.h
>> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
>> @@ -77,9 +77,18 @@ struct intel_gvt_gtt_gma_ops {
>>   	unsigned long (*gma_to_pml4_index)(unsigned long gma);
>>   };
>>   
>> +struct intel_gvt_gtt_pat_ops {
>> +	unsigned int (*get_pat_value)(u32 *mem, unsigned int index,
>> +				      struct intel_gvt *gvt);
>> +	void (*set_pat_value)(u32 *mem, unsigned int index, unsigned int value,
>> +			      struct intel_gvt *gvt);
>> +	unsigned int (*match_pat_value)(unsigned int src, unsigned int dst);
>> +};
>> +
>>   struct intel_gvt_gtt {
>>   	struct intel_gvt_gtt_pte_ops *pte_ops;
>>   	struct intel_gvt_gtt_gma_ops *gma_ops;
>> +	struct intel_gvt_gtt_pat_ops *pat_ops;
>>   	int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
>>   	void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
>>   	struct list_head oos_page_use_list_head;
>> -- 
>> 2.7.4
>>
> 
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Re: [RFC 2/7] drm/i915/gvt: Introduce GEN8 private PAT ops

[Zhenyu Wang]

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On 2017.08.16 05:31:10 +0800, Zhi Wang wrote:
> This patch introduces private PAT operations for GEN8.
> 
> The "get_pat_value" operation offers an API to get a PPAT entry from the
> virtual or physical PPAT MMIO registers. Similar with the "get_pat_value",
> the "set_pat_value" operation offers the API to write a PPAT entry back to
> PPAT MMIO registers. The caller doesn't need to care about the PPAT MMIO
> layout, since the layout is different between different GENs.
> 
> The "match_pat_value" will try to compare two PAT entries and give a score
> to indicate how perfect they match with each other. The most important
> attribute is "cache attribute", which affects the correctness and has to
> be matched. Other attributes gain different scores by the their
> importance in a partial match.
> 
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/gtt.c | 81 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/gvt/gtt.h |  9 +++++
>  2 files changed, 90 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index e6dfc33..16bfca9 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -402,6 +402,80 @@ DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
>  DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
>  DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
>  
> +static unsigned int gen8_pat_get_value(u32 *mem, unsigned int index,
> +				       struct intel_gvt *gvt)
> +{
> +	struct drm_i915_private *dev_priv = gvt->dev_priv;
> +	int reg_index = index / 4;
> +	u32 buf[2];
> +
> +	if (WARN_ON(reg_index >= 2))
> +		return 0;
> +
> +	if (!mem) {
> +		mem = buf;
> +		mem[reg_index] = reg_index ? I915_READ(GEN8_PRIVATE_PAT_HI) :
> +				 I915_READ(GEN8_PRIVATE_PAT_LO);
> +	}
> +
> +	index -= reg_index * 4;
> +	return (mem[reg_index] >> (index * 8)) & 0x3f;
> +}
> +
> +static void gen8_pat_set_value(u32 *mem, unsigned int index, unsigned int value,
> +			       struct intel_gvt *gvt)
> +{
> +	struct drm_i915_private *dev_priv = gvt->dev_priv;
> +	int reg_index = index / 4;
> +	u32 buf[2];
> +	bool writeback = false;
> +
> +	if (WARN_ON(reg_index >= 2))
> +		return;
> +
> +	if (!mem) {
> +		mem = buf;
> +		writeback = true;
> +		mem[reg_index] = reg_index ? I915_READ(GEN8_PRIVATE_PAT_HI) :
> +				 I915_READ(GEN8_PRIVATE_PAT_LO);
> +	}
> +
> +	index -= reg_index * 4;
> +
> +	mem[reg_index] &= ~(0xff << (index * 8));
> +	mem[reg_index] |= ((value & 0x3f) << (index * 8));
> +
> +	if (writeback) {
> +		if (reg_index)
> +			I915_WRITE(GEN8_PRIVATE_PAT_LO, mem[1]);
> +		else
> +			I915_WRITE(GEN8_PRIVATE_PAT_LO, mem[0]);
> +	}
> +}

Make sure you get runtime pm for mmio.

> +
> +#define gen8_pat_ca(v) ((v) & 0x3)
> +#define gen8_pat_tc(v) ((v) >> 2 & 0x3)
> +#define gen8_pat_age(v) ((v) >> 4 & 0x3)
> +
> +static unsigned int gen8_pat_match_value(unsigned int src, unsigned int dst)
> +{
> +	unsigned int score = 0;
> +
> +	if (gen8_pat_ca(src) != gen8_pat_ca(dst))
> +		return 0;
> +
> +	if (gen8_pat_age(src) == gen8_pat_age(dst))
> +		score += 1;
> +
> +	if (gen8_pat_tc(src) == gen8_pat_tc(dst))
> +		score += 2;

Can define more bits on age/target score to count for more precision.

> +
> +	if (score == 3)
> +		return ~0;
> +
> +	return score;
> +}
> +
>  static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
>  	.get_entry = gtt_get_entry64,
>  	.set_entry = gtt_set_entry64,
> @@ -421,6 +495,12 @@ static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
>  	.gma_to_pml4_index = gen8_gma_to_pml4_index,
>  };
>  
> +static struct intel_gvt_gtt_pat_ops gen8_pat_ops = {
> +	.get_pat_value = gen8_pat_get_value,
> +	.set_pat_value = gen8_pat_set_value,
> +	.match_pat_value = gen8_pat_match_value,
> +};
> +
>  static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p,
>  		struct intel_gvt_gtt_entry *m)
>  {
> @@ -2267,6 +2347,7 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
>  		|| IS_KABYLAKE(gvt->dev_priv)) {
>  		gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
>  		gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
> +		gvt->gtt.pat_ops = &gen8_pat_ops;
>  		gvt->gtt.mm_alloc_page_table = gen8_mm_alloc_page_table;
>  		gvt->gtt.mm_free_page_table = gen8_mm_free_page_table;
>  	} else {
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
> index 30a4c8d..7a9eb05 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.h
> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
> @@ -77,9 +77,18 @@ struct intel_gvt_gtt_gma_ops {
>  	unsigned long (*gma_to_pml4_index)(unsigned long gma);
>  };
>  
> +struct intel_gvt_gtt_pat_ops {
> +	unsigned int (*get_pat_value)(u32 *mem, unsigned int index,
> +				      struct intel_gvt *gvt);
> +	void (*set_pat_value)(u32 *mem, unsigned int index, unsigned int value,
> +			      struct intel_gvt *gvt);
> +	unsigned int (*match_pat_value)(unsigned int src, unsigned int dst);
> +};
> +
>  struct intel_gvt_gtt {
>  	struct intel_gvt_gtt_pte_ops *pte_ops;
>  	struct intel_gvt_gtt_gma_ops *gma_ops;
> +	struct intel_gvt_gtt_pat_ops *pat_ops;
>  	int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
>  	void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
>  	struct list_head oos_page_use_list_head;
> -- 
> 2.7.4
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

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[RFC 3/7] drm/i915: Introduce GEN8 {set, get} private PAT index ops

[Zhi Wang]

Introduce operations of {set, get} private PAT index to decode and encode
the private PAT index in a guest/shadow PPGTT page table entry.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c | 38 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/gtt.h |  3 +++
 2 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 16bfca9..c630015 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -378,6 +378,42 @@ static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
 }
 
 /*
+ * For GEN8 platform.
+ * PAT: bit 7, PCD: bit 4, PWT: bit 3.
+ * Index: index = 4 * PAT + 2 * PCD + PWT
+ */
+static unsigned int gen8_get_pat_index(struct intel_gvt_gtt_entry *e)
+{
+	u8 index = 0;
+
+	if (_PAGE_PWT & e->val64)
+		index |= (1 << 0);
+
+	if (_PAGE_PCD & e->val64)
+		index |= (1 << 1);
+
+	if (_PAGE_PAT & e->val64)
+		index |= (1 << 2);
+
+	return index;
+}
+
+static void gen8_set_pat_index(struct intel_gvt_gtt_entry *e,
+			       unsigned int index)
+{
+	e->val64 &= ~(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT);
+
+	if (index & (1 << 0))
+		e->val64 |= _PAGE_PWT;
+
+	if (index & (1 << 1))
+		e->val64 |= _PAGE_PCD;
+
+	if (index & (1 << 2))
+		e->val64 |= _PAGE_PAT;
+}
+
+/*
  * Per-platform GMA routines.
  */
 static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
@@ -484,6 +520,8 @@ static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
 	.test_pse = gen8_gtt_test_pse,
 	.get_pfn = gen8_gtt_get_pfn,
 	.set_pfn = gen8_gtt_set_pfn,
+	.get_pat_index = gen8_get_pat_index,
+	.set_pat_index = gen8_set_pat_index,
 };
 
 static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 7a9eb05..02f6bd9 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -66,6 +66,9 @@ struct intel_gvt_gtt_pte_ops {
 	bool (*test_pse)(struct intel_gvt_gtt_entry *e);
 	void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn);
 	unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e);
+	unsigned int (*get_pat_index)(struct intel_gvt_gtt_entry *e);
+	void (*set_pat_index)(struct intel_gvt_gtt_entry *e,
+			      unsigned int index);
 };
 
 struct intel_gvt_gtt_gma_ops {
-- 
2.7.4

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[RFC 4/7] drm/i915: Introduce dynamic private PAT management

[Zhi Wang]

To manage the dynamic private PAT entries, this patch introduces some
basic functionalities for getting and putting an expected private PAT
entry.

When building the private PAT mapping between virtual PPAT indexes and
physical PPAT indexes, GVT-g would check if there is already an usable
private PAT entry.

If it's a perfect match, it would be directly used.

If it's not a perfect match and there is still unused PPAT entry, GVT
will allocate a new PPAT entry index for a guest.

If it's not a perfect match and there is no available unused PPAT entry,
GVT will use the parital matched PPAT entry index.

Each dynamic PPAT entry is associated with a reference count. If no
vGPU is using it, it will be freed.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c | 100 +++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/gtt.h |   6 +++
 2 files changed, 106 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index c630015..6e19d7a 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -2254,6 +2254,103 @@ static int setup_spt_oos(struct intel_gvt *gvt)
 	return ret;
 }
 
+static void setup_private_pat(struct intel_gvt *gvt)
+{
+	struct drm_i915_private *dev_priv = gvt->dev_priv;
+	struct intel_gvt_gtt *gtt = &gvt->gtt;
+	struct intel_gvt_gtt_pat_ops *ops = gtt->pat_ops;
+	int i;
+
+	i = find_first_bit(dev_priv->avail_ppat_bitmap, gtt->max_ppat_index);
+	if (i >= gtt->max_ppat_index) {
+		DRM_DEBUG_DRIVER("no private PAT support\n");
+		return;
+	}
+
+	gtt->has_ppat = true;
+
+	/* Save available PPAT bitmap from host */
+	bitmap_copy(gtt->avail_ppat_bitmap, dev_priv->avail_ppat_bitmap,
+			gtt->max_ppat_index);
+
+	/* Read host PPAT configuration */
+	for_each_clear_bit(i, gtt->avail_ppat_bitmap, gtt->max_ppat_index)
+		gtt->ppat_value[i] = ops->get_pat_value(NULL, i, gvt);
+}
+
+static int get_private_pat_index(struct intel_gvt *gvt, u32 value)
+{
+	struct drm_i915_private *dev_priv = gvt->dev_priv;
+	struct intel_gvt_gtt *gtt = &gvt->gtt;
+	struct intel_gvt_gtt_pat_ops *ops = gtt->pat_ops;
+	int i, index, used;
+	unsigned int score, best_score;
+
+	if (WARN_ON(!gtt->has_ppat))
+		return 0;
+
+	score = best_score = 0;
+	used = 0;
+
+	/* First, find a suitable value from available configurations */
+	for_each_clear_bit(i, gtt->avail_ppat_bitmap, gtt->max_ppat_index) {
+		score = ops->match_pat_value(gtt->ppat_value[i], value);
+		/* Perfect match */
+		if (score == ~0) {
+			index = i;
+			goto found;
+		}
+
+		if (score > best_score) {
+			index = i;
+			best_score = score;
+		}
+		used++;
+	}
+
+	if (!best_score && used == gtt->max_ppat_index) {
+		DRM_ERROR("cannot find a suitable PPAT entry\n");
+		return -ENOSPC;
+	}
+
+	/*
+	 * Found a matched entry which is not perfect,
+	 * but we don't have a available free entry
+	 */
+	if (best_score && used == gtt->max_ppat_index)
+		goto found;
+
+	/* Allocate a new one */
+	index = find_first_bit(gtt->avail_ppat_bitmap, gtt->max_ppat_index);
+	clear_bit(index, gtt->avail_ppat_bitmap);
+	gtt->ppat_value[index] = value;
+	ops->set_pat_value(NULL, index, gtt->ppat_value[index], gvt);
+
+found:
+	/* Not need to increase reference for host entries.*/
+	if (test_bit(index, dev_priv->avail_ppat_bitmap))
+		return index;
+
+	atomic_inc(&gtt->ppat_refc[index]);
+	return index;
+}
+
+static void put_private_pat_index(struct intel_gvt *gvt, unsigned int index)
+{
+	struct drm_i915_private *dev_priv = gvt->dev_priv;
+	struct intel_gvt_gtt *gtt = &gvt->gtt;
+
+	if (WARN_ON(!gtt->has_ppat))
+		return;
+
+	/* Nothing to do with host PPAT configuration */
+	if (test_bit(index, dev_priv->avail_ppat_bitmap))
+		return;
+
+	if (atomic_dec_and_test(&gtt->ppat_refc[index]))
+		set_bit(index, gtt->avail_ppat_bitmap);
+}
+
 /**
  * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
  * @vgpu: a vGPU
@@ -2386,12 +2483,15 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
 		gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
 		gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
 		gvt->gtt.pat_ops = &gen8_pat_ops;
+		gvt->gtt.max_ppat_index = 8;
 		gvt->gtt.mm_alloc_page_table = gen8_mm_alloc_page_table;
 		gvt->gtt.mm_free_page_table = gen8_mm_free_page_table;
 	} else {
 		return -ENODEV;
 	}
 
+	setup_private_pat(gvt);
+
 	page = (void *)get_zeroed_page(GFP_KERNEL);
 	if (!page) {
 		gvt_err("fail to allocate scratch ggtt page\n");
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 02f6bd9..6cd4fc7 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -100,6 +100,12 @@ struct intel_gvt_gtt {
 
 	struct page *scratch_ggtt_page;
 	unsigned long scratch_ggtt_mfn;
+
+	DECLARE_BITMAP(avail_ppat_bitmap, MAX_PPAT_INDEX);
+	unsigned int ppat_value[MAX_PPAT_INDEX];
+	atomic_t ppat_refc[MAX_PPAT_INDEX];
+	unsigned int max_ppat_index;
+	bool has_ppat;
 };
 
 enum {
-- 
2.7.4

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[RFC 5/7] drm/i915/gvt: Introduce functions for retiring all shadow PPGTTs of a vGPU

[Zhi Wang]

Introduce a new function to retiring all shadow PPGTTs of a vGPU.

The shadow PPPGTs of a vGPU need to be invalidated if a guest modifies the
virtual private PPAT since the mapping between the virtual PPAT indexes
and the shadow PPAT indexes will be re-built after a guest writes a new
virtual PPAT configruation.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c | 23 +++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/gtt.h |  1 +
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 6e19d7a..1d7077d 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1745,6 +1745,11 @@ void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
 		return;
 
 	atomic_dec(&mm->pincount);
+
+	if (mm->need_rebuild) {
+		invalidate_mm(mm);
+		mm->need_rebuild = false;
+	}
 }
 
 /**
@@ -1798,6 +1803,24 @@ static int reclaim_one_mm(struct intel_gvt *gvt)
 	return 0;
 }
 
+static void retire_vgpu_ppgtt_mm(struct intel_vgpu *vgpu)
+{
+	struct intel_vgpu_mm *mm;
+	struct list_head *pos;
+
+	list_for_each(pos, &vgpu->gtt.mm_list_head) {
+		mm = container_of(pos, struct intel_vgpu_mm, list);
+
+		if (mm->type != INTEL_GVT_MM_PPGTT)
+			continue;
+		if (atomic_read(&mm->pincount)) {
+			mm->need_rebuild = true;
+			continue;
+		}
+		invalidate_mm(mm);
+	}
+}
+
 /*
  * GMA translation APIs.
  */
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 6cd4fc7..a83d1f0 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -147,6 +147,7 @@ struct intel_vgpu_mm {
 	int type;
 	bool initialized;
 	bool shadowed;
+	bool need_rebuild;
 
 	int page_table_entry_type;
 	u32 page_table_entry_size;
-- 
2.7.4

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[RFC 6/7] drm/i915/gvt: Introduce virtual private PAT support

[Zhi Wang]

Introduce PPAT MMIO handlers. The mapping between virtual PPAT indexes
and physical PPAT indexes needs to be re-built after a guest write its
virtual PPAT configuration.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c      | 26 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/gtt.h      |  4 +++-
 drivers/gpu/drm/i915/gvt/handlers.c | 16 ++++++++++++++--
 3 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 1d7077d..6ec2a03 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -2374,6 +2374,32 @@ static void put_private_pat_index(struct intel_gvt *gvt, unsigned int index)
 		set_bit(index, gtt->avail_ppat_bitmap);
 }
 
+int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu)
+{
+	struct intel_gvt *gvt = vgpu->gvt;
+	struct intel_gvt_gtt_pat_ops *ops = gvt->gtt.pat_ops;
+	struct intel_vgpu_gtt *gtt = &vgpu->gtt;
+	unsigned int value;
+	void *mem = &vgpu_vreg(vgpu, GEN8_PRIVATE_PAT_LO);
+	int i;
+
+	if (gtt->ppat_configured) {
+		/* Release all indexes first */
+		for (i = 0; i < gvt->gtt.max_ppat_index; i++)
+			put_private_pat_index(gvt, gtt->ppat_index[i]);
+	}
+
+	for (i = 0; i < gvt->gtt.max_ppat_index; i++) {
+		value = ops->get_pat_value(mem, i, NULL);
+		gtt->ppat_index[i] = get_private_pat_index(gvt, value);
+	}
+
+	retire_vgpu_ppgtt_mm(vgpu);
+
+	gtt->ppat_configured = true;
+	return 0;
+}
+
 /**
  * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
  * @vgpu: a vGPU
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index a83d1f0..ab3e771 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -223,7 +223,8 @@ struct intel_vgpu_gtt {
 	struct list_head oos_page_list_head;
 	struct list_head post_shadow_list_head;
 	struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
-
+	bool ppat_configured;
+	unsigned int ppat_index[MAX_PPAT_INDEX];
 };
 
 extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
@@ -234,6 +235,7 @@ extern int intel_gvt_init_gtt(struct intel_gvt *gvt);
 void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
 extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);
 
+extern int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu);
 extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
 		int page_table_level, void *root_entry);
 
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 825abfc..e07264f 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1369,6 +1369,18 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
 	return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
 }
 
+static int gen8_ppat_write(struct intel_vgpu *vgpu, unsigned int offset,
+		void *p_data, unsigned int bytes)
+{
+	int ret;
+
+	ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
+	if (ret)
+		return ret;
+
+	return intel_vgpu_update_virtual_ppat(vgpu);
+}
+
 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
 		unsigned int offset, void *p_data, unsigned int bytes)
 {
@@ -2543,8 +2555,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
 
 	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
 
-	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
-	MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
+	MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS, NULL, gen8_ppat_write);
+	MMIO_DH(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS, NULL, gen8_ppat_write);
 
 	MMIO_D(GAMTARBMODE, D_BDW_PLUS);
 
-- 
2.7.4

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Re: [RFC 6/7] drm/i915/gvt: Introduce virtual private PAT support

[Zhenyu Wang]

[-- Attachment #1.1: Type: text/plain, Size: 4369 bytes --]

On 2017.08.16 05:31:14 +0800, Zhi Wang wrote:
> Introduce PPAT MMIO handlers. The mapping between virtual PPAT indexes
> and physical PPAT indexes needs to be re-built after a guest write its
> virtual PPAT configuration.
> 
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/gtt.c      | 26 ++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/gvt/gtt.h      |  4 +++-
>  drivers/gpu/drm/i915/gvt/handlers.c | 16 ++++++++++++++--
>  3 files changed, 43 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 1d7077d..6ec2a03 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -2374,6 +2374,32 @@ static void put_private_pat_index(struct intel_gvt *gvt, unsigned int index)
>  		set_bit(index, gtt->avail_ppat_bitmap);
>  }
>  
> +int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu)
> +{
> +	struct intel_gvt *gvt = vgpu->gvt;
> +	struct intel_gvt_gtt_pat_ops *ops = gvt->gtt.pat_ops;
> +	struct intel_vgpu_gtt *gtt = &vgpu->gtt;
> +	unsigned int value;
> +	void *mem = &vgpu_vreg(vgpu, GEN8_PRIVATE_PAT_LO);
> +	int i;
> +
> +	if (gtt->ppat_configured) {
> +		/* Release all indexes first */
> +		for (i = 0; i < gvt->gtt.max_ppat_index; i++)
> +			put_private_pat_index(gvt, gtt->ppat_index[i]);
> +	}
> +
> +	for (i = 0; i < gvt->gtt.max_ppat_index; i++) {
> +		value = ops->get_pat_value(mem, i, NULL);
> +		gtt->ppat_index[i] = get_private_pat_index(gvt, value);
> +	}

Looks those part in 4/7 should be in this one for easier review.

And how to handle if really no ppat entry available? Should we define
some PV interface for guest on sane usage? And as with this new handler
for PPAT regs, should remove that from save/restore list too?

> +
> +	retire_vgpu_ppgtt_mm(vgpu);
> +
> +	gtt->ppat_configured = true;
> +	return 0;
> +}
> +
>  /**
>   * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
>   * @vgpu: a vGPU
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
> index a83d1f0..ab3e771 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.h
> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
> @@ -223,7 +223,8 @@ struct intel_vgpu_gtt {
>  	struct list_head oos_page_list_head;
>  	struct list_head post_shadow_list_head;
>  	struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
> -
> +	bool ppat_configured;
> +	unsigned int ppat_index[MAX_PPAT_INDEX];
>  };
>  
>  extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
> @@ -234,6 +235,7 @@ extern int intel_gvt_init_gtt(struct intel_gvt *gvt);
>  void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
>  extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);
>  
> +extern int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu);
>  extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
>  		int page_table_level, void *root_entry);
>  
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 825abfc..e07264f 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1369,6 +1369,18 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
>  	return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
>  }
>  
> +static int gen8_ppat_write(struct intel_vgpu *vgpu, unsigned int offset,
> +		void *p_data, unsigned int bytes)
> +{
> +	int ret;
> +
> +	ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
> +	if (ret)
> +		return ret;
> +
> +	return intel_vgpu_update_virtual_ppat(vgpu);
> +}
> +
>  static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
>  		unsigned int offset, void *p_data, unsigned int bytes)
>  {
> @@ -2543,8 +2555,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
>  
>  	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>  
> -	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
> -	MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
> +	MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS, NULL, gen8_ppat_write);
> +	MMIO_DH(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS, NULL, gen8_ppat_write);
>  
>  	MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>  
> -- 
> 2.7.4
> 

-- 
Open Source Technology Center, Intel ltd.

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Re: [RFC 6/7] drm/i915/gvt: Introduce virtual private PAT support

[Zhi Wang]

Yes. They will be removed after this feature checked-in. The discussion 
before is at least host should provide all collections of cache 
attribute so we will have a partial match.

On 08/16/17 13:18, Zhenyu Wang wrote:
> On 2017.08.16 05:31:14 +0800, Zhi Wang wrote:
>> Introduce PPAT MMIO handlers. The mapping between virtual PPAT indexes
>> and physical PPAT indexes needs to be re-built after a guest write its
>> virtual PPAT configuration.
>>
>> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gvt/gtt.c      | 26 ++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/gvt/gtt.h      |  4 +++-
>>   drivers/gpu/drm/i915/gvt/handlers.c | 16 ++++++++++++++--
>>   3 files changed, 43 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
>> index 1d7077d..6ec2a03 100644
>> --- a/drivers/gpu/drm/i915/gvt/gtt.c
>> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
>> @@ -2374,6 +2374,32 @@ static void put_private_pat_index(struct intel_gvt *gvt, unsigned int index)
>>   		set_bit(index, gtt->avail_ppat_bitmap);
>>   }
>>   
>> +int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu)
>> +{
>> +	struct intel_gvt *gvt = vgpu->gvt;
>> +	struct intel_gvt_gtt_pat_ops *ops = gvt->gtt.pat_ops;
>> +	struct intel_vgpu_gtt *gtt = &vgpu->gtt;
>> +	unsigned int value;
>> +	void *mem = &vgpu_vreg(vgpu, GEN8_PRIVATE_PAT_LO);
>> +	int i;
>> +
>> +	if (gtt->ppat_configured) {
>> +		/* Release all indexes first */
>> +		for (i = 0; i < gvt->gtt.max_ppat_index; i++)
>> +			put_private_pat_index(gvt, gtt->ppat_index[i]);
>> +	}
>> +
>> +	for (i = 0; i < gvt->gtt.max_ppat_index; i++) {
>> +		value = ops->get_pat_value(mem, i, NULL);
>> +		gtt->ppat_index[i] = get_private_pat_index(gvt, value);
>> +	}
> 
> Looks those part in 4/7 should be in this one for easier review.
> 
> And how to handle if really no ppat entry available? Should we define
> some PV interface for guest on sane usage? And as with this new handler
> for PPAT regs, should remove that from save/restore list too?
> 
>> +
>> +	retire_vgpu_ppgtt_mm(vgpu);
>> +
>> +	gtt->ppat_configured = true;
>> +	return 0;
>> +}
>> +
>>   /**
>>    * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
>>    * @vgpu: a vGPU
>> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
>> index a83d1f0..ab3e771 100644
>> --- a/drivers/gpu/drm/i915/gvt/gtt.h
>> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
>> @@ -223,7 +223,8 @@ struct intel_vgpu_gtt {
>>   	struct list_head oos_page_list_head;
>>   	struct list_head post_shadow_list_head;
>>   	struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
>> -
>> +	bool ppat_configured;
>> +	unsigned int ppat_index[MAX_PPAT_INDEX];
>>   };
>>   
>>   extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
>> @@ -234,6 +235,7 @@ extern int intel_gvt_init_gtt(struct intel_gvt *gvt);
>>   void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
>>   extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);
>>   
>> +extern int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu);
>>   extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
>>   		int page_table_level, void *root_entry);
>>   
>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>> index 825abfc..e07264f 100644
>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>> @@ -1369,6 +1369,18 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
>>   	return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
>>   }
>>   
>> +static int gen8_ppat_write(struct intel_vgpu *vgpu, unsigned int offset,
>> +		void *p_data, unsigned int bytes)
>> +{
>> +	int ret;
>> +
>> +	ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
>> +	if (ret)
>> +		return ret;
>> +
>> +	return intel_vgpu_update_virtual_ppat(vgpu);
>> +}
>> +
>>   static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
>>   		unsigned int offset, void *p_data, unsigned int bytes)
>>   {
>> @@ -2543,8 +2555,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
>>   
>>   	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>   
>> -	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
>> -	MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>> +	MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS, NULL, gen8_ppat_write);
>> +	MMIO_DH(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS, NULL, gen8_ppat_write);
>>   
>>   	MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>   
>> -- 
>> 2.7.4
>>
> 
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Re: [RFC 6/7] drm/i915/gvt: Introduce virtual private PAT support

[Zhenyu Wang]

[-- Attachment #1.1: Type: text/plain, Size: 5730 bytes --]

On 2017.08.16 21:48:24 +0800, Zhi Wang wrote:
> Yes. They will be removed after this feature checked-in.

That should be in this series too for whole picture.

> The discussion
> before is at least host should provide all collections of cache attribute so
> we will have a partial match.
>

PAT index is not enough to hold for all combinations. So can improve match
search for more details on age/location for best match. And as this is not
like other hw resource which can be assigned when vgpu create, but be setup
at vgpu run time, maybe show current ppat setting to guest e.g as hw default
for vgpu, guest can adjust for that so won't cause surprise on cache penalty?
Or at lease should output warning..

> On 08/16/17 13:18, Zhenyu Wang wrote:
> > On 2017.08.16 05:31:14 +0800, Zhi Wang wrote:
> > > Introduce PPAT MMIO handlers. The mapping between virtual PPAT indexes
> > > and physical PPAT indexes needs to be re-built after a guest write its
> > > virtual PPAT configuration.
> > > 
> > > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/gvt/gtt.c      | 26 ++++++++++++++++++++++++++
> > >   drivers/gpu/drm/i915/gvt/gtt.h      |  4 +++-
> > >   drivers/gpu/drm/i915/gvt/handlers.c | 16 ++++++++++++++--
> > >   3 files changed, 43 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> > > index 1d7077d..6ec2a03 100644
> > > --- a/drivers/gpu/drm/i915/gvt/gtt.c
> > > +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> > > @@ -2374,6 +2374,32 @@ static void put_private_pat_index(struct intel_gvt *gvt, unsigned int index)
> > >   		set_bit(index, gtt->avail_ppat_bitmap);
> > >   }
> > > +int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu)
> > > +{
> > > +	struct intel_gvt *gvt = vgpu->gvt;
> > > +	struct intel_gvt_gtt_pat_ops *ops = gvt->gtt.pat_ops;
> > > +	struct intel_vgpu_gtt *gtt = &vgpu->gtt;
> > > +	unsigned int value;
> > > +	void *mem = &vgpu_vreg(vgpu, GEN8_PRIVATE_PAT_LO);
> > > +	int i;
> > > +
> > > +	if (gtt->ppat_configured) {
> > > +		/* Release all indexes first */
> > > +		for (i = 0; i < gvt->gtt.max_ppat_index; i++)
> > > +			put_private_pat_index(gvt, gtt->ppat_index[i]);
> > > +	}
> > > +
> > > +	for (i = 0; i < gvt->gtt.max_ppat_index; i++) {
> > > +		value = ops->get_pat_value(mem, i, NULL);
> > > +		gtt->ppat_index[i] = get_private_pat_index(gvt, value);
> > > +	}
> > 
> > Looks those part in 4/7 should be in this one for easier review.
> > 
> > And how to handle if really no ppat entry available? Should we define
> > some PV interface for guest on sane usage? And as with this new handler
> > for PPAT regs, should remove that from save/restore list too?
> > 
> > > +
> > > +	retire_vgpu_ppgtt_mm(vgpu);
> > > +
> > > +	gtt->ppat_configured = true;
> > > +	return 0;
> > > +}
> > > +
> > >   /**
> > >    * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
> > >    * @vgpu: a vGPU
> > > diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
> > > index a83d1f0..ab3e771 100644
> > > --- a/drivers/gpu/drm/i915/gvt/gtt.h
> > > +++ b/drivers/gpu/drm/i915/gvt/gtt.h
> > > @@ -223,7 +223,8 @@ struct intel_vgpu_gtt {
> > >   	struct list_head oos_page_list_head;
> > >   	struct list_head post_shadow_list_head;
> > >   	struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
> > > -
> > > +	bool ppat_configured;
> > > +	unsigned int ppat_index[MAX_PPAT_INDEX];
> > >   };
> > >   extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
> > > @@ -234,6 +235,7 @@ extern int intel_gvt_init_gtt(struct intel_gvt *gvt);
> > >   void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
> > >   extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);
> > > +extern int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu);
> > >   extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
> > >   		int page_table_level, void *root_entry);
> > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> > > index 825abfc..e07264f 100644
> > > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > > @@ -1369,6 +1369,18 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
> > >   	return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
> > >   }
> > > +static int gen8_ppat_write(struct intel_vgpu *vgpu, unsigned int offset,
> > > +		void *p_data, unsigned int bytes)
> > > +{
> > > +	int ret;
> > > +
> > > +	ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
> > > +	if (ret)
> > > +		return ret;
> > > +
> > > +	return intel_vgpu_update_virtual_ppat(vgpu);
> > > +}
> > > +
> > >   static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
> > >   		unsigned int offset, void *p_data, unsigned int bytes)
> > >   {
> > > @@ -2543,8 +2555,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
> > >   	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
> > > -	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
> > > -	MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
> > > +	MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS, NULL, gen8_ppat_write);
> > > +	MMIO_DH(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS, NULL, gen8_ppat_write);
> > >   	MMIO_D(GAMTARBMODE, D_BDW_PLUS);
> > > -- 
> > > 2.7.4
> > > 
> > 
> _______________________________________________
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> intel-gvt-dev@lists.freedesktop.org
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Re: [RFC 6/7] drm/i915/gvt: Introduce virtual private PAT support

[Wang, Zhi A]

-----Original Message-----
From: Zhenyu Wang [mailto:zhenyuw@linux.intel.com] 
Sent: Wednesday, August 16, 2017 2:13 PM
To: Wang, Zhi A <zhi.a.wang@intel.com>
Cc: intel-gfx@lists.freedesktop.org; joonas.lahtinen@linux.intel.com; intel-gvt-dev@lists.freedesktop.org; chris@chris-wilson.co.uk
Subject: Re: [RFC 6/7] drm/i915/gvt: Introduce virtual private PAT support

On 2017.08.16 21:48:24 +0800, Zhi Wang wrote:
> Yes. They will be removed after this feature checked-in.

That should be in this series too for whole picture.

> The discussion
> before is at least host should provide all collections of cache 
> attribute so we will have a partial match.
>

PAT index is not enough to hold for all combinations. So can improve match search for more details on age/location for best match. And as this is not like other hw resource which can be assigned when vgpu create, but be setup at vgpu run time, maybe show current ppat setting to guest e.g as hw default for vgpu, guest can adjust for that so won't cause surprise on cache penalty?
Or at lease should output warning..

The match you said is already in the code, see PATCH 4.

More debug message will be introduced in [PATCH]. The first V1 is to show how GVT-g use the bitmap in i915 and if i915 developer agree to put these management logic in GVT-g.

> On 08/16/17 13:18, Zhenyu Wang wrote:
> > On 2017.08.16 05:31:14 +0800, Zhi Wang wrote:
> > > Introduce PPAT MMIO handlers. The mapping between virtual PPAT 
> > > indexes and physical PPAT indexes needs to be re-built after a 
> > > guest write its virtual PPAT configuration.
> > > 
> > > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/gvt/gtt.c      | 26 ++++++++++++++++++++++++++
> > >   drivers/gpu/drm/i915/gvt/gtt.h      |  4 +++-
> > >   drivers/gpu/drm/i915/gvt/handlers.c | 16 ++++++++++++++--
> > >   3 files changed, 43 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gvt/gtt.c 
> > > b/drivers/gpu/drm/i915/gvt/gtt.c index 1d7077d..6ec2a03 100644
> > > --- a/drivers/gpu/drm/i915/gvt/gtt.c
> > > +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> > > @@ -2374,6 +2374,32 @@ static void put_private_pat_index(struct intel_gvt *gvt, unsigned int index)
> > >   		set_bit(index, gtt->avail_ppat_bitmap);
> > >   }
> > > +int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu) {
> > > +	struct intel_gvt *gvt = vgpu->gvt;
> > > +	struct intel_gvt_gtt_pat_ops *ops = gvt->gtt.pat_ops;
> > > +	struct intel_vgpu_gtt *gtt = &vgpu->gtt;
> > > +	unsigned int value;
> > > +	void *mem = &vgpu_vreg(vgpu, GEN8_PRIVATE_PAT_LO);
> > > +	int i;
> > > +
> > > +	if (gtt->ppat_configured) {
> > > +		/* Release all indexes first */
> > > +		for (i = 0; i < gvt->gtt.max_ppat_index; i++)
> > > +			put_private_pat_index(gvt, gtt->ppat_index[i]);
> > > +	}
> > > +
> > > +	for (i = 0; i < gvt->gtt.max_ppat_index; i++) {
> > > +		value = ops->get_pat_value(mem, i, NULL);
> > > +		gtt->ppat_index[i] = get_private_pat_index(gvt, value);
> > > +	}
> > 
> > Looks those part in 4/7 should be in this one for easier review.
> > 
> > And how to handle if really no ppat entry available? Should we 
> > define some PV interface for guest on sane usage? And as with this 
> > new handler for PPAT regs, should remove that from save/restore list too?
> > 
> > > +
> > > +	retire_vgpu_ppgtt_mm(vgpu);
> > > +
> > > +	gtt->ppat_configured = true;
> > > +	return 0;
> > > +}
> > > +
> > >   /**
> > >    * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
> > >    * @vgpu: a vGPU
> > > diff --git a/drivers/gpu/drm/i915/gvt/gtt.h 
> > > b/drivers/gpu/drm/i915/gvt/gtt.h index a83d1f0..ab3e771 100644
> > > --- a/drivers/gpu/drm/i915/gvt/gtt.h
> > > +++ b/drivers/gpu/drm/i915/gvt/gtt.h
> > > @@ -223,7 +223,8 @@ struct intel_vgpu_gtt {
> > >   	struct list_head oos_page_list_head;
> > >   	struct list_head post_shadow_list_head;
> > >   	struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
> > > -
> > > +	bool ppat_configured;
> > > +	unsigned int ppat_index[MAX_PPAT_INDEX];
> > >   };
> > >   extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu); @@ 
> > > -234,6 +235,7 @@ extern int intel_gvt_init_gtt(struct intel_gvt *gvt);
> > >   void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
> > >   extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);
> > > +extern int intel_vgpu_update_virtual_ppat(struct intel_vgpu 
> > > +*vgpu);
> > >   extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
> > >   		int page_table_level, void *root_entry); diff --git 
> > > a/drivers/gpu/drm/i915/gvt/handlers.c 
> > > b/drivers/gpu/drm/i915/gvt/handlers.c
> > > index 825abfc..e07264f 100644
> > > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > > @@ -1369,6 +1369,18 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
> > >   	return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
> > >   }
> > > +static int gen8_ppat_write(struct intel_vgpu *vgpu, unsigned int offset,
> > > +		void *p_data, unsigned int bytes) {
> > > +	int ret;
> > > +
> > > +	ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
> > > +	if (ret)
> > > +		return ret;
> > > +
> > > +	return intel_vgpu_update_virtual_ppat(vgpu);
> > > +}
> > > +
> > >   static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
> > >   		unsigned int offset, void *p_data, unsigned int bytes)
> > >   {
> > > @@ -2543,8 +2555,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
> > >   	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
> > > -	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
> > > -	MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
> > > +	MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS, NULL, gen8_ppat_write);
> > > +	MMIO_DH(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS, NULL, gen8_ppat_write);
> > >   	MMIO_D(GAMTARBMODE, D_BDW_PLUS);
> > > --
> > > 2.7.4
> > > 
> > 
> _______________________________________________
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> intel-gvt-dev@lists.freedesktop.org
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[RFC 7/7] drm/i915/gvt: Translate virtual PPAT indexes

[Zhi Wang]

Translate virtual PPAT indexes into physical PPAT indexes, according to
the mapping between virtual PPAT indexes and physical PPAT indexes during
building a PPGTT shadow page table.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 6ec2a03..5487375 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -539,6 +539,24 @@ static struct intel_gvt_gtt_pat_ops gen8_pat_ops = {
 	.match_pat_value = gen8_pat_match_value,
 };
 
+static inline void translate_ppat(struct intel_vgpu *vgpu,
+			     struct intel_gvt_gtt_entry *ge,
+			     struct intel_gvt_gtt_entry *se)
+{
+	struct intel_gvt *gvt = vgpu->gvt;
+	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+
+	unsigned int virtual_ppat_index;
+
+	if (!gvt->gtt.has_ppat)
+		return;
+
+	WARN_ON(!vgpu->gtt.ppat_configured);
+
+	virtual_ppat_index = ops->get_pat_index(ge);
+	ops->set_pat_index(se, vgpu->gtt.ppat_index[virtual_ppat_index]);
+}
+
 static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p,
 		struct intel_gvt_gtt_entry *m)
 {
@@ -559,6 +577,8 @@ static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p,
 	}
 
 	ops->set_pfn(m, mfn);
+
+	translate_ppat(vgpu, p, m);
 	return 0;
 }
 
@@ -1051,6 +1071,7 @@ static struct intel_vgpu_ppgtt_spt *ppgtt_populate_shadow_page_by_guest_entry(
 	return ERR_PTR(ret);
 }
 
+
 static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
 		struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
 {
@@ -1060,6 +1081,8 @@ static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
 	se->val64 = ge->val64;
 
 	ops->set_pfn(se, s->shadow_page.mfn);
+
+	translate_ppat(s->vgpu, ge, se);
 }
 
 static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
-- 
2.7.4

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Re: [RFC 0/7] Introduce dynamic PPAT managment for GVT-g

[Zhi Wang]

Oops. Actually only this first one is a change for i915. :( Will fix 
that in further.

On 08/16/17 05:31, Zhi Wang wrote:
> This patchset introduces dynamic PPAT managment for GVT-g.
> 
> Since different VM can have different PPAT configurations, GVT-g needs
> to map the virtual private PAT configuration into the physical private
> PAT between different VMs.
> 
> More background of this patchset can be found at:
> https://lists.freedesktop.org/archives/intel-gfx/2017-August/135415.html
> 
> Zhi Wang (7):
>    drm/i915: Introduce a bitmap to indicate available PPAT entries
>    drm/i915/gvt: Introduce GEN8 private PAT ops
>    drm/i915: Introduce GEN8 {set, get} private PAT index ops
>    drm/i915: Introduce dynamic private PAT management
>    drm/i915/gvt: Introduce functions for retiring all shadow PPGTTs of a
>      vGPU
>    drm/i915/gvt: Introduce virtual private PAT support
>    drm/i915/gvt: Translate virtual PPAT indexes
> 
>   drivers/gpu/drm/i915/gvt/gtt.c      | 291 ++++++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/gvt/gtt.h      |  23 ++-
>   drivers/gpu/drm/i915/gvt/handlers.c |  16 +-
>   drivers/gpu/drm/i915/i915_drv.h     |   3 +
>   drivers/gpu/drm/i915/i915_gem_gtt.c |  13 +-
>   5 files changed, 342 insertions(+), 4 deletions(-)
> 
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