* [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write
@ 2017-09-07 15:40 Oscar Mateo
2017-09-07 15:40 ` [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort " Oscar Mateo
` (6 more replies)
0 siblings, 7 replies; 10+ messages in thread
From: Oscar Mateo @ 2017-09-07 15:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Mika Kuoppala
Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing
it on every context creation is overkill (and wrong).
v2: Missing end parenthesis
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 23812ec..4600325 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -985,8 +985,9 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
/* WaInPlaceDecompressionHang:skl */
if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
- WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
/* WaDisableLSQCROPERFforOCL:skl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1059,8 +1060,9 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
/* WaInPlaceDecompressionHang:bxt */
if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
- WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
return 0;
}
@@ -1089,8 +1091,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
/* WaInPlaceDecompressionHang:cnl */
- WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
/* WaPushConstantDereferenceHoldDisable:cnl */
WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
@@ -1143,8 +1146,9 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
/* WaInPlaceDecompressionHang:kbl */
- WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
/* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1196,8 +1200,9 @@ static int cfl_init_workarounds(struct intel_engine_cs *engine)
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
/* WaInPlaceDecompressionHang:cfl */
- WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort into a simple reg write
2017-09-07 15:40 [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write Oscar Mateo
@ 2017-09-07 15:40 ` Oscar Mateo
2017-09-07 15:40 ` [PATCH 3/6] drm/i915: WaPushConstantDereferenceHoldDisable needs to modify a masked register Oscar Mateo
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Oscar Mateo @ 2017-09-07 15:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Mika Kuoppala
GAMT_CHKN_BIT_REG does not live in the context.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 4600325..7c384d5 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1072,10 +1072,11 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
- /* WaDisableI2mCycleOnWRPort: cnl (pre-prod) */
+ /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
- WA_SET_BIT(GAMT_CHKN_BIT_REG,
- GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
+ I915_WRITE(GAMT_CHKN_BIT_REG,
+ (I915_READ(GAMT_CHKN_BIT_REG) |
+ GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT));
/* WaForceContextSaveRestoreNonCoherent:cnl */
WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
--
1.9.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 3/6] drm/i915: WaPushConstantDereferenceHoldDisable needs to modify a masked register
2017-09-07 15:40 [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write Oscar Mateo
2017-09-07 15:40 ` [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort " Oscar Mateo
@ 2017-09-07 15:40 ` Oscar Mateo
2017-09-07 15:40 ` [PATCH 4/6] drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write Oscar Mateo
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Oscar Mateo @ 2017-09-07 15:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Mika Kuoppala
So do it correctly.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 7c384d5..cdd86ef 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1097,7 +1097,7 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
/* WaPushConstantDereferenceHoldDisable:cnl */
- WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
/* FtrEnableFastAnisoL1BankingFix: cnl */
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
--
1.9.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/6] drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write
2017-09-07 15:40 [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write Oscar Mateo
2017-09-07 15:40 ` [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort " Oscar Mateo
2017-09-07 15:40 ` [PATCH 3/6] drm/i915: WaPushConstantDereferenceHoldDisable needs to modify a masked register Oscar Mateo
@ 2017-09-07 15:40 ` Oscar Mateo
2017-09-07 15:40 ` [PATCH 5/6] drm/i915: Transform WaDisableDynamicCreditSharing into a simple register write Oscar Mateo
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Oscar Mateo @ 2017-09-07 15:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Mika Kuoppala
GEN7_UCGCTL4 does not live in the context.
v2: Missing parenthesis
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index cdd86ef..829552b 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -981,7 +981,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
GEN9_GAPS_TSV_CREDIT_DISABLE));
/* WaDisableGafsUnitClkGating:skl */
- WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
+ GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
/* WaInPlaceDecompressionHang:skl */
if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
@@ -1139,7 +1140,8 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaDisableGafsUnitClkGating:kbl */
- WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
+ GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
/* WaDisableSbeCacheDispatchPortSharing:kbl */
WA_SET_BIT_MASKED(
@@ -1193,7 +1195,8 @@ static int cfl_init_workarounds(struct intel_engine_cs *engine)
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaDisableGafsUnitClkGating:cfl */
- WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
+ GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
/* WaDisableSbeCacheDispatchPortSharing:cfl */
WA_SET_BIT_MASKED(
--
1.9.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 5/6] drm/i915: Transform WaDisableDynamicCreditSharing into a simple register write
2017-09-07 15:40 [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write Oscar Mateo
` (2 preceding siblings ...)
2017-09-07 15:40 ` [PATCH 4/6] drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write Oscar Mateo
@ 2017-09-07 15:40 ` Oscar Mateo
2017-09-07 15:40 ` [PATCH 6/6] drm/i915: Transform WaDisablePooledEuLoadBalancingFix " Oscar Mateo
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Oscar Mateo @ 2017-09-07 15:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Mika Kuoppala
GAMT_CHKN_BIT_REG does not live in the context image.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 829552b..a6e048a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1126,8 +1126,9 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
/* WaDisableDynamicCreditSharing:kbl */
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
- WA_SET_BIT(GAMT_CHKN_BIT_REG,
- GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
+ I915_WRITE(GAMT_CHKN_BIT_REG,
+ (I915_READ(GAMT_CHKN_BIT_REG) |
+ GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING));
/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
--
1.9.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 6/6] drm/i915: Transform WaDisablePooledEuLoadBalancingFix into a simple register write
2017-09-07 15:40 [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write Oscar Mateo
` (3 preceding siblings ...)
2017-09-07 15:40 ` [PATCH 5/6] drm/i915: Transform WaDisableDynamicCreditSharing into a simple register write Oscar Mateo
@ 2017-09-07 15:40 ` Oscar Mateo
2017-09-07 15:58 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write Patchwork
2017-09-07 20:26 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 10+ messages in thread
From: Oscar Mateo @ 2017-09-07 15:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Mika Kuoppala
FF_SLICE_CS_CHICKEN2 does not belong to the context image.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a6e048a..c7d0cd9 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1024,8 +1024,8 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
/* WaDisablePooledEuLoadBalancingFix:bxt */
if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
- WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
- GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
+ I915_WRITE(FF_SLICE_CS_CHICKEN2,
+ _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
}
/* WaDisableSbeCacheDispatchPortSharing:bxt */
--
1.9.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write
2017-09-07 15:40 [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write Oscar Mateo
` (4 preceding siblings ...)
2017-09-07 15:40 ` [PATCH 6/6] drm/i915: Transform WaDisablePooledEuLoadBalancingFix " Oscar Mateo
@ 2017-09-07 15:58 ` Patchwork
2017-09-07 21:02 ` Chris Wilson
2017-09-07 20:26 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 1 reply; 10+ messages in thread
From: Patchwork @ 2017-09-07 15:58 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write
URL : https://patchwork.freedesktop.org/series/29957/
State : success
== Summary ==
Series 29957v1 series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write
https://patchwork.freedesktop.org/api/1.0/series/29957/revisions/1/mbox/
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass -> SKIP (fi-cfl-s) fdo#102294
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:452s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:443s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:364s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:560s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:257s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:528s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:522s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:520s
fi-cfl-s total:289 pass:249 dwarn:4 dfail:0 fail:0 skip:36 time:460s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:437s
fi-glk-2a total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:609s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:448s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:425s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:428s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:510s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:513s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:603s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:600s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:525s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:473s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:538s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:520s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:447s
fi-skl-x1585l total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:488s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:555s
fi-snb-2600 total:289 pass:248 dwarn:0 dfail:0 fail:2 skip:39 time:408s
fi-ivb-3770 failed to connect after reboot
9d8ff561fb222119a1a9faa1b19e4cc35b4a983d drm-tip: 2017y-09m-07d-15h-07m-16s UTC integration manifest
a8043e63f4c8 drm/i915: Transform WaDisablePooledEuLoadBalancingFix into a simple register write
141a4e9d4965 drm/i915: Transform WaDisableDynamicCreditSharing into a simple register write
c26da1b2af60 drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write
8c5c78523c2b drm/i915: WaPushConstantDereferenceHoldDisable needs to modify a masked register
78c29263e94c drm/i915: Transform WaDisableI2mCycleOnWRPort into a simple reg write
ec51a4e70746 drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5610/
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^ permalink raw reply [flat|nested] 10+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write
2017-09-07 15:40 [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write Oscar Mateo
` (5 preceding siblings ...)
2017-09-07 15:58 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write Patchwork
@ 2017-09-07 20:26 ` Patchwork
6 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-09-07 20:26 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write
URL : https://patchwork.freedesktop.org/series/29957/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
Test kms_atomic_transition:
Subgroup plane-use-after-nonblocking-unbind:
fail -> INCOMPLETE (shard-hsw) fdo#101847
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#101847 https://bugs.freedesktop.org/show_bug.cgi?id=101847
shard-hsw total:2222 pass:1207 dwarn:0 dfail:0 fail:14 skip:1000 time:9437s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5610/shards.html
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write
@ 2017-09-07 0:15 Oscar Mateo
2017-09-07 0:15 ` [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort " Oscar Mateo
0 siblings, 1 reply; 10+ messages in thread
From: Oscar Mateo @ 2017-09-07 0:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Mika Kuoppala
Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing
it on every context creation is overkill (and wrong).
v2: Missing end parenthesis
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 23812ec..4600325 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -985,8 +985,9 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
/* WaInPlaceDecompressionHang:skl */
if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
- WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
/* WaDisableLSQCROPERFforOCL:skl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1059,8 +1060,9 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
/* WaInPlaceDecompressionHang:bxt */
if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
- WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
return 0;
}
@@ -1089,8 +1091,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
/* WaInPlaceDecompressionHang:cnl */
- WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
/* WaPushConstantDereferenceHoldDisable:cnl */
WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
@@ -1143,8 +1146,9 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
/* WaInPlaceDecompressionHang:kbl */
- WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
/* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1196,8 +1200,9 @@ static int cfl_init_workarounds(struct intel_engine_cs *engine)
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
/* WaInPlaceDecompressionHang:cfl */
- WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort into a simple reg write
2017-09-07 0:15 [PATCH 1/6] " Oscar Mateo
@ 2017-09-07 0:15 ` Oscar Mateo
0 siblings, 0 replies; 10+ messages in thread
From: Oscar Mateo @ 2017-09-07 0:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Mika Kuoppala
GAMT_CHKN_BIT_REG does not live in the context.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 4600325..7c384d5 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1072,10 +1072,11 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
- /* WaDisableI2mCycleOnWRPort: cnl (pre-prod) */
+ /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
- WA_SET_BIT(GAMT_CHKN_BIT_REG,
- GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
+ I915_WRITE(GAMT_CHKN_BIT_REG,
+ (I915_READ(GAMT_CHKN_BIT_REG) |
+ GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT));
/* WaForceContextSaveRestoreNonCoherent:cnl */
WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
--
1.9.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-09-07 21:02 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-09-07 15:40 [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write Oscar Mateo
2017-09-07 15:40 ` [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort " Oscar Mateo
2017-09-07 15:40 ` [PATCH 3/6] drm/i915: WaPushConstantDereferenceHoldDisable needs to modify a masked register Oscar Mateo
2017-09-07 15:40 ` [PATCH 4/6] drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write Oscar Mateo
2017-09-07 15:40 ` [PATCH 5/6] drm/i915: Transform WaDisableDynamicCreditSharing into a simple register write Oscar Mateo
2017-09-07 15:40 ` [PATCH 6/6] drm/i915: Transform WaDisablePooledEuLoadBalancingFix " Oscar Mateo
2017-09-07 15:58 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write Patchwork
2017-09-07 21:02 ` Chris Wilson
2017-09-07 20:26 ` ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2017-09-07 0:15 [PATCH 1/6] " Oscar Mateo
2017-09-07 0:15 ` [PATCH 2/6] drm/i915: Transform WaDisableI2mCycleOnWRPort " Oscar Mateo
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