[PATCH 26/43] drm/i915: Define Intel HDCP2.2 registers

From: Ramalingam C <ramalingam.c@intel.com>
To: seanpaul@chromium.org, intel-gfx@lists.freedesktop.org,
	rodrigo.vivi@intel.com, daniel.vetter@ffwll.ch
Cc: tomas.winkler@intel.com
Subject: [PATCH 26/43] drm/i915: Define Intel HDCP2.2 registers
Date: Wed, 14 Feb 2018 19:43:41 +0530	[thread overview]
Message-ID: <1518617638-21684-27-git-send-email-ramalingam.c@intel.com> (raw)
In-Reply-To: <1518617638-21684-1-git-send-email-ramalingam.c@intel.com>

Intel HDCP2.2 registers are defined with addr offsets and bit details.

Macros are defined for referencing the register offsets based on the
port index.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 120 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 120 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6afa5e5e7c1..6a57b12d8dab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2268,6 +2268,126 @@ enum i915_power_well_id {
 				   _PORT_TX_DW14_LN0_C) +		\
 	      _BXT_LANE_OFFSET(lane))
 
+/*
+ *HDCP Registers
+ **/
+
+/*
+ * HW register offsets are incresing in the order of B, C, D, A, F, E.
+ * But enum value increses in the order of A, B, C, D, E, F.
+ * So port numbers are adjusted for offset calculations.
+ */
+#define HDCP_PORT_INDEX_ADJUST(p)	(((p) == PORT_A ? PORT_E : \
+						(p) == PORT_E ? (0x6) : \
+						(p)) - 1)
+#define _MMIO_HDCP_PORT(p, a, b)	_MMIO_PORT(HDCP_PORT_INDEX_ADJUST(p), \
+						a, b)
+
+
+/* RO Registers for I915. Programmable from FW(ME) only */
+#define HDCP2_AUTH_DDI_A		0x66898
+#define HDCP2_AUTH_DDI_B		0x66598
+#define HDCP2_AUTH_DDI_C		0x66698
+#define HDCP2_AUTH_DDI_D		0x66798
+#define HDCP2_AUTH_DDI_E		0x66A98
+#define HDCP2_AUTH_DDI_F		0x66998
+#define   AUTH_LINK_AUTHENTICATED	(1 << 31)
+#define   AUTH_LINK_TYPE		(1 << 30)
+#define   AUTH_FORCE_CLR_INPUTCTR	(1 << 19)
+#define   AUTH_CLR_KEYS			(1 << 18)
+
+#define HDCP2_AUTH_DDI(port)		_MMIO_HDCP_PORT(port, \
+							HDCP2_AUTH_DDI_B, \
+							HDCP2_AUTH_DDI_C)
+
+
+/* Multi stream DP registers */
+/* RO Registers for I915. Programmable from FW(ME) only */
+#define HDCP2_AUTH_STREAM_A		0x66F00
+#define HDCP2_AUTH_STREAM_B		0x66F04
+#define HDCP2_AUTH_STREAM_C		0x66F08
+#define HDCP2_AUTH_STREAM_D		0x66F0C
+#define   AUTH_STREAM_TYPE		(1 << 31)
+
+#define HDCP2_AUTH_STREAM(stream)	_MMIO_PORT(stream, \
+						   HDCP2_AUTH_STREAM_A, \
+						   HDCP2_AUTH_STREAM_B)
+
+/* RW Registers for I915 */
+#define HDCP2_CTL_DDI_A			0x668B0
+#define HDCP2_CTL_DDI_B			0x665B0
+#define HDCP2_CTL_DDI_C			0x666B0
+#define HDCP2_CTL_DDI_D			0x667B0
+#define HDCP2_CTL_DDI_E			0x66AB0
+#define HDCP2_CTL_DDI_F			0x669B0
+#define   CTL_LINK_ENCRYPTION_REQ	(1 << 31)
+#define   CTL_VBID_TYPE_SELECT_SHIFT	29
+#define   CTL_VBID_TYPE_SELECT_MASK	(3 << CTL_VBID_TYPE_SELECT_SHIFT)
+
+#define HDCP2_CTR_DDI(port)		_MMIO_HDCP_PORT(port, HDCP2_CTL_DDI_B, \
+							HDCP2_CTL_DDI_C)
+
+/* RO only. For Debug purpose */
+#define HDCP2_INPUTCTR_DDI_A		0x668B8
+#define HDCP2_INPUTCTR_DDI_B		0x665B8
+#define HDCP2_INPUTCTR_DDI_C		0x666B8
+#define HDCP2_INPUTCTR_DDI_D		0x667B8
+#define HDCP2_INPUTCTR_DDI_E		0x66AB8
+#define HDCP2_INPUTCTR_DDI_F		0x669B8
+
+#define HDCP2_INPUTCTR_LO_DDI(port)	_MMIO_HDCP_PORT(port, \
+							HDCP2_INPUTCTL_DDI_B, \
+							HDCP2_INPUTCTL_DDI_C)
+
+#define HDCP2_INPUTCTR_HI_DDI(port)	_MMIO_HDCP_PORT(port, \
+						(HDCP2_INPUTCTL_DDI_B + 4), \
+						(HDCP2_INPUTCTL_DDI_C + 4))
+
+/* RO Registers for I915. Programmable from FW(ME) only */
+#define HDCP2_RIV_DDI_A			0x66890
+#define HDCP2_RIV_DDI_B			0x66590
+#define HDCP2_RIV_DDI_C			0x66690
+#define HDCP2_RIV_DDI_D			0x66790
+#define HDCP2_RIV_DDI_E			0x66A90
+#define HDCP2_RIV_DDI_F			0x66990
+
+#define HDCP2_RIV_LO_DDI(port)		_MMIO_HDCP_PORT(port, HDCP2_RIV_DDI_B, \
+							HDCP2_RIV_DDI_C)
+
+#define HDCP2_RIV_HI_DDI(port)		_MMIO_HDCP_PORT(port, \
+							(HDCP2_RIV_DDI_B + 4), \
+							(HDCP2_RIV_DDI_C + 4))
+
+/* RO only. For Debug purpose */
+#define HDCP2_STATUS_DDI_A		0x668B4
+#define HDCP2_STATUS_DDI_B		0x665B4
+#define HDCP2_STATUS_DDI_C		0x666B4
+#define HDCP2_STATUS_DDI_D		0x667B4
+#define HDCP2_STATUS_DDI_E		0x66AB4
+#define HDCP2_STATUS_DDI_F		0x669B4
+#define   STREAM_ENCRYPTION_STATUS_A	(1 << 31)
+#define   STREAM_ENCRYPTION_STATUS_B	(1 << 30)
+#define   STREAM_ENCRYPTION_STATUS_C	(1 << 29)
+#define   LINK_TYPE_STATUS		(1 << 22)
+#define   LINK_AUTH_STATUS		(1 << 21)
+#define   LINK_ENCRYPTION_STATUS	(1 << 20)
+
+#define HDCP2_STATUS_DDI(port)		_MMIO_HDCP_PORT(port, \
+							HDCP2_STATUS_DDI_B, \
+							HDCP2_STATUS_DDI_C)
+
+/* RO only. For Debug purpose */
+#define HDCP2_STREAM_STATUS_A		0x668C0
+#define HDCP2_STREAM_STATUS_B		0x665C0
+#define HDCP2_STREAM_STATUS_C		0x666C0
+#define HDCP2_STREAM_STATUS_D		0x667C0
+#define   STREAM_ENCRYPTION_STATUS	(1 << 31)
+#define   STREAM_TYPE_STATUS		(1 << 30)
+
+#define HDCP2_STREAM_STATUS(stream)	_MMIO_HDCP_PORT(stream, \
+							HDCP2_STREAM_STATUS_B, \
+							HDCP2_STREAM_STATUS_C)
+
 /* UAIMI scratch pad register 1 */
 #define UAIMI_SPR1			_MMIO(0x4F074)
 /* SKL VccIO mask */
-- 
2.7.4

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