[PATCH 39/43] drm/i915: Implement the HDCP2.2 support for DP

[Ramalingam C <ramalingam.c@intel.com>]

Implements the DP adaptation specific HDCP2.2 functions
intel_hdcp2_shim.

These functions perform the DPCD read and write for communicating the
HDCP2.2 auth message back and forth.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 331 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 331 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6f6b4c8e3a42..241777398359 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5303,6 +5303,337 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
 	.hdcp_capable = intel_dp_hdcp_capable,
 };
 
+static inline
+int intel_dpcd_offset_for_hdcp2_msgid(uint8_t byte, unsigned int *offset)
+{
+	switch (byte) {
+	case AKE_INIT:
+		*offset = DP_HDCP_2_2_AKE_INIT_OFFSET;
+		break;
+	case AKE_SEND_CERT:
+		*offset = DP_HDCP_2_2_AKE_SEND_CERT_OFFSET;
+		break;
+	case AKE_NO_STORED_KM:
+		*offset = DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET;
+		break;
+	case AKE_STORED_KM:
+		*offset = DP_HDCP_2_2_AKE_STORED_KM_OFFSET;
+		break;
+	case AKE_SEND_HPRIME:
+		*offset = DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET;
+		break;
+	case AKE_SEND_PARING_INFO:
+		*offset = DP_HDCP_2_2_AKE_SEND_PARING_INFO_OFFSET;
+		break;
+	case LC_INIT:
+		*offset = DP_HDCP_2_2_LC_INIT_OFFSET;
+		break;
+	case LC_SEND_LPRIME:
+		*offset = DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET;
+		break;
+	case SKE_SEND_EKS:
+		*offset = DP_HDCP_2_2_SKE_SEND_EKS_OFFSET;
+		break;
+	case REP_SEND_RECVID_LIST:
+		*offset = DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET;
+		break;
+	case REP_SEND_ACK:
+		*offset = DP_HDCP_2_2_REP_SEND_ACK_OFFSET;
+		break;
+	case REP_STREAM_MANAGE:
+		*offset = DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET;
+		break;
+	case REP_STREAM_READY:
+		*offset = DP_HDCP_2_2_REP_STREAM_READY_OFFSET;
+		break;
+	case ERRATA_DP_STREAM_TYPE:
+		*offset = DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET;
+		break;
+	default:
+		DRM_ERROR("Unrecognized Msg ID\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static inline
+int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
+				union hdcp2_dp_rx_status *rx_status)
+{
+	ssize_t ret;
+
+	ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
+			       DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
+			       sizeof(union hdcp2_dp_rx_status));
+	if (ret != sizeof(union hdcp2_dp_rx_status)) {
+		DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", ret);
+		return ret >= 0 ? -EIO : ret;
+	}
+
+	return 0;
+}
+
+static inline
+int intel_dp_hdcp2_timeout_for_msg(uint8_t msg_id, bool paired)
+{
+	int timeout = -EINVAL;
+
+	switch (msg_id) {
+	case AKE_SEND_CERT:
+		timeout = HDCP_2_2_CERT_TIMEOUT;
+		break;
+	case AKE_SEND_HPRIME:
+		if (paired)
+			timeout = HDCP_2_2_HPRIME_PAIRED_TIMEOUT;
+		else
+			timeout = HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT;
+		break;
+	case AKE_SEND_PARING_INFO:
+		timeout = HDCP_2_2_PAIRING_TIMEOUT;
+		break;
+	case LC_SEND_LPRIME:
+		timeout = HDCP_2_2_DP_LPRIME_TIMEOUT;
+		break;
+	case REP_SEND_RECVID_LIST:
+		timeout = HDCP_2_2_RECVID_LIST_TIMEOUT;
+		break;
+	case REP_STREAM_READY:
+		timeout = HDCP_2_2_STREAM_READY_TIMEOUT;
+		break;
+	default:
+		DRM_ERROR("Unsupported msg_id: %d\n", (int)msg_id);
+	}
+	return timeout;
+}
+
+static inline
+int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
+				  uint8_t msg_id, bool *msg_ready)
+{
+	union hdcp2_dp_rx_status rx_status;
+	int ret;
+
+	*msg_ready = false;
+	ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
+	if (ret < 0)
+		return ret;
+
+	switch (msg_id) {
+	case AKE_SEND_HPRIME:
+		if (rx_status.fields.hprime_available)
+			*msg_ready = true;
+		break;
+	case AKE_SEND_PARING_INFO:
+		if (rx_status.fields.paring_available)
+			*msg_ready = true;
+		break;
+	case REP_SEND_RECVID_LIST:
+		if (rx_status.fields.ready)
+			*msg_ready = true;
+		break;
+	default:
+		DRM_DEBUG_KMS("Unidentified msg_id: %d\n", (int)msg_id);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+
+static inline ssize_t
+intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
+			    uint8_t msg_id)
+{
+	struct intel_dp *dp = &intel_dig_port->dp;
+	struct intel_hdcp *hdcp = dp->attached_connector->hdcp;
+	int ret, timeout;
+	bool msg_ready = false;
+
+	timeout = intel_dp_hdcp2_timeout_for_msg(msg_id, hdcp->is_paired);
+	switch (msg_id) {
+
+	/*
+	 * There is no way to detect the CERT, LPRIME and STREAM_READY
+	 * availability. So Wait for timeout and read the msg.
+	 */
+	case AKE_SEND_CERT:
+	case LC_SEND_LPRIME:
+	case REP_STREAM_READY:
+		mdelay(timeout);
+		ret = 0;
+		break;
+	case AKE_SEND_HPRIME:
+	case AKE_SEND_PARING_INFO:
+	case REP_SEND_RECVID_LIST:
+		wait_for_cp_irq(&hdcp->cp_irq_recved, timeout);
+		ret = hdcp2_detect_msg_availability(intel_dig_port, msg_id,
+						    &msg_ready);
+		if (!msg_ready)
+			ret = -ETIMEDOUT;
+		break;
+	default:
+		DRM_DEBUG_KMS("Unidentified msg_id: %d\n", (int)msg_id);
+		return -EINVAL;
+	}
+	if (ret)
+		DRM_ERROR("msg_id %d, ret %d, timeout(mSec): %d\n", msg_id, ret,
+			  timeout);
+	return ret;
+}
+
+static
+int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
+			     void *buf, size_t size)
+{
+	unsigned int offset;
+	uint8_t *byte = buf;
+	ssize_t ret, bytes_to_write, len;
+
+	if (intel_dpcd_offset_for_hdcp2_msgid(*byte, &offset) < 0)
+		return -EINVAL;
+
+	/* No msg_id in DP HDCP2.2 msgs */
+	bytes_to_write = size - 1;
+	byte++;
+
+	while (bytes_to_write) {
+		len = bytes_to_write > DRM_HDCP_MAX_AUX_LEN ?
+				DRM_HDCP_MAX_AUX_LEN : bytes_to_write;
+
+		ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, offset,
+					(void *)byte, len);
+		if (ret < 0)
+			return ret;
+
+		bytes_to_write -= ret;
+		byte += ret;
+		offset += ret;
+	}
+	return size;
+}
+
+static
+int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
+			    uint8_t msg_id, void *buf, size_t size)
+{
+	unsigned int offset, dev_cnt;
+	uint8_t *byte = buf;
+	union hdcp2_rx_info rx_info;
+	ssize_t ret, bytes_to_recv, len;
+
+	if (intel_dpcd_offset_for_hdcp2_msgid(msg_id, &offset) < 0)
+		return -EINVAL;
+
+	ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, msg_id);
+	if (ret < 0)
+		return ret;
+
+	/* Finding the ReceiverID List size */
+	if (msg_id == REP_SEND_RECVID_LIST) {
+		ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
+				DP_HDCP_2_2_REG_RXINFO_OFFSET, (void *)&rx_info,
+				sizeof(union hdcp2_rx_info));
+		if (ret != sizeof(union hdcp2_rx_info))
+			return ret >= 0 ? -EIO : ret;
+
+		dev_cnt = (rx_info.fields.device_count_hi << 4 |
+				rx_info.fields.device_count_lo);
+
+		if (dev_cnt > HDCP_MAX_DEVICE_COUNT)
+			dev_cnt = HDCP_MAX_DEVICE_COUNT;
+
+		size = sizeof(struct hdcp2_rep_send_receiverid_list) -
+				HDCP_RECEIVER_IDS_MAX_LEN +
+				(dev_cnt * HDCP_RECEIVER_ID_LEN);
+	}
+
+	bytes_to_recv = size - 1;
+
+	/* To skip the msg_id, as msgs in DP adaptation has no msg_id */
+	byte++;
+
+	while (bytes_to_recv) {
+		len = bytes_to_recv > DRM_HDCP_MAX_AUX_LEN ?
+				DRM_HDCP_MAX_AUX_LEN : bytes_to_recv;
+
+		ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
+				       (void *)byte, len);
+		if (ret < 0) {
+			DRM_DEBUG_KMS("msg_id %d, ret %d\n", msg_id, (int)ret);
+			return ret;
+		}
+
+		bytes_to_recv -= ret;
+		byte += ret;
+		offset += ret;
+	}
+	byte = buf;
+	*byte = msg_id;
+
+	return size;
+}
+
+static
+int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
+				      void *buf, size_t size)
+{
+	return intel_dp_hdcp2_write_msg(intel_dig_port, buf, size);
+}
+
+static
+int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
+{
+	union hdcp2_dp_rx_status rx_status;
+	int ret;
+
+	ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
+	if (ret)
+		return ret;
+
+	if (rx_status.fields.reauth_req)
+		ret = DRM_HDCP_REAUTH_REQUEST;
+	else if (rx_status.fields.Link_integrity_failure)
+		ret = DRM_HDCP_LINK_INTEGRITY_FAILURE;
+	else if (rx_status.fields.ready)
+		ret = DRM_HDCP_TOPOLOGY_CHANGE;
+
+	return ret;
+}
+
+static
+int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
+			   bool *capable)
+{
+	union hdcp2_rx_caps rx_caps;
+	int ret;
+
+	*capable = false;
+	ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
+			       DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
+			       &rx_caps, sizeof(rx_caps));
+	if (ret != sizeof(rx_caps))
+		return ret >= 0 ? -EIO : ret;
+
+	if (rx_caps.fields.version == HDCP_RXCAPS_VERSION_HDCP_2_2_VAL)
+		*capable = true;
+
+	return 0;
+}
+
+static
+enum hdcp_protocol intel_dp_hdcp2_protocol(void)
+{
+	return HDCP_PROTOCOL_DP;
+}
+
+static const struct intel_hdcp2_shim intel_dp_hdcp2_shim = {
+	.write_msg		= intel_dp_hdcp2_write_msg,
+	.read_msg		= intel_dp_hdcp2_read_msg,
+	.config_stream_type	= intel_dp_hdcp2_config_stream_type,
+	.check_link		= intel_dp_hdcp2_check_link,
+	.hdcp_capable		= intel_dp_hdcp2_capable,
+	.hdcp_protocol		= intel_dp_hdcp2_protocol,
+};
+
 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
-- 
2.7.4

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