* [PATCH v2 01/10] drm/i915/icl: Fix power well anonymous union initializers
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
@ 2018-08-06 9:58 ` Imre Deak
2018-08-06 9:58 ` [PATCH v2 02/10] drm/i915: Rename intel_power_domains_fini() to intel_power_domains_fini_hw() Imre Deak
` (11 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2018-08-06 9:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni
Similarly to commit 0a445945be6d
("drm/i915: Work around GCC anonymous union initialization bug")
we need to initialize anonymous unions inside extra braces to work
around a GCC4.4 build error.
v2:
- Fix checkpatch errors in commit log. (Paulo)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index cf89141b2281..11cb2a70e3fe 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2620,14 +2620,18 @@ static struct i915_power_well icl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_1,
- .hsw.has_fuses = true,
+ {
+ .hsw.has_fuses = true,
+ },
},
{
.name = "power well 2",
.domains = ICL_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_2,
- .hsw.has_fuses = true,
+ {
+ .hsw.has_fuses = true,
+ },
},
{
.name = "DC off",
@@ -2640,9 +2644,11 @@ static struct i915_power_well icl_power_wells[] = {
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
+ {
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
},
{
.name = "DDI A IO",
@@ -2745,8 +2751,10 @@ static struct i915_power_well icl_power_wells[] = {
.domains = ICL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
+ {
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ },
},
};
--
2.13.2
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 02/10] drm/i915: Rename intel_power_domains_fini() to intel_power_domains_fini_hw()
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
2018-08-06 9:58 ` [PATCH v2 01/10] drm/i915/icl: Fix power well anonymous union initializers Imre Deak
@ 2018-08-06 9:58 ` Imre Deak
2018-08-06 9:58 ` [PATCH v2 03/10] drm/i915/vlv: Remove redundant power well ID asserts Imre Deak
` (10 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2018-08-06 9:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni
intel_power_domains_fini() rolls back what was done in
intel_power_domains_init_hw(), so rename and move it accordingly. This
allows us adding a cleanup function later for intel_power_domains_init()
in a cleaner way.
No functional change.
v2:
- Fix checkpatch error adding missing param name to function
declaration. (Paulo)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 69 ++++++++++++++++-----------------
3 files changed, 37 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 64e0ea4bef67..e92f374521fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -712,7 +712,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_teardown_gmbus(dev_priv);
cleanup_csr:
intel_csr_ucode_fini(dev_priv);
- intel_power_domains_fini(dev_priv);
+ intel_power_domains_fini_hw(dev_priv);
vga_switcheroo_unregister_client(pdev);
cleanup_vga_client:
vga_client_register(pdev, NULL, NULL, NULL);
@@ -1462,7 +1462,7 @@ void i915_driver_unload(struct drm_device *dev)
i915_gem_fini(dev_priv);
intel_fbc_cleanup_cfb(dev_priv);
- intel_power_domains_fini(dev_priv);
+ intel_power_domains_fini_hw(dev_priv);
i915_driver_cleanup_hw(dev_priv);
i915_driver_cleanup_mmio(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1ad7c1124bef..3576ab5735b1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1948,8 +1948,8 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
/* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *);
-void intel_power_domains_fini(struct drm_i915_private *);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
+void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 11cb2a70e3fe..e82aa38bfd23 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2902,41 +2902,6 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
return 0;
}
-/**
- * intel_power_domains_fini - finalizes the power domain structures
- * @dev_priv: i915 device instance
- *
- * Finalizes the power domain structures for @dev_priv depending upon the
- * supported platform. This function also disables runtime pm and ensures that
- * the device stays powered up so that the driver can be reloaded.
- */
-void intel_power_domains_fini(struct drm_i915_private *dev_priv)
-{
- struct device *kdev = &dev_priv->drm.pdev->dev;
-
- /*
- * The i915.ko module is still not prepared to be loaded when
- * the power well is not enabled, so just enable it in case
- * we're going to unload/reload.
- * The following also reacquires the RPM reference the core passed
- * to the driver during loading, which is dropped in
- * intel_runtime_pm_enable(). We have to hand back the control of the
- * device to the core with this reference held.
- */
- intel_display_set_init_power(dev_priv, true);
-
- /* Remove the refcount we took to keep power well support disabled. */
- if (!i915_modparams.disable_power_well)
- intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
-
- /*
- * Remove the refcount we took in intel_runtime_pm_enable() in case
- * the platform doesn't support runtime PM.
- */
- if (!HAS_RUNTIME_PM(dev_priv))
- pm_runtime_put(kdev);
-}
-
static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
@@ -3577,6 +3542,40 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
}
/**
+ * intel_power_domains_fini_hw - deinitialize hw power domain state
+ * @dev_priv: i915 device instance
+ *
+ * De-initializes the display power domain HW state. It also ensures that the
+ * device stays powered up so that the driver can be reloaded.
+ */
+void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv)
+{
+ struct device *kdev = &dev_priv->drm.pdev->dev;
+
+ /*
+ * The i915.ko module is still not prepared to be loaded when
+ * the power well is not enabled, so just enable it in case
+ * we're going to unload/reload.
+ * The following also reacquires the RPM reference the core passed
+ * to the driver during loading, which is dropped in
+ * intel_runtime_pm_enable(). We have to hand back the control of the
+ * device to the core with this reference held.
+ */
+ intel_display_set_init_power(dev_priv, true);
+
+ /* Remove the refcount we took to keep power well support disabled. */
+ if (!i915_modparams.disable_power_well)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+
+ /*
+ * Remove the refcount we took in intel_runtime_pm_enable() in case
+ * the platform doesn't support runtime PM.
+ */
+ if (!HAS_RUNTIME_PM(dev_priv))
+ pm_runtime_put(kdev);
+}
+
+/**
* intel_power_domains_suspend - suspend power domain state
* @dev_priv: i915 device instance
*
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 03/10] drm/i915/vlv: Remove redundant power well ID asserts
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
2018-08-06 9:58 ` [PATCH v2 01/10] drm/i915/icl: Fix power well anonymous union initializers Imre Deak
2018-08-06 9:58 ` [PATCH v2 02/10] drm/i915: Rename intel_power_domains_fini() to intel_power_domains_fini_hw() Imre Deak
@ 2018-08-06 9:58 ` Imre Deak
2018-08-06 9:58 ` [PATCH v2 04/10] drm/i915: Constify power well descriptors Imre Deak
` (9 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2018-08-06 9:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni
The callbacks these asserts are called from are used from a single power
well, so not much point in checking that. The check also requires a unique
power well ID that we would need to keep around only for this purpose.
(A follow-up patch removes power well IDs not needed for direct power
well access).
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e82aa38bfd23..b2d182cc3319 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1045,8 +1045,6 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D);
-
vlv_set_power_well(dev_priv, power_well, true);
vlv_display_power_well_init(dev_priv);
@@ -1055,8 +1053,6 @@ static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D);
-
vlv_display_power_well_deinit(dev_priv);
vlv_set_power_well(dev_priv, power_well, false);
@@ -1065,8 +1061,6 @@ static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC);
-
/* since ref/cri clock was enabled */
udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
@@ -1091,8 +1085,6 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
{
enum pipe pipe;
- WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC);
-
for_each_pipe(dev_priv, pipe)
assert_pll_disabled(dev_priv, pipe);
@@ -1516,8 +1508,6 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
-
chv_set_pipe_power_well(dev_priv, power_well, true);
vlv_display_power_well_init(dev_priv);
@@ -1526,8 +1516,6 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A);
-
vlv_display_power_well_deinit(dev_priv);
chv_set_pipe_power_well(dev_priv, power_well, false);
--
2.13.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 04/10] drm/i915: Constify power well descriptors
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
` (2 preceding siblings ...)
2018-08-06 9:58 ` [PATCH v2 03/10] drm/i915/vlv: Remove redundant power well ID asserts Imre Deak
@ 2018-08-06 9:58 ` Imre Deak
2018-08-06 22:52 ` Paulo Zanoni
2018-08-06 9:58 ` [PATCH v2 05/10] drm/i915/vlv: Use power well CTL IDX instead of ID Imre Deak
` (8 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2018-08-06 9:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni
It makes sense to keep unchanging data const. Extract such fields from
the i915_power_well struct into a new i915_power_well_desc struct that
we initialize during compile time. For the rest of the dynamic
fields allocate an array of i915_power_well objects in i915 dev_priv,
and link to each of these objects their corresponding
i915_power_well_desc object.
v2:
- Fix checkpatch warnings about missing param name in fn declaration and
lines over 80 chars. (Paulo)
- Move check for unique IDs to __set_power_wells().
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 14 ++-
drivers/gpu/drm/i915/intel_display.h | 4 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdcp.c | 6 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 205 ++++++++++++++++++--------------
7 files changed, 140 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f9ce35da4123..23f38bc257a2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2845,10 +2845,10 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
enum intel_display_power_domain power_domain;
power_well = &power_domains->power_wells[i];
- seq_printf(m, "%-25s %d\n", power_well->name,
+ seq_printf(m, "%-25s %d\n", power_well->desc->name,
power_well->count);
- for_each_power_domain(power_domain, power_well->domains)
+ for_each_power_domain(power_domain, power_well->desc->domains)
seq_printf(m, " %-23s %d\n",
intel_display_power_domain_str(power_domain),
power_domains->domain_use_count[power_domain]);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e92f374521fc..e8df8180be35 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -924,7 +924,9 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
intel_uc_init_early(dev_priv);
intel_pm_setup(dev_priv);
intel_init_dpio(dev_priv);
- intel_power_domains_init(dev_priv);
+ ret = intel_power_domains_init(dev_priv);
+ if (ret < 0)
+ goto err_uc;
intel_irq_init(dev_priv);
intel_hangcheck_init(dev_priv);
intel_init_display_hooks(dev_priv);
@@ -936,6 +938,9 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
return 0;
+err_uc:
+ intel_uc_cleanup_early(dev_priv);
+ i915_gem_cleanup_early(dev_priv);
err_workqueues:
i915_workqueues_cleanup(dev_priv);
err_engines:
@@ -950,6 +955,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
{
intel_irq_fini(dev_priv);
+ intel_power_domains_cleanup(dev_priv);
intel_uc_cleanup_early(dev_priv);
i915_gem_cleanup_early(dev_priv);
i915_workqueues_cleanup(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4aca5344863d..85ad1909f5f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -868,13 +868,9 @@ struct i915_power_well_ops {
};
/* Power well structure for haswell */
-struct i915_power_well {
+struct i915_power_well_desc {
const char *name;
bool always_on;
- /* power well enable/disable usage count */
- int count;
- /* cached hw enabled state */
- bool hw_enabled;
u64 domains;
/* unique identifier for this power well */
enum i915_power_well_id id;
@@ -897,6 +893,14 @@ struct i915_power_well {
const struct i915_power_well_ops *ops;
};
+struct i915_power_well {
+ const struct i915_power_well_desc *desc;
+ /* power well enable/disable usage count */
+ int count;
+ /* cached hw enabled state */
+ bool hw_enabled;
+};
+
struct i915_power_domains {
/*
* Power wells needed for initialization at driver init and suspend
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 0a79a46d5805..6a28bac71128 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -329,11 +329,11 @@ struct intel_link_m_n {
#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
for_each_power_well(__dev_priv, __power_well) \
- for_each_if((__power_well)->domains & (__domain_mask))
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
for_each_power_well_rev(__dev_priv, __power_well) \
- for_each_if((__power_well)->domains & (__domain_mask))
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
for ((__i) = 0; \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3576ab5735b1..0601abb8c71f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1948,6 +1948,7 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
/* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *);
+void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 0cc6a861bcf8..26e48fc95543 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -57,9 +57,9 @@ static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
/* PG1 (power well #1) needs to be enabled */
for_each_power_well(dev_priv, power_well) {
- if (power_well->id == id) {
- enabled = power_well->ops->is_enabled(dev_priv,
- power_well);
+ if (power_well->desc->id == id) {
+ enabled = power_well->desc->ops->is_enabled(dev_priv,
+ power_well);
break;
}
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b2d182cc3319..a8916090a85e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -159,17 +159,17 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
static void intel_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- DRM_DEBUG_KMS("enabling %s\n", power_well->name);
- power_well->ops->enable(dev_priv, power_well);
+ DRM_DEBUG_KMS("enabling %s\n", power_well->desc->name);
+ power_well->desc->ops->enable(dev_priv, power_well);
power_well->hw_enabled = true;
}
static void intel_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- DRM_DEBUG_KMS("disabling %s\n", power_well->name);
+ DRM_DEBUG_KMS("disabling %s\n", power_well->desc->name);
power_well->hw_enabled = false;
- power_well->ops->disable(dev_priv, power_well);
+ power_well->desc->ops->disable(dev_priv, power_well);
}
static void intel_power_well_get(struct drm_i915_private *dev_priv,
@@ -183,7 +183,7 @@ static void intel_power_well_put(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
WARN(!power_well->count, "Use count on power well %s is already zero",
- power_well->name);
+ power_well->desc->name);
if (!--power_well->count)
intel_power_well_disable(dev_priv, power_well);
@@ -213,7 +213,7 @@ bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
is_enabled = true;
for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) {
- if (power_well->always_on)
+ if (power_well->desc->always_on)
continue;
if (!power_well->hw_enabled) {
@@ -323,7 +323,7 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->id;
+ enum i915_power_well_id id = power_well->desc->id;
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
WARN_ON(intel_wait_for_register(dev_priv,
@@ -350,7 +350,7 @@ static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->id;
+ enum i915_power_well_id id = power_well->desc->id;
bool disabled;
u32 reqs;
@@ -370,7 +370,7 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
return;
DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
- power_well->name,
+ power_well->desc->name,
!!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
}
@@ -386,8 +386,8 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->id;
- bool wait_fuses = power_well->hsw.has_fuses;
+ enum i915_power_well_id id = power_well->desc->id;
+ bool wait_fuses = power_well->desc->hsw.has_fuses;
enum skl_power_gate uninitialized_var(pg);
u32 val;
@@ -421,17 +421,19 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
if (wait_fuses)
gen9_wait_for_power_well_fuses(dev_priv, pg);
- hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
- power_well->hsw.has_vga);
+ hsw_power_well_post_enable(dev_priv,
+ power_well->desc->hsw.irq_pipe_mask,
+ power_well->desc->hsw.has_vga);
}
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->id;
+ enum i915_power_well_id id = power_well->desc->id;
u32 val;
- hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask);
+ hsw_power_well_pre_disable(dev_priv,
+ power_well->desc->hsw.irq_pipe_mask);
val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id),
@@ -445,7 +447,7 @@ static void
icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->id;
+ enum i915_power_well_id id = power_well->desc->id;
enum port port = ICL_AUX_PW_TO_PORT(id);
u32 val;
@@ -462,7 +464,7 @@ static void
icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->id;
+ enum i915_power_well_id id = power_well->desc->id;
enum port port = ICL_AUX_PW_TO_PORT(id);
u32 val;
@@ -484,7 +486,7 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->id;
+ enum i915_power_well_id id = power_well->desc->id;
u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id);
return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask;
@@ -723,7 +725,7 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv)
static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->id;
+ enum i915_power_well_id id = power_well->desc->id;
u32 mask = HSW_PWR_WELL_CTL_REQ(id);
u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id));
@@ -740,19 +742,19 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_ddi_phy_init(dev_priv, power_well->bxt.phy);
+ bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
}
static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy);
+ bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
}
static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy);
+ return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy);
}
static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
@@ -761,16 +763,17 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
if (power_well->count > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
+ bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
if (power_well->count > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
+ bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
if (IS_GEMINILAKE(dev_priv)) {
power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C);
if (power_well->count > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy);
+ bxt_ddi_phy_verify_state(dev_priv,
+ power_well->desc->bxt.phy);
}
}
@@ -869,7 +872,7 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
static void vlv_set_power_well(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well, bool enable)
{
- enum i915_power_well_id power_well_id = power_well->id;
+ enum i915_power_well_id power_well_id = power_well->desc->id;
u32 mask;
u32 state;
u32 ctrl;
@@ -917,7 +920,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id power_well_id = power_well->id;
+ enum i915_power_well_id power_well_id = power_well->desc->id;
bool enabled = false;
u32 mask;
u32 state;
@@ -1107,7 +1110,7 @@ lookup_power_well(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well;
power_well = &power_domains->power_wells[i];
- if (power_well->id == power_well_id)
+ if (power_well->desc->id == power_well_id)
return power_well;
}
@@ -1146,7 +1149,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
- if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
+ if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
phy_status |= PHY_POWERGOOD(DPIO_PHY0);
/* this assumes override is only used to enable lanes */
@@ -1187,7 +1190,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
}
- if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
+ if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
phy_status |= PHY_POWERGOOD(DPIO_PHY1);
/* this assumes override is only used to enable lanes */
@@ -1231,10 +1234,10 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
enum pipe pipe;
uint32_t tmp;
- WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
- power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
+ WARN_ON_ONCE(power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
+ power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_D);
- if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+ if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
pipe = PIPE_A;
phy = DPIO_PHY0;
} else {
@@ -1262,7 +1265,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
- if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+ if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
tmp |= DPIO_DYNPWRDOWNEN_CH1;
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
@@ -1293,10 +1296,10 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
{
enum dpio_phy phy;
- WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
- power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
+ WARN_ON_ONCE(power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
+ power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_D);
- if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+ if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
phy = DPIO_PHY0;
assert_pll_disabled(dev_priv, PIPE_A);
assert_pll_disabled(dev_priv, PIPE_B);
@@ -2051,7 +2054,7 @@ static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
.is_enabled = vlv_power_well_enabled,
};
-static struct i915_power_well i9xx_always_on_power_well[] = {
+static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
{
.name = "always-on",
.always_on = 1,
@@ -2068,7 +2071,7 @@ static const struct i915_power_well_ops i830_pipes_power_well_ops = {
.is_enabled = i830_pipes_power_well_enabled,
};
-static struct i915_power_well i830_power_wells[] = {
+static const struct i915_power_well_desc i830_power_wells[] = {
{
.name = "always-on",
.always_on = 1,
@@ -2105,7 +2108,7 @@ static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
.is_enabled = bxt_dpio_cmn_power_well_enabled,
};
-static struct i915_power_well hsw_power_wells[] = {
+static const struct i915_power_well_desc hsw_power_wells[] = {
{
.name = "always-on",
.always_on = 1,
@@ -2124,7 +2127,7 @@ static struct i915_power_well hsw_power_wells[] = {
},
};
-static struct i915_power_well bdw_power_wells[] = {
+static const struct i915_power_well_desc bdw_power_wells[] = {
{
.name = "always-on",
.always_on = 1,
@@ -2165,7 +2168,7 @@ static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
.is_enabled = vlv_power_well_enabled,
};
-static struct i915_power_well vlv_power_wells[] = {
+static const struct i915_power_well_desc vlv_power_wells[] = {
{
.name = "always-on",
.always_on = 1,
@@ -2223,7 +2226,7 @@ static struct i915_power_well vlv_power_wells[] = {
},
};
-static struct i915_power_well chv_power_wells[] = {
+static const struct i915_power_well_desc chv_power_wells[] = {
{
.name = "always-on",
.always_on = 1,
@@ -2263,12 +2266,12 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
bool ret;
power_well = lookup_power_well(dev_priv, power_well_id);
- ret = power_well->ops->is_enabled(dev_priv, power_well);
+ ret = power_well->desc->ops->is_enabled(dev_priv, power_well);
return ret;
}
-static struct i915_power_well skl_power_wells[] = {
+static const struct i915_power_well_desc skl_power_wells[] = {
{
.name = "always-on",
.always_on = 1,
@@ -2336,7 +2339,7 @@ static struct i915_power_well skl_power_wells[] = {
},
};
-static struct i915_power_well bxt_power_wells[] = {
+static const struct i915_power_well_desc bxt_power_wells[] = {
{
.name = "always-on",
.always_on = 1,
@@ -2390,7 +2393,7 @@ static struct i915_power_well bxt_power_wells[] = {
},
};
-static struct i915_power_well glk_power_wells[] = {
+static const struct i915_power_well_desc glk_power_wells[] = {
{
.name = "always-on",
.always_on = 1,
@@ -2490,7 +2493,7 @@ static struct i915_power_well glk_power_wells[] = {
},
};
-static struct i915_power_well cnl_power_wells[] = {
+static const struct i915_power_well_desc cnl_power_wells[] = {
{
.name = "always-on",
.always_on = 1,
@@ -2594,7 +2597,7 @@ static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = {
.is_enabled = hsw_power_well_enabled,
};
-static struct i915_power_well icl_power_wells[] = {
+static const struct i915_power_well_desc icl_power_wells[] = {
{
.name = "always-on",
.always_on = 1,
@@ -2805,26 +2808,37 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
return mask;
}
-static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv)
+static int
+__set_power_wells(struct i915_power_domains *power_domains,
+ const struct i915_power_well_desc *power_well_descs,
+ int power_well_count)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
- u64 power_well_ids;
+ u64 power_well_ids = 0;
int i;
- power_well_ids = 0;
- for (i = 0; i < power_domains->power_well_count; i++) {
- enum i915_power_well_id id = power_domains->power_wells[i].id;
+ power_domains->power_well_count = power_well_count;
+ power_domains->power_wells = kcalloc(power_well_count,
+ sizeof(*power_domains->power_wells),
+ GFP_KERNEL);
+ if (!power_domains->power_wells)
+ return -ENOMEM;
+
+ for (i = 0; i < power_well_count; i++) {
+ enum i915_power_well_id id = power_well_descs[i].id;
+
+ power_domains->power_wells[i].desc = &power_well_descs[i];
WARN_ON(id >= sizeof(power_well_ids) * 8);
WARN_ON(power_well_ids & BIT_ULL(id));
power_well_ids |= BIT_ULL(id);
}
+
+ return 0;
}
-#define set_power_wells(power_domains, __power_wells) ({ \
- (power_domains)->power_wells = (__power_wells); \
- (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
-})
+#define set_power_wells(power_domains, __power_well_descs) \
+ __set_power_wells(power_domains, __power_well_descs, \
+ ARRAY_SIZE(__power_well_descs))
/**
* intel_power_domains_init - initializes the power domain structures
@@ -2836,6 +2850,7 @@ static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv)
int intel_power_domains_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ int err;
i915_modparams.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
@@ -2852,15 +2867,15 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* the disabling order is reversed.
*/
if (IS_ICELAKE(dev_priv)) {
- set_power_wells(power_domains, icl_power_wells);
+ err = set_power_wells(power_domains, icl_power_wells);
} else if (IS_HASWELL(dev_priv)) {
- set_power_wells(power_domains, hsw_power_wells);
+ err = set_power_wells(power_domains, hsw_power_wells);
} else if (IS_BROADWELL(dev_priv)) {
- set_power_wells(power_domains, bdw_power_wells);
+ err = set_power_wells(power_domains, bdw_power_wells);
} else if (IS_GEN9_BC(dev_priv)) {
- set_power_wells(power_domains, skl_power_wells);
+ err = set_power_wells(power_domains, skl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
- set_power_wells(power_domains, cnl_power_wells);
+ err = set_power_wells(power_domains, cnl_power_wells);
/*
* DDI and Aux IO are getting enabled for all ports
@@ -2872,22 +2887,31 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
power_domains->power_well_count -= 2;
} else if (IS_BROXTON(dev_priv)) {
- set_power_wells(power_domains, bxt_power_wells);
+ err = set_power_wells(power_domains, bxt_power_wells);
} else if (IS_GEMINILAKE(dev_priv)) {
- set_power_wells(power_domains, glk_power_wells);
+ err = set_power_wells(power_domains, glk_power_wells);
} else if (IS_CHERRYVIEW(dev_priv)) {
- set_power_wells(power_domains, chv_power_wells);
+ err = set_power_wells(power_domains, chv_power_wells);
} else if (IS_VALLEYVIEW(dev_priv)) {
- set_power_wells(power_domains, vlv_power_wells);
+ err = set_power_wells(power_domains, vlv_power_wells);
} else if (IS_I830(dev_priv)) {
- set_power_wells(power_domains, i830_power_wells);
+ err = set_power_wells(power_domains, i830_power_wells);
} else {
- set_power_wells(power_domains, i9xx_always_on_power_well);
+ err = set_power_wells(power_domains, i9xx_always_on_power_well);
}
- assert_power_well_ids_unique(dev_priv);
+ return err;
+}
- return 0;
+/**
+ * intel_power_domains_cleanup - clean up power domains resources
+ * @dev_priv: i915 device instance
+ *
+ * Release any resources acquired by intel_power_domains_init()
+ */
+void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
+{
+ kfree(dev_priv->power_domains.power_wells);
}
static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
@@ -2897,9 +2921,9 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
mutex_lock(&power_domains->lock);
for_each_power_well(dev_priv, power_well) {
- power_well->ops->sync_hw(dev_priv, power_well);
- power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
- power_well);
+ power_well->desc->ops->sync_hw(dev_priv, power_well);
+ power_well->hw_enabled =
+ power_well->desc->ops->is_enabled(dev_priv, power_well);
}
mutex_unlock(&power_domains->lock);
}
@@ -3398,7 +3422,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
* override and set the lane powerdown bits accding to the
* current lane status.
*/
- if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
+ if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
uint32_t status = I915_READ(DPLL(PIPE_A));
unsigned int mask;
@@ -3429,7 +3453,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
dev_priv->chv_phy_assert[DPIO_PHY0] = true;
}
- if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
+ if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
uint32_t status = I915_READ(DPIO_PHY_STATUS);
unsigned int mask;
@@ -3465,15 +3489,15 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
/* If the display might be already active skip this */
- if (cmn->ops->is_enabled(dev_priv, cmn) &&
- disp2d->ops->is_enabled(dev_priv, disp2d) &&
+ if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&
+ disp2d->desc->ops->is_enabled(dev_priv, disp2d) &&
I915_READ(DPIO_CTL) & DPIO_CMNRST)
return;
DRM_DEBUG_KMS("toggling display PHY side reset\n");
/* cmnlane needs DPLL registers */
- disp2d->ops->enable(dev_priv, disp2d);
+ disp2d->desc->ops->enable(dev_priv, disp2d);
/*
* From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
@@ -3482,7 +3506,7 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
* Simply ungating isn't enough to reset the PHY enough to get
* ports and lanes running.
*/
- cmn->ops->disable(dev_priv, cmn);
+ cmn->desc->ops->disable(dev_priv, cmn);
}
/**
@@ -3598,9 +3622,9 @@ static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
enum intel_display_power_domain domain;
DRM_DEBUG_DRIVER("%-25s %d\n",
- power_well->name, power_well->count);
+ power_well->desc->name, power_well->count);
- for_each_power_domain(domain, power_well->domains)
+ for_each_power_domain(domain, power_well->desc->domains)
DRM_DEBUG_DRIVER(" %-23s %d\n",
intel_display_power_domain_str(domain),
power_domains->domain_use_count[domain]);
@@ -3636,22 +3660,25 @@ void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
* and PW1 power wells) are under FW control, so ignore them,
* since their state can change asynchronously.
*/
- if (!power_well->domains)
+ if (!power_well->desc->domains)
continue;
- enabled = power_well->ops->is_enabled(dev_priv, power_well);
- if ((power_well->count || power_well->always_on) != enabled)
+ enabled = power_well->desc->ops->is_enabled(dev_priv,
+ power_well);
+ if ((power_well->count || power_well->desc->always_on) !=
+ enabled)
DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)",
- power_well->name, power_well->count, enabled);
+ power_well->desc->name,
+ power_well->count, enabled);
domains_count = 0;
- for_each_power_domain(domain, power_well->domains)
+ for_each_power_domain(domain, power_well->desc->domains)
domains_count += power_domains->domain_use_count[domain];
if (power_well->count != domains_count) {
DRM_ERROR("power well %s refcount/domain refcount mismatch "
"(refcount %d/domains refcount %d)\n",
- power_well->name, power_well->count,
+ power_well->desc->name, power_well->count,
domains_count);
dump_domain_info = true;
}
--
2.13.2
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 04/10] drm/i915: Constify power well descriptors
2018-08-06 9:58 ` [PATCH v2 04/10] drm/i915: Constify power well descriptors Imre Deak
@ 2018-08-06 22:52 ` Paulo Zanoni
0 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-08-06 22:52 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: Jani Nikula
Em Seg, 2018-08-06 às 12:58 +0300, Imre Deak escreveu:
> It makes sense to keep unchanging data const. Extract such fields
> from
> the i915_power_well struct into a new i915_power_well_desc struct
> that
> we initialize during compile time. For the rest of the dynamic
> fields allocate an array of i915_power_well objects in i915 dev_priv,
> and link to each of these objects their corresponding
> i915_power_well_desc object.
>
> v2:
> - Fix checkpatch warnings about missing param name in fn declaration
> and
> lines over 80 chars. (Paulo)
> - Move check for unique IDs to __set_power_wells().
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
R-B still valid for v2 (or v3) as long as the kcalloc checkpatch issue
is fixed.
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.c | 8 +-
> drivers/gpu/drm/i915/i915_drv.h | 14 ++-
> drivers/gpu/drm/i915/intel_display.h | 4 +-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_hdcp.c | 6 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 205 ++++++++++++++++++--
> ------------
> 7 files changed, 140 insertions(+), 102 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index f9ce35da4123..23f38bc257a2 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2845,10 +2845,10 @@ static int i915_power_domain_info(struct
> seq_file *m, void *unused)
> enum intel_display_power_domain power_domain;
>
> power_well = &power_domains->power_wells[i];
> - seq_printf(m, "%-25s %d\n", power_well->name,
> + seq_printf(m, "%-25s %d\n", power_well->desc->name,
> power_well->count);
>
> - for_each_power_domain(power_domain, power_well-
> >domains)
> + for_each_power_domain(power_domain, power_well-
> >desc->domains)
> seq_printf(m, " %-23s %d\n",
> intel_display_power_domain_str(powe
> r_domain),
> power_domains-
> >domain_use_count[power_domain]);
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index e92f374521fc..e8df8180be35 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -924,7 +924,9 @@ static int i915_driver_init_early(struct
> drm_i915_private *dev_priv,
> intel_uc_init_early(dev_priv);
> intel_pm_setup(dev_priv);
> intel_init_dpio(dev_priv);
> - intel_power_domains_init(dev_priv);
> + ret = intel_power_domains_init(dev_priv);
> + if (ret < 0)
> + goto err_uc;
> intel_irq_init(dev_priv);
> intel_hangcheck_init(dev_priv);
> intel_init_display_hooks(dev_priv);
> @@ -936,6 +938,9 @@ static int i915_driver_init_early(struct
> drm_i915_private *dev_priv,
>
> return 0;
>
> +err_uc:
> + intel_uc_cleanup_early(dev_priv);
> + i915_gem_cleanup_early(dev_priv);
> err_workqueues:
> i915_workqueues_cleanup(dev_priv);
> err_engines:
> @@ -950,6 +955,7 @@ static int i915_driver_init_early(struct
> drm_i915_private *dev_priv,
> static void i915_driver_cleanup_early(struct drm_i915_private
> *dev_priv)
> {
> intel_irq_fini(dev_priv);
> + intel_power_domains_cleanup(dev_priv);
> intel_uc_cleanup_early(dev_priv);
> i915_gem_cleanup_early(dev_priv);
> i915_workqueues_cleanup(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 4aca5344863d..85ad1909f5f0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -868,13 +868,9 @@ struct i915_power_well_ops {
> };
>
> /* Power well structure for haswell */
> -struct i915_power_well {
> +struct i915_power_well_desc {
> const char *name;
> bool always_on;
> - /* power well enable/disable usage count */
> - int count;
> - /* cached hw enabled state */
> - bool hw_enabled;
> u64 domains;
> /* unique identifier for this power well */
> enum i915_power_well_id id;
> @@ -897,6 +893,14 @@ struct i915_power_well {
> const struct i915_power_well_ops *ops;
> };
>
> +struct i915_power_well {
> + const struct i915_power_well_desc *desc;
> + /* power well enable/disable usage count */
> + int count;
> + /* cached hw enabled state */
> + bool hw_enabled;
> +};
> +
> struct i915_power_domains {
> /*
> * Power wells needed for initialization at driver init and
> suspend
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index 0a79a46d5805..6a28bac71128 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -329,11 +329,11 @@ struct intel_link_m_n {
>
> #define for_each_power_domain_well(__dev_priv, __power_well,
> __domain_mask) \
> for_each_power_well(__dev_priv, __power_well)
> \
> - for_each_if((__power_well)->domains &
> (__domain_mask))
> + for_each_if((__power_well)->desc->domains &
> (__domain_mask))
>
> #define for_each_power_domain_well_rev(__dev_priv, __power_well,
> __domain_mask) \
> for_each_power_well_rev(__dev_priv, __power_well)
> \
> - for_each_if((__power_well)->domains &
> (__domain_mask))
> + for_each_if((__power_well)->desc->domains &
> (__domain_mask))
>
> #define for_each_new_intel_plane_in_state(__state, plane,
> new_plane_state, __i) \
> for ((__i) = 0; \
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 3576ab5735b1..0601abb8c71f 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1948,6 +1948,7 @@ int intel_psr_wait_for_idle(const struct
> intel_crtc_state *new_crtc_state);
>
> /* intel_runtime_pm.c */
> int intel_power_domains_init(struct drm_i915_private *);
> +void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
> void intel_power_domains_init_hw(struct drm_i915_private *dev_priv,
> bool resume);
> void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
> void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
> b/drivers/gpu/drm/i915/intel_hdcp.c
> index 0cc6a861bcf8..26e48fc95543 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -57,9 +57,9 @@ static bool hdcp_key_loadable(struct
> drm_i915_private *dev_priv)
>
> /* PG1 (power well #1) needs to be enabled */
> for_each_power_well(dev_priv, power_well) {
> - if (power_well->id == id) {
> - enabled = power_well->ops-
> >is_enabled(dev_priv,
> - power_
> well);
> + if (power_well->desc->id == id) {
> + enabled = power_well->desc->ops-
> >is_enabled(dev_priv,
> +
> power_well);
> break;
> }
> }
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b2d182cc3319..a8916090a85e 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -159,17 +159,17 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> static void intel_power_well_enable(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - DRM_DEBUG_KMS("enabling %s\n", power_well->name);
> - power_well->ops->enable(dev_priv, power_well);
> + DRM_DEBUG_KMS("enabling %s\n", power_well->desc->name);
> + power_well->desc->ops->enable(dev_priv, power_well);
> power_well->hw_enabled = true;
> }
>
> static void intel_power_well_disable(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - DRM_DEBUG_KMS("disabling %s\n", power_well->name);
> + DRM_DEBUG_KMS("disabling %s\n", power_well->desc->name);
> power_well->hw_enabled = false;
> - power_well->ops->disable(dev_priv, power_well);
> + power_well->desc->ops->disable(dev_priv, power_well);
> }
>
> static void intel_power_well_get(struct drm_i915_private *dev_priv,
> @@ -183,7 +183,7 @@ static void intel_power_well_put(struct
> drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> WARN(!power_well->count, "Use count on power well %s is
> already zero",
> - power_well->name);
> + power_well->desc->name);
>
> if (!--power_well->count)
> intel_power_well_disable(dev_priv, power_well);
> @@ -213,7 +213,7 @@ bool __intel_display_power_is_enabled(struct
> drm_i915_private *dev_priv,
> is_enabled = true;
>
> for_each_power_domain_well_rev(dev_priv, power_well,
> BIT_ULL(domain)) {
> - if (power_well->always_on)
> + if (power_well->desc->always_on)
> continue;
>
> if (!power_well->hw_enabled) {
> @@ -323,7 +323,7 @@ static void hsw_power_well_pre_disable(struct
> drm_i915_private *dev_priv,
> static void hsw_wait_for_power_well_enable(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - enum i915_power_well_id id = power_well->id;
> + enum i915_power_well_id id = power_well->desc->id;
>
> /* Timeout for PW1:10 us, AUX:not specified, other PWs:20
> us. */
> WARN_ON(intel_wait_for_register(dev_priv,
> @@ -350,7 +350,7 @@ static u32 hsw_power_well_requesters(struct
> drm_i915_private *dev_priv,
> static void hsw_wait_for_power_well_disable(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - enum i915_power_well_id id = power_well->id;
> + enum i915_power_well_id id = power_well->desc->id;
> bool disabled;
> u32 reqs;
>
> @@ -370,7 +370,7 @@ static void
> hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
> return;
>
> DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d
> debug:%d)\n",
> - power_well->name,
> + power_well->desc->name,
> !!(reqs & 1), !!(reqs & 2), !!(reqs & 4),
> !!(reqs & 8));
> }
>
> @@ -386,8 +386,8 @@ static void gen9_wait_for_power_well_fuses(struct
> drm_i915_private *dev_priv,
> static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - enum i915_power_well_id id = power_well->id;
> - bool wait_fuses = power_well->hsw.has_fuses;
> + enum i915_power_well_id id = power_well->desc->id;
> + bool wait_fuses = power_well->desc->hsw.has_fuses;
> enum skl_power_gate uninitialized_var(pg);
> u32 val;
>
> @@ -421,17 +421,19 @@ static void hsw_power_well_enable(struct
> drm_i915_private *dev_priv,
> if (wait_fuses)
> gen9_wait_for_power_well_fuses(dev_priv, pg);
>
> - hsw_power_well_post_enable(dev_priv, power_well-
> >hsw.irq_pipe_mask,
> - power_well->hsw.has_vga);
> + hsw_power_well_post_enable(dev_priv,
> + power_well->desc-
> >hsw.irq_pipe_mask,
> + power_well->desc->hsw.has_vga);
> }
>
> static void hsw_power_well_disable(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - enum i915_power_well_id id = power_well->id;
> + enum i915_power_well_id id = power_well->desc->id;
> u32 val;
>
> - hsw_power_well_pre_disable(dev_priv, power_well-
> >hsw.irq_pipe_mask);
> + hsw_power_well_pre_disable(dev_priv,
> + power_well->desc-
> >hsw.irq_pipe_mask);
>
> val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
> I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id),
> @@ -445,7 +447,7 @@ static void
> icl_combo_phy_aux_power_well_enable(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - enum i915_power_well_id id = power_well->id;
> + enum i915_power_well_id id = power_well->desc->id;
> enum port port = ICL_AUX_PW_TO_PORT(id);
> u32 val;
>
> @@ -462,7 +464,7 @@ static void
> icl_combo_phy_aux_power_well_disable(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - enum i915_power_well_id id = power_well->id;
> + enum i915_power_well_id id = power_well->desc->id;
> enum port port = ICL_AUX_PW_TO_PORT(id);
> u32 val;
>
> @@ -484,7 +486,7 @@ icl_combo_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
> static bool hsw_power_well_enabled(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - enum i915_power_well_id id = power_well->id;
> + enum i915_power_well_id id = power_well->desc->id;
> u32 mask = HSW_PWR_WELL_CTL_REQ(id) |
> HSW_PWR_WELL_CTL_STATE(id);
>
> return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) ==
> mask;
> @@ -723,7 +725,7 @@ static void skl_enable_dc6(struct
> drm_i915_private *dev_priv)
> static void hsw_power_well_sync_hw(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - enum i915_power_well_id id = power_well->id;
> + enum i915_power_well_id id = power_well->desc->id;
> u32 mask = HSW_PWR_WELL_CTL_REQ(id);
> u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id));
>
> @@ -740,19 +742,19 @@ static void hsw_power_well_sync_hw(struct
> drm_i915_private *dev_priv,
> static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - bxt_ddi_phy_init(dev_priv, power_well->bxt.phy);
> + bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
> }
>
> static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy);
> + bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
> }
>
> static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - return bxt_ddi_phy_is_enabled(dev_priv, power_well-
> >bxt.phy);
> + return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc-
> >bxt.phy);
> }
>
> static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private
> *dev_priv)
> @@ -761,16 +763,17 @@ static void
> bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
>
> power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
> if (power_well->count > 0)
> - bxt_ddi_phy_verify_state(dev_priv, power_well-
> >bxt.phy);
> + bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
> >bxt.phy);
>
> power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
> if (power_well->count > 0)
> - bxt_ddi_phy_verify_state(dev_priv, power_well-
> >bxt.phy);
> + bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
> >bxt.phy);
>
> if (IS_GEMINILAKE(dev_priv)) {
> power_well = lookup_power_well(dev_priv,
> GLK_DPIO_CMN_C);
> if (power_well->count > 0)
> - bxt_ddi_phy_verify_state(dev_priv,
> power_well->bxt.phy);
> + bxt_ddi_phy_verify_state(dev_priv,
> + power_well->desc-
> >bxt.phy);
> }
> }
>
> @@ -869,7 +872,7 @@ static void i830_pipes_power_well_sync_hw(struct
> drm_i915_private *dev_priv,
> static void vlv_set_power_well(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well,
> bool enable)
> {
> - enum i915_power_well_id power_well_id = power_well->id;
> + enum i915_power_well_id power_well_id = power_well->desc-
> >id;
> u32 mask;
> u32 state;
> u32 ctrl;
> @@ -917,7 +920,7 @@ static void vlv_power_well_disable(struct
> drm_i915_private *dev_priv,
> static bool vlv_power_well_enabled(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - enum i915_power_well_id power_well_id = power_well->id;
> + enum i915_power_well_id power_well_id = power_well->desc-
> >id;
> bool enabled = false;
> u32 mask;
> u32 state;
> @@ -1107,7 +1110,7 @@ lookup_power_well(struct drm_i915_private
> *dev_priv,
> struct i915_power_well *power_well;
>
> power_well = &power_domains->power_wells[i];
> - if (power_well->id == power_well_id)
> + if (power_well->desc->id == power_well_id)
> return power_well;
> }
>
> @@ -1146,7 +1149,7 @@ static void assert_chv_phy_status(struct
> drm_i915_private *dev_priv)
> PHY_STATUS_SPLINE_LDO(DPIO_PHY1
> , DPIO_CH0, 0) |
> PHY_STATUS_SPLINE_LDO(DPIO_PHY1
> , DPIO_CH0, 1));
>
> - if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
> + if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
> phy_status |= PHY_POWERGOOD(DPIO_PHY0);
>
> /* this assumes override is only used to enable
> lanes */
> @@ -1187,7 +1190,7 @@ static void assert_chv_phy_status(struct
> drm_i915_private *dev_priv)
> phy_status |=
> PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
> }
>
> - if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
> + if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
> phy_status |= PHY_POWERGOOD(DPIO_PHY1);
>
> /* this assumes override is only used to enable
> lanes */
> @@ -1231,10 +1234,10 @@ static void
> chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> enum pipe pipe;
> uint32_t tmp;
>
> - WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC
> &&
> - power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
> + WARN_ON_ONCE(power_well->desc->id !=
> PUNIT_POWER_WELL_DPIO_CMN_BC &&
> + power_well->desc->id !=
> PUNIT_POWER_WELL_DPIO_CMN_D);
>
> - if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> + if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> pipe = PIPE_A;
> phy = DPIO_PHY0;
> } else {
> @@ -1262,7 +1265,7 @@ static void
> chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
> vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
>
> - if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> + if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> tmp = vlv_dpio_read(dev_priv, pipe,
> _CHV_CMN_DW6_CH1);
> tmp |= DPIO_DYNPWRDOWNEN_CH1;
> vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1,
> tmp);
> @@ -1293,10 +1296,10 @@ static void
> chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
> {
> enum dpio_phy phy;
>
> - WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC
> &&
> - power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
> + WARN_ON_ONCE(power_well->desc->id !=
> PUNIT_POWER_WELL_DPIO_CMN_BC &&
> + power_well->desc->id !=
> PUNIT_POWER_WELL_DPIO_CMN_D);
>
> - if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> + if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> phy = DPIO_PHY0;
> assert_pll_disabled(dev_priv, PIPE_A);
> assert_pll_disabled(dev_priv, PIPE_B);
> @@ -2051,7 +2054,7 @@ static const struct i915_power_well_ops
> chv_dpio_cmn_power_well_ops = {
> .is_enabled = vlv_power_well_enabled,
> };
>
> -static struct i915_power_well i9xx_always_on_power_well[] = {
> +static const struct i915_power_well_desc i9xx_always_on_power_well[]
> = {
> {
> .name = "always-on",
> .always_on = 1,
> @@ -2068,7 +2071,7 @@ static const struct i915_power_well_ops
> i830_pipes_power_well_ops = {
> .is_enabled = i830_pipes_power_well_enabled,
> };
>
> -static struct i915_power_well i830_power_wells[] = {
> +static const struct i915_power_well_desc i830_power_wells[] = {
> {
> .name = "always-on",
> .always_on = 1,
> @@ -2105,7 +2108,7 @@ static const struct i915_power_well_ops
> bxt_dpio_cmn_power_well_ops = {
> .is_enabled = bxt_dpio_cmn_power_well_enabled,
> };
>
> -static struct i915_power_well hsw_power_wells[] = {
> +static const struct i915_power_well_desc hsw_power_wells[] = {
> {
> .name = "always-on",
> .always_on = 1,
> @@ -2124,7 +2127,7 @@ static struct i915_power_well hsw_power_wells[]
> = {
> },
> };
>
> -static struct i915_power_well bdw_power_wells[] = {
> +static const struct i915_power_well_desc bdw_power_wells[] = {
> {
> .name = "always-on",
> .always_on = 1,
> @@ -2165,7 +2168,7 @@ static const struct i915_power_well_ops
> vlv_dpio_power_well_ops = {
> .is_enabled = vlv_power_well_enabled,
> };
>
> -static struct i915_power_well vlv_power_wells[] = {
> +static const struct i915_power_well_desc vlv_power_wells[] = {
> {
> .name = "always-on",
> .always_on = 1,
> @@ -2223,7 +2226,7 @@ static struct i915_power_well vlv_power_wells[]
> = {
> },
> };
>
> -static struct i915_power_well chv_power_wells[] = {
> +static const struct i915_power_well_desc chv_power_wells[] = {
> {
> .name = "always-on",
> .always_on = 1,
> @@ -2263,12 +2266,12 @@ bool
> intel_display_power_well_is_enabled(struct drm_i915_private
> *dev_priv,
> bool ret;
>
> power_well = lookup_power_well(dev_priv, power_well_id);
> - ret = power_well->ops->is_enabled(dev_priv, power_well);
> + ret = power_well->desc->ops->is_enabled(dev_priv,
> power_well);
>
> return ret;
> }
>
> -static struct i915_power_well skl_power_wells[] = {
> +static const struct i915_power_well_desc skl_power_wells[] = {
> {
> .name = "always-on",
> .always_on = 1,
> @@ -2336,7 +2339,7 @@ static struct i915_power_well skl_power_wells[]
> = {
> },
> };
>
> -static struct i915_power_well bxt_power_wells[] = {
> +static const struct i915_power_well_desc bxt_power_wells[] = {
> {
> .name = "always-on",
> .always_on = 1,
> @@ -2390,7 +2393,7 @@ static struct i915_power_well bxt_power_wells[]
> = {
> },
> };
>
> -static struct i915_power_well glk_power_wells[] = {
> +static const struct i915_power_well_desc glk_power_wells[] = {
> {
> .name = "always-on",
> .always_on = 1,
> @@ -2490,7 +2493,7 @@ static struct i915_power_well glk_power_wells[]
> = {
> },
> };
>
> -static struct i915_power_well cnl_power_wells[] = {
> +static const struct i915_power_well_desc cnl_power_wells[] = {
> {
> .name = "always-on",
> .always_on = 1,
> @@ -2594,7 +2597,7 @@ static const struct i915_power_well_ops
> icl_combo_phy_aux_power_well_ops = {
> .is_enabled = hsw_power_well_enabled,
> };
>
> -static struct i915_power_well icl_power_wells[] = {
> +static const struct i915_power_well_desc icl_power_wells[] = {
> {
> .name = "always-on",
> .always_on = 1,
> @@ -2805,26 +2808,37 @@ static uint32_t get_allowed_dc_mask(const
> struct drm_i915_private *dev_priv,
> return mask;
> }
>
> -static void assert_power_well_ids_unique(struct drm_i915_private
> *dev_priv)
> +static int
> +__set_power_wells(struct i915_power_domains *power_domains,
> + const struct i915_power_well_desc
> *power_well_descs,
> + int power_well_count)
> {
> - struct i915_power_domains *power_domains = &dev_priv-
> >power_domains;
> - u64 power_well_ids;
> + u64 power_well_ids = 0;
> int i;
>
> - power_well_ids = 0;
> - for (i = 0; i < power_domains->power_well_count; i++) {
> - enum i915_power_well_id id = power_domains-
> >power_wells[i].id;
> + power_domains->power_well_count = power_well_count;
> + power_domains->power_wells = kcalloc(power_well_count,
> + sizeof(*power_domains-
> >power_wells),
> + GFP_KERNEL);
> + if (!power_domains->power_wells)
> + return -ENOMEM;
> +
> + for (i = 0; i < power_well_count; i++) {
> + enum i915_power_well_id id = power_well_descs[i].id;
> +
> + power_domains->power_wells[i].desc =
> &power_well_descs[i];
>
> WARN_ON(id >= sizeof(power_well_ids) * 8);
> WARN_ON(power_well_ids & BIT_ULL(id));
> power_well_ids |= BIT_ULL(id);
> }
> +
> + return 0;
> }
>
> -#define set_power_wells(power_domains, __power_wells) ({
> \
> - (power_domains)->power_wells = (__power_wells);
> \
> - (power_domains)->power_well_count =
> ARRAY_SIZE(__power_wells); \
> -})
> +#define set_power_wells(power_domains, __power_well_descs) \
> + __set_power_wells(power_domains, __power_well_descs, \
> + ARRAY_SIZE(__power_well_descs))
>
> /**
> * intel_power_domains_init - initializes the power domain
> structures
> @@ -2836,6 +2850,7 @@ static void assert_power_well_ids_unique(struct
> drm_i915_private *dev_priv)
> int intel_power_domains_init(struct drm_i915_private *dev_priv)
> {
> struct i915_power_domains *power_domains = &dev_priv-
> >power_domains;
> + int err;
>
> i915_modparams.disable_power_well =
> sanitize_disable_power_well_option(dev_priv,
> @@ -2852,15 +2867,15 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
> * the disabling order is reversed.
> */
> if (IS_ICELAKE(dev_priv)) {
> - set_power_wells(power_domains, icl_power_wells);
> + err = set_power_wells(power_domains,
> icl_power_wells);
> } else if (IS_HASWELL(dev_priv)) {
> - set_power_wells(power_domains, hsw_power_wells);
> + err = set_power_wells(power_domains,
> hsw_power_wells);
> } else if (IS_BROADWELL(dev_priv)) {
> - set_power_wells(power_domains, bdw_power_wells);
> + err = set_power_wells(power_domains,
> bdw_power_wells);
> } else if (IS_GEN9_BC(dev_priv)) {
> - set_power_wells(power_domains, skl_power_wells);
> + err = set_power_wells(power_domains,
> skl_power_wells);
> } else if (IS_CANNONLAKE(dev_priv)) {
> - set_power_wells(power_domains, cnl_power_wells);
> + err = set_power_wells(power_domains,
> cnl_power_wells);
>
> /*
> * DDI and Aux IO are getting enabled for all ports
> @@ -2872,22 +2887,31 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
> power_domains->power_well_count -= 2;
>
> } else if (IS_BROXTON(dev_priv)) {
> - set_power_wells(power_domains, bxt_power_wells);
> + err = set_power_wells(power_domains,
> bxt_power_wells);
> } else if (IS_GEMINILAKE(dev_priv)) {
> - set_power_wells(power_domains, glk_power_wells);
> + err = set_power_wells(power_domains,
> glk_power_wells);
> } else if (IS_CHERRYVIEW(dev_priv)) {
> - set_power_wells(power_domains, chv_power_wells);
> + err = set_power_wells(power_domains,
> chv_power_wells);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> - set_power_wells(power_domains, vlv_power_wells);
> + err = set_power_wells(power_domains,
> vlv_power_wells);
> } else if (IS_I830(dev_priv)) {
> - set_power_wells(power_domains, i830_power_wells);
> + err = set_power_wells(power_domains,
> i830_power_wells);
> } else {
> - set_power_wells(power_domains,
> i9xx_always_on_power_well);
> + err = set_power_wells(power_domains,
> i9xx_always_on_power_well);
> }
>
> - assert_power_well_ids_unique(dev_priv);
> + return err;
> +}
>
> - return 0;
> +/**
> + * intel_power_domains_cleanup - clean up power domains resources
> + * @dev_priv: i915 device instance
> + *
> + * Release any resources acquired by intel_power_domains_init()
> + */
> +void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
> +{
> + kfree(dev_priv->power_domains.power_wells);
> }
>
> static void intel_power_domains_sync_hw(struct drm_i915_private
> *dev_priv)
> @@ -2897,9 +2921,9 @@ static void intel_power_domains_sync_hw(struct
> drm_i915_private *dev_priv)
>
> mutex_lock(&power_domains->lock);
> for_each_power_well(dev_priv, power_well) {
> - power_well->ops->sync_hw(dev_priv, power_well);
> - power_well->hw_enabled = power_well->ops-
> >is_enabled(dev_priv,
> -
> power_well);
> + power_well->desc->ops->sync_hw(dev_priv,
> power_well);
> + power_well->hw_enabled =
> + power_well->desc->ops->is_enabled(dev_priv,
> power_well);
> }
> mutex_unlock(&power_domains->lock);
> }
> @@ -3398,7 +3422,7 @@ static void chv_phy_control_init(struct
> drm_i915_private *dev_priv)
> * override and set the lane powerdown bits accding to the
> * current lane status.
> */
> - if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
> + if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
> uint32_t status = I915_READ(DPLL(PIPE_A));
> unsigned int mask;
>
> @@ -3429,7 +3453,7 @@ static void chv_phy_control_init(struct
> drm_i915_private *dev_priv)
> dev_priv->chv_phy_assert[DPIO_PHY0] = true;
> }
>
> - if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
> + if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
> uint32_t status = I915_READ(DPIO_PHY_STATUS);
> unsigned int mask;
>
> @@ -3465,15 +3489,15 @@ static void vlv_cmnlane_wa(struct
> drm_i915_private *dev_priv)
> lookup_power_well(dev_priv,
> PUNIT_POWER_WELL_DISP2D);
>
> /* If the display might be already active skip this */
> - if (cmn->ops->is_enabled(dev_priv, cmn) &&
> - disp2d->ops->is_enabled(dev_priv, disp2d) &&
> + if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&
> + disp2d->desc->ops->is_enabled(dev_priv, disp2d) &&
> I915_READ(DPIO_CTL) & DPIO_CMNRST)
> return;
>
> DRM_DEBUG_KMS("toggling display PHY side reset\n");
>
> /* cmnlane needs DPLL registers */
> - disp2d->ops->enable(dev_priv, disp2d);
> + disp2d->desc->ops->enable(dev_priv, disp2d);
>
> /*
> * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
> @@ -3482,7 +3506,7 @@ static void vlv_cmnlane_wa(struct
> drm_i915_private *dev_priv)
> * Simply ungating isn't enough to reset the PHY enough to
> get
> * ports and lanes running.
> */
> - cmn->ops->disable(dev_priv, cmn);
> + cmn->desc->ops->disable(dev_priv, cmn);
> }
>
> /**
> @@ -3598,9 +3622,9 @@ static void
> intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
> enum intel_display_power_domain domain;
>
> DRM_DEBUG_DRIVER("%-25s %d\n",
> - power_well->name, power_well-
> >count);
> + power_well->desc->name, power_well-
> >count);
>
> - for_each_power_domain(domain, power_well->domains)
> + for_each_power_domain(domain, power_well->desc-
> >domains)
> DRM_DEBUG_DRIVER(" %-23s %d\n",
> intel_display_power_domain_
> str(domain),
> power_domains-
> >domain_use_count[domain]);
> @@ -3636,22 +3660,25 @@ void intel_power_domains_verify_state(struct
> drm_i915_private *dev_priv)
> * and PW1 power wells) are under FW control, so
> ignore them,
> * since their state can change asynchronously.
> */
> - if (!power_well->domains)
> + if (!power_well->desc->domains)
> continue;
>
> - enabled = power_well->ops->is_enabled(dev_priv,
> power_well);
> - if ((power_well->count || power_well->always_on) !=
> enabled)
> + enabled = power_well->desc->ops-
> >is_enabled(dev_priv,
> + power_we
> ll);
> + if ((power_well->count || power_well->desc-
> >always_on) !=
> + enabled)
> DRM_ERROR("power well %s state mismatch
> (refcount %d/enabled %d)",
> - power_well->name, power_well-
> >count, enabled);
> + power_well->desc->name,
> + power_well->count, enabled);
>
> domains_count = 0;
> - for_each_power_domain(domain, power_well->domains)
> + for_each_power_domain(domain, power_well->desc-
> >domains)
> domains_count += power_domains-
> >domain_use_count[domain];
>
> if (power_well->count != domains_count) {
> DRM_ERROR("power well %s refcount/domain
> refcount mismatch "
> "(refcount %d/domains refcount
> %d)\n",
> - power_well->name, power_well-
> >count,
> + power_well->desc->name,
> power_well->count,
> domains_count);
> dump_domain_info = true;
> }
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 05/10] drm/i915/vlv: Use power well CTL IDX instead of ID
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
` (3 preceding siblings ...)
2018-08-06 9:58 ` [PATCH v2 04/10] drm/i915: Constify power well descriptors Imre Deak
@ 2018-08-06 9:58 ` Imre Deak
2018-08-06 9:58 ` [PATCH v2 06/10] drm/i915/ddi: " Imre Deak
` (7 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2018-08-06 9:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni
Atm, we determine the control/status flag offsets within the PUNIT
control/status registers based on the power well's ID. Since the power
well ID enum is global across all platforms, the associated macros to
get the flag offsets involves some magic. This makes checking the
register/bit definitions against the specification more difficult than
necessary. Also the values in the power well ID enum must stay fixed,
making code maintenance of the enum cumbersome.
To solve the above define the control/status flag indices right after
the corresponding registers and use these to derive the control/status
flag values by storing the indices in the i915_power_well_desc struct.
Initializing anonymous union fields require the preceding field in the
struct to be explicitly initialized - even when using named
initializers - and the initialization to be done right before the union
initialization, hence the reordering of the .id fields.
v2:
- Clarify commit log message about anonymous union initializers. (Paulo)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++++
drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++----
drivers/gpu/drm/i915/intel_runtime_pm.c | 52 ++++++++++++++++++++++++---------
3 files changed, 62 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 85ad1909f5f0..be82f1dc001d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -880,6 +880,13 @@ struct i915_power_well_desc {
*/
union {
struct {
+ /*
+ * request/status flag index in the PUNIT power well
+ * control/status registers.
+ */
+ u8 idx;
+ } vlv;
+ struct {
enum dpio_phy phy;
} bxt;
struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b656f31fde9..ed30b4f8b948 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1144,11 +1144,23 @@ enum i915_power_well_id {
#define PUNIT_REG_PWRGT_CTRL 0x60
#define PUNIT_REG_PWRGT_STATUS 0x61
-#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
-#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
-#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
-#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
-#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
+#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
+#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
+
+#define PUNIT_PWGT_IDX_RENDER 0
+#define PUNIT_PWGT_IDX_MEDIA 1
+#define PUNIT_PWGT_IDX_DISP2D 3
+#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
+#define PUNIT_PWGT_IDX_DPIO_RX0 10
+#define PUNIT_PWGT_IDX_DPIO_RX1 11
+#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
#define PUNIT_REG_GPU_LFM 0xd3
#define PUNIT_REG_GPU_FREQ_REQ 0xd4
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a8916090a85e..1cb14d1a8a53 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -872,14 +872,14 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
static void vlv_set_power_well(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well, bool enable)
{
- enum i915_power_well_id power_well_id = power_well->desc->id;
+ int pw_idx = power_well->desc->vlv.idx;
u32 mask;
u32 state;
u32 ctrl;
- mask = PUNIT_PWRGT_MASK(power_well_id);
- state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
- PUNIT_PWRGT_PWR_GATE(power_well_id);
+ mask = PUNIT_PWRGT_MASK(pw_idx);
+ state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
+ PUNIT_PWRGT_PWR_GATE(pw_idx);
mutex_lock(&dev_priv->pcu_lock);
@@ -920,14 +920,14 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id power_well_id = power_well->desc->id;
+ int pw_idx = power_well->desc->vlv.idx;
bool enabled = false;
u32 mask;
u32 state;
u32 ctrl;
- mask = PUNIT_PWRGT_MASK(power_well_id);
- ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
+ mask = PUNIT_PWRGT_MASK(pw_idx);
+ ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
mutex_lock(&dev_priv->pcu_lock);
@@ -936,8 +936,8 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
* We only ever set the power-on and power-gate states, anything
* else is unexpected.
*/
- WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
- state != PUNIT_PWRGT_PWR_GATE(power_well_id));
+ WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
+ state != PUNIT_PWRGT_PWR_GATE(pw_idx));
if (state == ctrl)
enabled = true;
@@ -2179,8 +2179,11 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
{
.name = "display",
.domains = VLV_DISPLAY_POWER_DOMAINS,
- .id = PUNIT_POWER_WELL_DISP2D,
.ops = &vlv_display_power_well_ops,
+ .id = PUNIT_POWER_WELL_DISP2D,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
+ },
},
{
.name = "dpio-tx-b-01",
@@ -2190,6 +2193,9 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
.id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
+ },
},
{
.name = "dpio-tx-b-23",
@@ -2199,6 +2205,9 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
.id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
+ },
},
{
.name = "dpio-tx-c-01",
@@ -2208,6 +2217,9 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
.id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
+ },
},
{
.name = "dpio-tx-c-23",
@@ -2217,12 +2229,18 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
.id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
+ },
},
{
.name = "dpio-common",
.domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
- .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
.ops = &vlv_dpio_cmn_power_well_ops,
+ .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
+ },
},
};
@@ -2242,20 +2260,26 @@ static const struct i915_power_well_desc chv_power_wells[] = {
* required for any pipe to work.
*/
.domains = CHV_DISPLAY_POWER_DOMAINS,
- .id = CHV_DISP_PW_PIPE_A,
.ops = &chv_pipe_power_well_ops,
+ .id = CHV_DISP_PW_PIPE_A,
},
{
.name = "dpio-common-bc",
.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
- .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
.ops = &chv_dpio_cmn_power_well_ops,
+ .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
+ },
},
{
.name = "dpio-common-d",
.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
+ .ops = &chv_dpio_cmn_power_well_ops,
.id = PUNIT_POWER_WELL_DPIO_CMN_D,
- .ops = &chv_dpio_cmn_power_well_ops,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
+ },
},
};
--
2.13.2
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 06/10] drm/i915/ddi: Use power well CTL IDX instead of ID
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
` (4 preceding siblings ...)
2018-08-06 9:58 ` [PATCH v2 05/10] drm/i915/vlv: Use power well CTL IDX instead of ID Imre Deak
@ 2018-08-06 9:58 ` Imre Deak
2018-08-06 9:58 ` [PATCH v2 07/10] drm/i915: Remove redundant power well IDs Imre Deak
` (6 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2018-08-06 9:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni
Similarly to the previous patch use a separate request/status HW flag
index defined right after the corresponding control registers instead of
depending for this on the power well IDs. Since the set of
control/status registers varies among the different power wells (on a
single platform), also add a new i915_power_well_registers struct that
we populate and assign to each DDI power well as needed.
Also clarify a bit the code comment describing the function and layout
of the control registers.
This also fixes a problem on ICL, where we incorrectly read the KVMR
control register in hsw_power_well_requesters() even for DDI and AUX
power wells.
v2:
- Clarify platform range tags in code comments. (Paulo)
- Fix line over 80 chars checkpatch warning.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/gvt/handlers.c | 31 ++--
drivers/gpu/drm/i915/i915_drv.h | 13 ++
drivers/gpu/drm/i915/i915_reg.h | 126 ++++++++-----
drivers/gpu/drm/i915/intel_display.c | 5 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 302 ++++++++++++++++++++++++++------
5 files changed, 360 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 7a58ca555197..ead7f61d29b1 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1287,12 +1287,13 @@ static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
{
write_vreg(vgpu, offset, p_data, bytes);
- if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL))
+ if (vgpu_vreg(vgpu, offset) &
+ HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
vgpu_vreg(vgpu, offset) |=
- HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
+ HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
else
vgpu_vreg(vgpu, offset) &=
- ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
+ ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
return 0;
}
@@ -2443,17 +2444,10 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
MMIO_D(GEN6_PMINTRMSK, D_ALL);
- /*
- * Use an arbitrary power well controlled by the PWR_WELL_CTL
- * register.
- */
- MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
- power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
- power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write);
- MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
- power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
+ MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
@@ -2804,13 +2798,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
dp_aux_ch_ctl_mmio_write);
- /*
- * Use an arbitrary power well controlled by the PWR_WELL_CTL
- * register.
- */
- MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
- MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
- skl_power_well_ctl_write);
+ MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
+ MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
MMIO_D(_MMIO(0xa210), D_SKL_PLUS);
MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be82f1dc001d..b237fd55d2b3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -867,6 +867,13 @@ struct i915_power_well_ops {
struct i915_power_well *power_well);
};
+struct i915_power_well_regs {
+ i915_reg_t bios;
+ i915_reg_t driver;
+ i915_reg_t kvmr;
+ i915_reg_t debug;
+};
+
/* Power well structure for haswell */
struct i915_power_well_desc {
const char *name;
@@ -890,6 +897,12 @@ struct i915_power_well_desc {
enum dpio_phy phy;
} bxt;
struct {
+ const struct i915_power_well_regs *regs;
+ /*
+ * request/status flag index in the power well
+ * constrol/status registers.
+ */
+ u8 idx;
/* Mask of pipes whose IRQ logic is backed by the pw */
u8 irq_pipe_mask;
/* The pw is backing the VGA functionality */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ed30b4f8b948..4f5eb49934b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8925,46 +8925,78 @@ enum {
#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
-/* HSW Power Wells */
-#define _HSW_PWR_WELL_CTL1 0x45400
-#define _HSW_PWR_WELL_CTL2 0x45404
-#define _HSW_PWR_WELL_CTL3 0x45408
-#define _HSW_PWR_WELL_CTL4 0x4540C
-
-#define _ICL_PWR_WELL_CTL_AUX1 0x45440
-#define _ICL_PWR_WELL_CTL_AUX2 0x45444
-#define _ICL_PWR_WELL_CTL_AUX4 0x4544C
-
-#define _ICL_PWR_WELL_CTL_DDI1 0x45450
-#define _ICL_PWR_WELL_CTL_DDI2 0x45454
-#define _ICL_PWR_WELL_CTL_DDI4 0x4545C
-
/*
- * Each power well control register contains up to 16 (request, status) HW
- * flag tuples. The register index and HW flag shift is determined by the
- * power well ID (see i915_power_well_id). There are 4 possible sources of
- * power well requests each source having its own set of control registers:
- * BIOS, DRIVER, KVMR, DEBUG.
+ * HSW - ICL power wells
+ *
+ * Platforms have up to 3 power well control register sets, each set
+ * controlling up to 16 power wells via a request/status HW flag tuple:
+ * - main (HSW_PWR_WELL_CTL[1-4])
+ * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
+ * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
+ * Each control register set consists of up to 4 registers used by different
+ * sources that can request a power well to be enabled:
+ * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
+ * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
+ * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
+ * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
*/
-#define _HSW_PW_REG_IDX(pw) ((pw) >> 4)
-#define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2)
-#define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
- _HSW_PWR_WELL_CTL1, \
- _ICL_PWR_WELL_CTL_AUX1, \
- _ICL_PWR_WELL_CTL_DDI1))
-#define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
- _HSW_PWR_WELL_CTL2, \
- _ICL_PWR_WELL_CTL_AUX2, \
- _ICL_PWR_WELL_CTL_DDI2))
-/* KVMR doesn't have a reg for AUX or DDI power well control */
-#define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3)
-#define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
- _HSW_PWR_WELL_CTL4, \
- _ICL_PWR_WELL_CTL_AUX4, \
- _ICL_PWR_WELL_CTL_DDI4))
+#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
+#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
+#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
+#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
+#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
+#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
-#define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1))
-#define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw))
+/* HSW/BDW power well */
+#define HSW_PW_CTL_IDX_GLOBAL 15
+
+/* SKL/BXT/GLK/CNL power wells */
+#define SKL_PW_CTL_IDX_PW_2 15
+#define SKL_PW_CTL_IDX_PW_1 14
+#define CNL_PW_CTL_IDX_AUX_F 12
+#define CNL_PW_CTL_IDX_AUX_D 11
+#define GLK_PW_CTL_IDX_AUX_C 10
+#define GLK_PW_CTL_IDX_AUX_B 9
+#define GLK_PW_CTL_IDX_AUX_A 8
+#define CNL_PW_CTL_IDX_DDI_F 6
+#define SKL_PW_CTL_IDX_DDI_D 4
+#define SKL_PW_CTL_IDX_DDI_C 3
+#define SKL_PW_CTL_IDX_DDI_B 2
+#define SKL_PW_CTL_IDX_DDI_A_E 1
+#define GLK_PW_CTL_IDX_DDI_A 1
+#define SKL_PW_CTL_IDX_MISC_IO 0
+
+/* ICL - power wells */
+#define ICL_PW_CTL_IDX_PW_4 3
+#define ICL_PW_CTL_IDX_PW_3 2
+#define ICL_PW_CTL_IDX_PW_2 1
+#define ICL_PW_CTL_IDX_PW_1 0
+
+#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
+#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
+#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
+#define ICL_PW_CTL_IDX_AUX_TBT4 11
+#define ICL_PW_CTL_IDX_AUX_TBT3 10
+#define ICL_PW_CTL_IDX_AUX_TBT2 9
+#define ICL_PW_CTL_IDX_AUX_TBT1 8
+#define ICL_PW_CTL_IDX_AUX_F 5
+#define ICL_PW_CTL_IDX_AUX_E 4
+#define ICL_PW_CTL_IDX_AUX_D 3
+#define ICL_PW_CTL_IDX_AUX_C 2
+#define ICL_PW_CTL_IDX_AUX_B 1
+#define ICL_PW_CTL_IDX_AUX_A 0
+
+#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
+#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
+#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
+#define ICL_PW_CTL_IDX_DDI_F 5
+#define ICL_PW_CTL_IDX_DDI_E 4
+#define ICL_PW_CTL_IDX_DDI_D 3
+#define ICL_PW_CTL_IDX_DDI_C 2
+#define ICL_PW_CTL_IDX_DDI_B 1
+#define ICL_PW_CTL_IDX_DDI_A 0
+
+/* HSW - power well misc debug registers */
#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
@@ -8980,18 +9012,26 @@ enum skl_power_gate {
#define SKL_FUSE_STATUS _MMIO(0x42000)
#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
-/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
-#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
-/* PG0 (HW control->no power well ID), PG1..PG4 (ICL_DISP_PW1..ICL_DISP_PW4) */
-#define ICL_PW_TO_PG(pw) ((pw) - ICL_DISP_PW_1 + SKL_PG1)
+/*
+ * PG0 is HW controlled, so doesn't have a corresponding power well control knob
+ * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
+ */
+#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
+ ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
+/*
+ * PG0 is HW controlled, so doesn't have a corresponding power well control knob
+ * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
+ */
+#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
+ ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
-#define _CNL_AUX_REG_IDX(pw) ((pw) - 9)
+#define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
#define _CNL_AUX_ANAOVRD1_B 0x162250
#define _CNL_AUX_ANAOVRD1_C 0x162210
#define _CNL_AUX_ANAOVRD1_D 0x1622D0
#define _CNL_AUX_ANAOVRD1_F 0x162A90
-#define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
+#define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
_CNL_AUX_ANAOVRD1_B, \
_CNL_AUX_ANAOVRD1_C, \
_CNL_AUX_ANAOVRD1_D, \
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 73c6d56ba3ec..53e7a7e75384 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8973,7 +8973,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
pipe_name(crtc->pipe));
- I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
+ I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
"Display power well on\n");
I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
@@ -16129,8 +16129,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
return NULL;
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- error->power_well_driver =
- I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
+ error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
for_each_pipe(dev_priv, i) {
error->pipe[i].power_domain_on =
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1cb14d1a8a53..626774f86cd2 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -323,26 +323,29 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->desc->id;
+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ int pw_idx = power_well->desc->hsw.idx;
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
WARN_ON(intel_wait_for_register(dev_priv,
- HSW_PWR_WELL_CTL_DRIVER(id),
- HSW_PWR_WELL_CTL_STATE(id),
- HSW_PWR_WELL_CTL_STATE(id),
+ regs->driver,
+ HSW_PWR_WELL_CTL_STATE(pw_idx),
+ HSW_PWR_WELL_CTL_STATE(pw_idx),
1));
}
static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
- enum i915_power_well_id id)
+ const struct i915_power_well_regs *regs,
+ int pw_idx)
{
- u32 req_mask = HSW_PWR_WELL_CTL_REQ(id);
+ u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
u32 ret;
- ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0;
- ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0;
- ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0;
- ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0;
+ ret = I915_READ(regs->bios) & req_mask ? 1 : 0;
+ ret |= I915_READ(regs->driver) & req_mask ? 2 : 0;
+ if (regs->kvmr.reg)
+ ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0;
+ ret |= I915_READ(regs->debug) & req_mask ? 8 : 0;
return ret;
}
@@ -350,7 +353,8 @@ static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->desc->id;
+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ int pw_idx = power_well->desc->hsw.idx;
bool disabled;
u32 reqs;
@@ -363,9 +367,9 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
* Skip the wait in case any of the request bits are set and print a
* diagnostic message.
*/
- wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) &
- HSW_PWR_WELL_CTL_STATE(id))) ||
- (reqs = hsw_power_well_requesters(dev_priv, id)), 1);
+ wait_for((disabled = !(I915_READ(regs->driver) &
+ HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
+ (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
if (disabled)
return;
@@ -386,14 +390,15 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->desc->id;
+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ int pw_idx = power_well->desc->hsw.idx;
bool wait_fuses = power_well->desc->hsw.has_fuses;
enum skl_power_gate uninitialized_var(pg);
u32 val;
if (wait_fuses) {
- pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_TO_PG(id) :
- SKL_PW_TO_PG(id);
+ pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
+ SKL_PW_CTL_IDX_TO_PG(pw_idx);
/*
* For PW1 we have to wait both for the PW0/PG0 fuse state
* before enabling the power well and PW1/PG1's own fuse
@@ -405,17 +410,17 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
}
- val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
- I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));
+ val = I915_READ(regs->driver);
+ I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
hsw_wait_for_power_well_enable(dev_priv, power_well);
/* Display WA #1178: cnl */
if (IS_CANNONLAKE(dev_priv) &&
- (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C ||
- id == CNL_DISP_PW_AUX_D || id == CNL_DISP_PW_AUX_F)) {
- val = I915_READ(CNL_AUX_ANAOVRD1(id));
+ pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
+ pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
+ val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx));
val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
- I915_WRITE(CNL_AUX_ANAOVRD1(id), val);
+ I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val);
}
if (wait_fuses)
@@ -429,30 +434,31 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->desc->id;
+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ int pw_idx = power_well->desc->hsw.idx;
u32 val;
hsw_power_well_pre_disable(dev_priv,
power_well->desc->hsw.irq_pipe_mask);
- val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
- I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id),
- val & ~HSW_PWR_WELL_CTL_REQ(id));
+ val = I915_READ(regs->driver);
+ I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
hsw_wait_for_power_well_disable(dev_priv, power_well);
}
-#define ICL_AUX_PW_TO_PORT(pw) ((pw) - ICL_DISP_PW_AUX_A)
+#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
static void
icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->desc->id;
- enum port port = ICL_AUX_PW_TO_PORT(id);
+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
u32 val;
- val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
- I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));
+ val = I915_READ(regs->driver);
+ I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
val = I915_READ(ICL_PORT_CL_DW12(port));
I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
@@ -464,16 +470,16 @@ static void
icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->desc->id;
- enum port port = ICL_AUX_PW_TO_PORT(id);
+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
u32 val;
val = I915_READ(ICL_PORT_CL_DW12(port));
I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
- val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
- I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id),
- val & ~HSW_PWR_WELL_CTL_REQ(id));
+ val = I915_READ(regs->driver);
+ I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
hsw_wait_for_power_well_disable(dev_priv, power_well);
}
@@ -486,22 +492,22 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->desc->id;
- u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id);
+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
+ HSW_PWR_WELL_CTL_STATE(pw_idx);
- return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask;
+ return (I915_READ(regs->driver) & mask) == mask;
}
static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
{
- enum i915_power_well_id id = SKL_DISP_PW_2;
-
WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
"DC9 already programmed to be enabled.\n");
WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
"DC5 still not disabled to enable DC9.\n");
- WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) &
- HSW_PWR_WELL_CTL_REQ(id),
+ WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL2) &
+ HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
"Power well 2 on.\n");
WARN_ONCE(intel_irqs_enabled(dev_priv),
"Interrupts not disabled yet.\n");
@@ -725,17 +731,18 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv)
static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- enum i915_power_well_id id = power_well->desc->id;
- u32 mask = HSW_PWR_WELL_CTL_REQ(id);
- u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id));
+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
+ u32 bios_req = I915_READ(regs->bios);
/* Take over the request bit if set by BIOS. */
if (bios_req & mask) {
- u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
+ u32 drv_req = I915_READ(regs->driver);
if (!(drv_req & mask))
- I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask);
- I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask);
+ I915_WRITE(regs->driver, drv_req | mask);
+ I915_WRITE(regs->bios, bios_req & ~mask);
}
}
@@ -2108,6 +2115,13 @@ static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
.is_enabled = bxt_dpio_cmn_power_well_enabled,
};
+static const struct i915_power_well_regs hsw_power_well_regs = {
+ .bios = HSW_PWR_WELL_CTL1,
+ .driver = HSW_PWR_WELL_CTL2,
+ .kvmr = HSW_PWR_WELL_CTL3,
+ .debug = HSW_PWR_WELL_CTL4,
+};
+
static const struct i915_power_well_desc hsw_power_wells[] = {
{
.name = "always-on",
@@ -2122,6 +2136,8 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
.hsw.has_vga = true,
},
},
@@ -2141,6 +2157,8 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
},
@@ -2310,6 +2328,8 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
},
@@ -2319,6 +2339,10 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_MISC_IO,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
+ },
},
{
.name = "DC off",
@@ -2332,6 +2356,8 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
@@ -2342,24 +2368,40 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_A_E,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
+ },
},
{
.name = "DDI B IO power well",
.domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_B,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
+ },
},
{
.name = "DDI C IO power well",
.domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_C,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
+ },
},
{
.name = "DDI D IO power well",
.domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_D,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
+ },
},
};
@@ -2377,6 +2419,8 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
},
@@ -2392,6 +2436,8 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
@@ -2432,6 +2478,8 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
},
@@ -2447,6 +2495,8 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
@@ -2484,36 +2534,60 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_AUX_A,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
+ },
},
{
.name = "AUX B",
.domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_AUX_B,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
+ },
},
{
.name = "AUX C",
.domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_AUX_C,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
+ },
},
{
.name = "DDI A IO power well",
.domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = GLK_DISP_PW_DDI_A,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
+ },
},
{
.name = "DDI B IO power well",
.domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_B,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
+ },
},
{
.name = "DDI C IO power well",
.domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_C,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
+ },
},
};
@@ -2532,6 +2606,8 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
},
@@ -2540,24 +2616,40 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_A,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
+ },
},
{
.name = "AUX B",
.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_B,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
+ },
},
{
.name = "AUX C",
.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_C,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
+ },
},
{
.name = "AUX D",
.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_D,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = CNL_PW_CTL_IDX_AUX_D,
+ },
},
{
.name = "DC off",
@@ -2571,6 +2663,8 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
@@ -2581,36 +2675,60 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_DDI_A,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
+ },
},
{
.name = "DDI B IO power well",
.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_B,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
+ },
},
{
.name = "DDI C IO power well",
.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_C,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
+ },
},
{
.name = "DDI D IO power well",
.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_DDI_D,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
+ },
},
{
.name = "DDI F IO power well",
.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_DDI_F,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = CNL_PW_CTL_IDX_DDI_F,
+ },
},
{
.name = "AUX F",
.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = CNL_DISP_PW_AUX_F,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = CNL_PW_CTL_IDX_AUX_F,
+ },
},
};
@@ -2621,6 +2739,18 @@ static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = {
.is_enabled = hsw_power_well_enabled,
};
+static const struct i915_power_well_regs icl_aux_power_well_regs = {
+ .bios = ICL_PWR_WELL_CTL_AUX1,
+ .driver = ICL_PWR_WELL_CTL_AUX2,
+ .debug = ICL_PWR_WELL_CTL_AUX4,
+};
+
+static const struct i915_power_well_regs icl_ddi_power_well_regs = {
+ .bios = ICL_PWR_WELL_CTL_DDI1,
+ .driver = ICL_PWR_WELL_CTL_DDI2,
+ .debug = ICL_PWR_WELL_CTL_DDI4,
+};
+
static const struct i915_power_well_desc icl_power_wells[] = {
{
.name = "always-on",
@@ -2636,6 +2766,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_1,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
.hsw.has_fuses = true,
},
},
@@ -2645,6 +2777,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_2,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
.hsw.has_fuses = true,
},
},
@@ -2660,6 +2794,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_3,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
.hsw.irq_pipe_mask = BIT(PIPE_B),
.hsw.has_vga = true,
.hsw.has_fuses = true,
@@ -2670,96 +2806,160 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_DDI_A,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ },
},
{
.name = "DDI B IO",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_DDI_B,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ },
},
{
.name = "DDI C IO",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_DDI_C,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+ },
},
{
.name = "DDI D IO",
.domains = ICL_DDI_IO_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_DDI_D,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
+ },
},
{
.name = "DDI E IO",
.domains = ICL_DDI_IO_E_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_DDI_E,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
+ },
},
{
.name = "DDI F IO",
.domains = ICL_DDI_IO_F_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_DDI_F,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
+ },
},
{
.name = "AUX A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_combo_phy_aux_power_well_ops,
.id = ICL_DISP_PW_AUX_A,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
},
{
.name = "AUX B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_combo_phy_aux_power_well_ops,
.id = ICL_DISP_PW_AUX_B,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
},
{
.name = "AUX C",
.domains = ICL_AUX_C_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_AUX_C,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ },
},
{
.name = "AUX D",
.domains = ICL_AUX_D_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_AUX_D,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
+ },
},
{
.name = "AUX E",
.domains = ICL_AUX_E_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_AUX_E,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
+ },
},
{
.name = "AUX F",
.domains = ICL_AUX_F_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_AUX_F,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
+ },
},
{
.name = "AUX TBT1",
.domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_AUX_TBT1,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
+ },
},
{
.name = "AUX TBT2",
.domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_AUX_TBT2,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
+ },
},
{
.name = "AUX TBT3",
.domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_AUX_TBT3,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
+ },
},
{
.name = "AUX TBT4",
.domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_AUX_TBT4,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
+ },
},
{
.name = "power well 4",
@@ -2767,6 +2967,8 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &hsw_power_well_ops,
.id = ICL_DISP_PW_4,
{
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
.hsw.has_fuses = true,
.hsw.irq_pipe_mask = BIT(PIPE_C),
},
--
2.13.2
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 07/10] drm/i915: Remove redundant power well IDs
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
` (5 preceding siblings ...)
2018-08-06 9:58 ` [PATCH v2 06/10] drm/i915/ddi: " Imre Deak
@ 2018-08-06 9:58 ` Imre Deak
2018-08-06 23:02 ` Paulo Zanoni
2018-08-06 9:58 ` [PATCH v2 08/10] drm/i915: Make power well ID names more uniform Imre Deak
` (5 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2018-08-06 9:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni
Now that we removed dependence on the power well IDs to determine the
control register and request/status flag offsets the only purpose of
power well IDs is to look up power wells directly bypassing the power
domains framework. However this direct lookup isn't needed for most of
the exisiting power wells and hopefully won't be needed for any new
power wells in the future. To make maintenance of the power well ID enum
easier, don't require a unique ID for each power well, only if it's
necessary. Remove the IDs becoming redundant this way and assign to all
the corresponding power wells a new DISP_PW_ID_NONE ID.
After the previous two patches the IDs don't need to have a fixed value,
so remove the explicit initializers and adjust the enum's code comment
accordingly.
v2:
- Keep required ID assignments for HSW_DISP_PW_GLOBAL and ICL_DISP_PW_2.
(Paulo)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 118 ++++--------------------------
drivers/gpu/drm/i915/intel_runtime_pm.c | 123 ++++++++++++++++----------------
2 files changed, 76 insertions(+), 165 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4f5eb49934b4..4568adc8369a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,117 +1029,25 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
/*
* i915_power_well_id:
*
- * Platform specific IDs used to look up power wells and - except for custom
- * power wells - to define request/status register flag bit positions. As such
- * the set of IDs on a given platform must be unique and except for custom
- * power wells their value must stay fixed.
+ * IDs used to look up power wells. Power wells accessed directly bypassing
+ * the power domains framework must be assigned a unique ID. The rest of power
+ * wells must be assigned DISP_PW_ID_NONE.
*/
enum i915_power_well_id {
- /*
- * I830
- * - custom power well
- */
- I830_DISP_PW_PIPES = 0,
-
- /*
- * VLV/CHV
- * - PUNIT_REG_PWRGT_CTRL (bit: id*2),
- * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
- */
- PUNIT_POWER_WELL_RENDER = 0,
- PUNIT_POWER_WELL_MEDIA = 1,
- PUNIT_POWER_WELL_DISP2D = 3,
- PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
- PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
- PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
- PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
- PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
- PUNIT_POWER_WELL_DPIO_RX0 = 10,
- PUNIT_POWER_WELL_DPIO_RX1 = 11,
- PUNIT_POWER_WELL_DPIO_CMN_D = 12,
- /* - custom power well */
- CHV_DISP_PW_PIPE_A, /* 13 */
-
- /*
- * HSW/BDW
- * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1)
- */
- HSW_DISP_PW_GLOBAL = 15,
-
- /*
- * GEN9+
- * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1)
- */
- SKL_DISP_PW_MISC_IO = 0,
- SKL_DISP_PW_DDI_A_E,
- GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
- CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
- SKL_DISP_PW_DDI_B,
- SKL_DISP_PW_DDI_C,
- SKL_DISP_PW_DDI_D,
- CNL_DISP_PW_DDI_F = 6,
-
- GLK_DISP_PW_AUX_A = 8,
- GLK_DISP_PW_AUX_B,
- GLK_DISP_PW_AUX_C,
- CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
- CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
- CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
- CNL_DISP_PW_AUX_D,
- CNL_DISP_PW_AUX_F,
-
- SKL_DISP_PW_1 = 14,
+ DISP_PW_ID_NONE,
+
+ PUNIT_POWER_WELL_DISP2D,
+ PUNIT_POWER_WELL_DPIO_CMN_BC,
+ PUNIT_POWER_WELL_DPIO_CMN_D,
+ HSW_DISP_PW_GLOBAL,
+ SKL_DISP_PW_MISC_IO,
+ SKL_DISP_PW_1,
SKL_DISP_PW_2,
-
- /* - custom power wells */
BXT_DPIO_CMN_A,
BXT_DPIO_CMN_BC,
- GLK_DPIO_CMN_C, /* 18 */
-
- /*
- * GEN11+
- * - _HSW_PWR_WELL_CTL1-4
- * (status bit: (id&15)*2, req bit:(id&15)*2+1)
- */
- ICL_DISP_PW_1 = 0,
+ GLK_DPIO_CMN_C,
+ ICL_DISP_PW_1,
ICL_DISP_PW_2,
- ICL_DISP_PW_3,
- ICL_DISP_PW_4,
-
- /*
- * - _HSW_PWR_WELL_CTL_AUX1/2/4
- * (status bit: (id&15)*2, req bit:(id&15)*2+1)
- */
- ICL_DISP_PW_AUX_A = 16,
- ICL_DISP_PW_AUX_B,
- ICL_DISP_PW_AUX_C,
- ICL_DISP_PW_AUX_D,
- ICL_DISP_PW_AUX_E,
- ICL_DISP_PW_AUX_F,
-
- ICL_DISP_PW_AUX_TBT1 = 24,
- ICL_DISP_PW_AUX_TBT2,
- ICL_DISP_PW_AUX_TBT3,
- ICL_DISP_PW_AUX_TBT4,
-
- /*
- * - _HSW_PWR_WELL_CTL_DDI1/2/4
- * (status bit: (id&15)*2, req bit:(id&15)*2+1)
- */
- ICL_DISP_PW_DDI_A = 32,
- ICL_DISP_PW_DDI_B,
- ICL_DISP_PW_DDI_C,
- ICL_DISP_PW_DDI_D,
- ICL_DISP_PW_DDI_E,
- ICL_DISP_PW_DDI_F, /* 37 */
-
- /*
- * Multiple platforms.
- * Must start following the highest ID of any platform.
- * - custom power wells
- */
- SKL_DISP_PW_DC_OFF = 38,
- I915_DISP_PW_ALWAYS_ON,
};
#define PUNIT_REG_PWRGT_CTRL 0x60
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 626774f86cd2..6aec980cea07 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2067,7 +2067,7 @@ static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
};
@@ -2084,13 +2084,13 @@ static const struct i915_power_well_desc i830_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "pipes",
.domains = I830_PIPES_POWER_DOMAINS,
.ops = &i830_pipes_power_well_ops,
- .id = I830_DISP_PW_PIPES,
+ .id = DISP_PW_ID_NONE,
},
};
@@ -2128,7 +2128,7 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "display",
@@ -2149,7 +2149,7 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "display",
@@ -2192,7 +2192,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "display",
@@ -2210,7 +2210,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
+ .id = DISP_PW_ID_NONE,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
},
@@ -2222,7 +2222,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
+ .id = DISP_PW_ID_NONE,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
},
@@ -2234,7 +2234,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
+ .id = DISP_PW_ID_NONE,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
},
@@ -2246,7 +2246,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
+ .id = DISP_PW_ID_NONE,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
},
@@ -2268,7 +2268,7 @@ static const struct i915_power_well_desc chv_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "display",
@@ -2279,7 +2279,7 @@ static const struct i915_power_well_desc chv_power_wells[] = {
*/
.domains = CHV_DISPLAY_POWER_DOMAINS,
.ops = &chv_pipe_power_well_ops,
- .id = CHV_DISP_PW_PIPE_A,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "dpio-common-bc",
@@ -2319,7 +2319,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 1",
@@ -2348,7 +2348,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.name = "DC off",
.domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 2",
@@ -2367,7 +2367,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.name = "DDI A/E IO power well",
.domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_A_E,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
@@ -2377,7 +2377,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.name = "DDI B IO power well",
.domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
@@ -2387,7 +2387,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.name = "DDI C IO power well",
.domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
@@ -2397,7 +2397,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.name = "DDI D IO power well",
.domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_D,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_D,
@@ -2411,7 +2411,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 1",
@@ -2428,7 +2428,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.name = "DC off",
.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 2",
@@ -2469,7 +2469,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 1",
@@ -2487,7 +2487,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "DC off",
.domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 2",
@@ -2533,7 +2533,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "AUX A",
.domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = GLK_DISP_PW_AUX_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_A,
@@ -2543,7 +2543,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "AUX B",
.domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = GLK_DISP_PW_AUX_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_B,
@@ -2553,7 +2553,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "AUX C",
.domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = GLK_DISP_PW_AUX_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_C,
@@ -2563,7 +2563,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "DDI A IO power well",
.domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = GLK_DISP_PW_DDI_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_DDI_A,
@@ -2573,7 +2573,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "DDI B IO power well",
.domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
@@ -2583,7 +2583,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "DDI C IO power well",
.domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
@@ -2597,7 +2597,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 1",
@@ -2615,7 +2615,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "AUX A",
.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_A,
@@ -2625,7 +2625,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "AUX B",
.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_B,
@@ -2635,7 +2635,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "AUX C",
.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_AUX_C,
@@ -2645,7 +2645,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "AUX D",
.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_D,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = CNL_PW_CTL_IDX_AUX_D,
@@ -2655,7 +2655,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "DC off",
.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 2",
@@ -2674,7 +2674,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "DDI A IO power well",
.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_DDI_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = GLK_PW_CTL_IDX_DDI_A,
@@ -2684,7 +2684,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "DDI B IO power well",
.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
@@ -2694,7 +2694,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "DDI C IO power well",
.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
@@ -2704,7 +2704,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "DDI D IO power well",
.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_DDI_D,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = SKL_PW_CTL_IDX_DDI_D,
@@ -2714,7 +2714,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "DDI F IO power well",
.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_DDI_F,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = CNL_PW_CTL_IDX_DDI_F,
@@ -2724,7 +2724,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "AUX F",
.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = CNL_DISP_PW_AUX_F,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = CNL_PW_CTL_IDX_AUX_F,
@@ -2757,7 +2757,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.always_on = 1,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
- .id = I915_DISP_PW_ALWAYS_ON,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 1",
@@ -2786,13 +2786,13 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "DC off",
.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_PW_DC_OFF,
+ .id = DISP_PW_ID_NONE,
},
{
.name = "power well 3",
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_3,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
@@ -2805,7 +2805,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "DDI A IO",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
@@ -2815,7 +2815,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "DDI B IO",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
@@ -2825,7 +2825,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "DDI C IO",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
@@ -2835,7 +2835,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "DDI D IO",
.domains = ICL_DDI_IO_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_D,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_D,
@@ -2845,7 +2845,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "DDI E IO",
.domains = ICL_DDI_IO_E_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_E,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_E,
@@ -2855,7 +2855,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "DDI F IO",
.domains = ICL_DDI_IO_F_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_DDI_F,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_ddi_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_DDI_F,
@@ -2865,7 +2865,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_combo_phy_aux_power_well_ops,
- .id = ICL_DISP_PW_AUX_A,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
@@ -2875,7 +2875,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_combo_phy_aux_power_well_ops,
- .id = ICL_DISP_PW_AUX_B,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
@@ -2885,7 +2885,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX C",
.domains = ICL_AUX_C_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_C,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
@@ -2895,7 +2895,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX D",
.domains = ICL_AUX_D_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_D,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_D,
@@ -2905,7 +2905,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX E",
.domains = ICL_AUX_E_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_E,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_E,
@@ -2915,7 +2915,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX F",
.domains = ICL_AUX_F_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_F,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_F,
@@ -2925,7 +2925,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX TBT1",
.domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_TBT1,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
@@ -2935,7 +2935,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX TBT2",
.domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_TBT2,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
@@ -2945,7 +2945,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX TBT3",
.domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_TBT3,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
@@ -2955,7 +2955,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX TBT4",
.domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_AUX_TBT4,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
@@ -2965,7 +2965,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "power well 4",
.domains = ICL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_4,
+ .id = DISP_PW_ID_NONE,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
@@ -3054,6 +3054,9 @@ __set_power_wells(struct i915_power_domains *power_domains,
power_domains->power_wells[i].desc = &power_well_descs[i];
+ if (id == DISP_PW_ID_NONE)
+ continue;
+
WARN_ON(id >= sizeof(power_well_ids) * 8);
WARN_ON(power_well_ids & BIT_ULL(id));
power_well_ids |= BIT_ULL(id);
--
2.13.2
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 07/10] drm/i915: Remove redundant power well IDs
2018-08-06 9:58 ` [PATCH v2 07/10] drm/i915: Remove redundant power well IDs Imre Deak
@ 2018-08-06 23:02 ` Paulo Zanoni
0 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-08-06 23:02 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: Jani Nikula
Em Seg, 2018-08-06 às 12:58 +0300, Imre Deak escreveu:
> Now that we removed dependence on the power well IDs to determine the
> control register and request/status flag offsets the only purpose of
> power well IDs is to look up power wells directly bypassing the power
> domains framework. However this direct lookup isn't needed for most
> of
> the exisiting power wells and hopefully won't be needed for any new
> power wells in the future. To make maintenance of the power well ID
> enum
> easier, don't require a unique ID for each power well, only if it's
> necessary. Remove the IDs becoming redundant this way and assign to
> all
> the corresponding power wells a new DISP_PW_ID_NONE ID.
>
> After the previous two patches the IDs don't need to have a fixed
> value,
> so remove the explicit initializers and adjust the enum's code
> comment
> accordingly.
>
> v2:
> - Keep required ID assignments for HSW_DISP_PW_GLOBAL and
> ICL_DISP_PW_2.
> (Paulo)
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 118 ++++----------------
> ----------
> drivers/gpu/drm/i915/intel_runtime_pm.c | 123 ++++++++++++++++----
> ------------
> 2 files changed, 76 insertions(+), 165 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 4f5eb49934b4..4568adc8369a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1029,117 +1029,25 @@ static inline bool
> i915_mmio_reg_valid(i915_reg_t reg)
> /*
> * i915_power_well_id:
> *
> - * Platform specific IDs used to look up power wells and - except
> for custom
> - * power wells - to define request/status register flag bit
> positions. As such
> - * the set of IDs on a given platform must be unique and except for
> custom
> - * power wells their value must stay fixed.
> + * IDs used to look up power wells. Power wells accessed directly
> bypassing
> + * the power domains framework must be assigned a unique ID. The
> rest of power
> + * wells must be assigned DISP_PW_ID_NONE.
> */
> enum i915_power_well_id {
> - /*
> - * I830
> - * - custom power well
> - */
> - I830_DISP_PW_PIPES = 0,
> -
> - /*
> - * VLV/CHV
> - * - PUNIT_REG_PWRGT_CTRL (bit: id*2),
> - * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
> - */
> - PUNIT_POWER_WELL_RENDER = 0,
> - PUNIT_POWER_WELL_MEDIA = 1,
> - PUNIT_POWER_WELL_DISP2D = 3,
> - PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
> - PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
> - PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
> - PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
> - PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
> - PUNIT_POWER_WELL_DPIO_RX0 = 10,
> - PUNIT_POWER_WELL_DPIO_RX1 = 11,
> - PUNIT_POWER_WELL_DPIO_CMN_D = 12,
> - /* - custom power well */
> - CHV_DISP_PW_PIPE_A, /* 13 */
> -
> - /*
> - * HSW/BDW
> - * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit:
> id*2+1)
> - */
> - HSW_DISP_PW_GLOBAL = 15,
> -
> - /*
> - * GEN9+
> - * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit:
> id*2+1)
> - */
> - SKL_DISP_PW_MISC_IO = 0,
> - SKL_DISP_PW_DDI_A_E,
> - GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> - CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> - SKL_DISP_PW_DDI_B,
> - SKL_DISP_PW_DDI_C,
> - SKL_DISP_PW_DDI_D,
> - CNL_DISP_PW_DDI_F = 6,
> -
> - GLK_DISP_PW_AUX_A = 8,
> - GLK_DISP_PW_AUX_B,
> - GLK_DISP_PW_AUX_C,
> - CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
> - CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
> - CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
> - CNL_DISP_PW_AUX_D,
> - CNL_DISP_PW_AUX_F,
> -
> - SKL_DISP_PW_1 = 14,
> + DISP_PW_ID_NONE,
> +
> + PUNIT_POWER_WELL_DISP2D,
> + PUNIT_POWER_WELL_DPIO_CMN_BC,
> + PUNIT_POWER_WELL_DPIO_CMN_D,
> + HSW_DISP_PW_GLOBAL,
> + SKL_DISP_PW_MISC_IO,
> + SKL_DISP_PW_1,
> SKL_DISP_PW_2,
> -
> - /* - custom power wells */
> BXT_DPIO_CMN_A,
> BXT_DPIO_CMN_BC,
> - GLK_DPIO_CMN_C, /* 18 */
> -
> - /*
> - * GEN11+
> - * - _HSW_PWR_WELL_CTL1-4
> - * (status bit: (id&15)*2, req bit:(id&15)*2+1)
> - */
> - ICL_DISP_PW_1 = 0,
> + GLK_DPIO_CMN_C,
> + ICL_DISP_PW_1,
> ICL_DISP_PW_2,
> - ICL_DISP_PW_3,
> - ICL_DISP_PW_4,
> -
> - /*
> - * - _HSW_PWR_WELL_CTL_AUX1/2/4
> - * (status bit: (id&15)*2, req bit:(id&15)*2+1)
> - */
> - ICL_DISP_PW_AUX_A = 16,
> - ICL_DISP_PW_AUX_B,
> - ICL_DISP_PW_AUX_C,
> - ICL_DISP_PW_AUX_D,
> - ICL_DISP_PW_AUX_E,
> - ICL_DISP_PW_AUX_F,
> -
> - ICL_DISP_PW_AUX_TBT1 = 24,
> - ICL_DISP_PW_AUX_TBT2,
> - ICL_DISP_PW_AUX_TBT3,
> - ICL_DISP_PW_AUX_TBT4,
> -
> - /*
> - * - _HSW_PWR_WELL_CTL_DDI1/2/4
> - * (status bit: (id&15)*2, req bit:(id&15)*2+1)
> - */
> - ICL_DISP_PW_DDI_A = 32,
> - ICL_DISP_PW_DDI_B,
> - ICL_DISP_PW_DDI_C,
> - ICL_DISP_PW_DDI_D,
> - ICL_DISP_PW_DDI_E,
> - ICL_DISP_PW_DDI_F, /* 37 */
> -
> - /*
> - * Multiple platforms.
> - * Must start following the highest ID of any platform.
> - * - custom power wells
> - */
> - SKL_DISP_PW_DC_OFF = 38,
> - I915_DISP_PW_ALWAYS_ON,
> };
>
> #define PUNIT_REG_PWRGT_CTRL 0x60
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 626774f86cd2..6aec980cea07 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2067,7 +2067,7 @@ static const struct i915_power_well_desc
> i9xx_always_on_power_well[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> + .id = DISP_PW_ID_NONE,
> },
> };
>
> @@ -2084,13 +2084,13 @@ static const struct i915_power_well_desc
> i830_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "pipes",
> .domains = I830_PIPES_POWER_DOMAINS,
> .ops = &i830_pipes_power_well_ops,
> - .id = I830_DISP_PW_PIPES,
> + .id = DISP_PW_ID_NONE,
> },
> };
>
> @@ -2128,7 +2128,7 @@ static const struct i915_power_well_desc
> hsw_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "display",
> @@ -2149,7 +2149,7 @@ static const struct i915_power_well_desc
> bdw_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "display",
> @@ -2192,7 +2192,7 @@ static const struct i915_power_well_desc
> vlv_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "display",
> @@ -2210,7 +2210,7 @@ static const struct i915_power_well_desc
> vlv_power_wells[] = {
> VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> .ops = &vlv_dpio_power_well_ops,
> - .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
> + .id = DISP_PW_ID_NONE,
> {
> .vlv.idx =
> PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
> },
> @@ -2222,7 +2222,7 @@ static const struct i915_power_well_desc
> vlv_power_wells[] = {
> VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> .ops = &vlv_dpio_power_well_ops,
> - .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
> + .id = DISP_PW_ID_NONE,
> {
> .vlv.idx =
> PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
> },
> @@ -2234,7 +2234,7 @@ static const struct i915_power_well_desc
> vlv_power_wells[] = {
> VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> .ops = &vlv_dpio_power_well_ops,
> - .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
> + .id = DISP_PW_ID_NONE,
> {
> .vlv.idx =
> PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
> },
> @@ -2246,7 +2246,7 @@ static const struct i915_power_well_desc
> vlv_power_wells[] = {
> VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> .ops = &vlv_dpio_power_well_ops,
> - .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
> + .id = DISP_PW_ID_NONE,
> {
> .vlv.idx =
> PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
> },
> @@ -2268,7 +2268,7 @@ static const struct i915_power_well_desc
> chv_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "display",
> @@ -2279,7 +2279,7 @@ static const struct i915_power_well_desc
> chv_power_wells[] = {
> */
> .domains = CHV_DISPLAY_POWER_DOMAINS,
> .ops = &chv_pipe_power_well_ops,
> - .id = CHV_DISP_PW_PIPE_A,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "dpio-common-bc",
> @@ -2319,7 +2319,7 @@ static const struct i915_power_well_desc
> skl_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "power well 1",
> @@ -2348,7 +2348,7 @@ static const struct i915_power_well_desc
> skl_power_wells[] = {
> .name = "DC off",
> .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_PW_DC_OFF,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "power well 2",
> @@ -2367,7 +2367,7 @@ static const struct i915_power_well_desc
> skl_power_wells[] = {
> .name = "DDI A/E IO power well",
> .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_A_E,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
> @@ -2377,7 +2377,7 @@ static const struct i915_power_well_desc
> skl_power_wells[] = {
> .name = "DDI B IO power well",
> .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_B,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
> @@ -2387,7 +2387,7 @@ static const struct i915_power_well_desc
> skl_power_wells[] = {
> .name = "DDI C IO power well",
> .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_C,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
> @@ -2397,7 +2397,7 @@ static const struct i915_power_well_desc
> skl_power_wells[] = {
> .name = "DDI D IO power well",
> .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_D,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
> @@ -2411,7 +2411,7 @@ static const struct i915_power_well_desc
> bxt_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "power well 1",
> @@ -2428,7 +2428,7 @@ static const struct i915_power_well_desc
> bxt_power_wells[] = {
> .name = "DC off",
> .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_PW_DC_OFF,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "power well 2",
> @@ -2469,7 +2469,7 @@ static const struct i915_power_well_desc
> glk_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "power well 1",
> @@ -2487,7 +2487,7 @@ static const struct i915_power_well_desc
> glk_power_wells[] = {
> .name = "DC off",
> .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
> .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_PW_DC_OFF,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "power well 2",
> @@ -2533,7 +2533,7 @@ static const struct i915_power_well_desc
> glk_power_wells[] = {
> .name = "AUX A",
> .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = GLK_DISP_PW_AUX_A,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
> @@ -2543,7 +2543,7 @@ static const struct i915_power_well_desc
> glk_power_wells[] = {
> .name = "AUX B",
> .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = GLK_DISP_PW_AUX_B,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
> @@ -2553,7 +2553,7 @@ static const struct i915_power_well_desc
> glk_power_wells[] = {
> .name = "AUX C",
> .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = GLK_DISP_PW_AUX_C,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
> @@ -2563,7 +2563,7 @@ static const struct i915_power_well_desc
> glk_power_wells[] = {
> .name = "DDI A IO power well",
> .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = GLK_DISP_PW_DDI_A,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
> @@ -2573,7 +2573,7 @@ static const struct i915_power_well_desc
> glk_power_wells[] = {
> .name = "DDI B IO power well",
> .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_B,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
> @@ -2583,7 +2583,7 @@ static const struct i915_power_well_desc
> glk_power_wells[] = {
> .name = "DDI C IO power well",
> .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_C,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
> @@ -2597,7 +2597,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "power well 1",
> @@ -2615,7 +2615,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .name = "AUX A",
> .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_AUX_A,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
> @@ -2625,7 +2625,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .name = "AUX B",
> .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_AUX_B,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
> @@ -2635,7 +2635,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .name = "AUX C",
> .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_AUX_C,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
> @@ -2645,7 +2645,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .name = "AUX D",
> .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_AUX_D,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = CNL_PW_CTL_IDX_AUX_D,
> @@ -2655,7 +2655,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .name = "DC off",
> .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
> .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_PW_DC_OFF,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "power well 2",
> @@ -2674,7 +2674,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .name = "DDI A IO power well",
> .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_DDI_A,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
> @@ -2684,7 +2684,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .name = "DDI B IO power well",
> .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_B,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
> @@ -2694,7 +2694,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .name = "DDI C IO power well",
> .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_C,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
> @@ -2704,7 +2704,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .name = "DDI D IO power well",
> .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_DDI_D,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
> @@ -2714,7 +2714,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .name = "DDI F IO power well",
> .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_DDI_F,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = CNL_PW_CTL_IDX_DDI_F,
> @@ -2724,7 +2724,7 @@ static const struct i915_power_well_desc
> cnl_power_wells[] = {
> .name = "AUX F",
> .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = CNL_DISP_PW_AUX_F,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = CNL_PW_CTL_IDX_AUX_F,
> @@ -2757,7 +2757,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .always_on = 1,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> - .id = I915_DISP_PW_ALWAYS_ON,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "power well 1",
> @@ -2786,13 +2786,13 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "DC off",
> .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
> .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_PW_DC_OFF,
> + .id = DISP_PW_ID_NONE,
> },
> {
> .name = "power well 3",
> .domains = ICL_PW_3_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_3,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> @@ -2805,7 +2805,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "DDI A IO",
> .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_DDI_A,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_ddi_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> @@ -2815,7 +2815,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "DDI B IO",
> .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_DDI_B,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_ddi_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> @@ -2825,7 +2825,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "DDI C IO",
> .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_DDI_C,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_ddi_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> @@ -2835,7 +2835,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "DDI D IO",
> .domains = ICL_DDI_IO_D_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_DDI_D,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_ddi_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
> @@ -2845,7 +2845,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "DDI E IO",
> .domains = ICL_DDI_IO_E_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_DDI_E,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_ddi_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
> @@ -2855,7 +2855,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "DDI F IO",
> .domains = ICL_DDI_IO_F_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_DDI_F,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_ddi_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
> @@ -2865,7 +2865,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "AUX A",
> .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> .ops = &icl_combo_phy_aux_power_well_ops,
> - .id = ICL_DISP_PW_AUX_A,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> @@ -2875,7 +2875,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "AUX B",
> .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> .ops = &icl_combo_phy_aux_power_well_ops,
> - .id = ICL_DISP_PW_AUX_B,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> @@ -2885,7 +2885,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "AUX C",
> .domains = ICL_AUX_C_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_AUX_C,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> @@ -2895,7 +2895,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "AUX D",
> .domains = ICL_AUX_D_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_AUX_D,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
> @@ -2905,7 +2905,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "AUX E",
> .domains = ICL_AUX_E_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_AUX_E,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
> @@ -2915,7 +2915,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "AUX F",
> .domains = ICL_AUX_F_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_AUX_F,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
> @@ -2925,7 +2925,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "AUX TBT1",
> .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_AUX_TBT1,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
> @@ -2935,7 +2935,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "AUX TBT2",
> .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_AUX_TBT2,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
> @@ -2945,7 +2945,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "AUX TBT3",
> .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_AUX_TBT3,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
> @@ -2955,7 +2955,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "AUX TBT4",
> .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_AUX_TBT4,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
> @@ -2965,7 +2965,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "power well 4",
> .domains = ICL_PW_4_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_4,
> + .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> @@ -3054,6 +3054,9 @@ __set_power_wells(struct i915_power_domains
> *power_domains,
>
> power_domains->power_wells[i].desc =
> &power_well_descs[i];
>
> + if (id == DISP_PW_ID_NONE)
> + continue;
> +
> WARN_ON(id >= sizeof(power_well_ids) * 8);
> WARN_ON(power_well_ids & BIT_ULL(id));
> power_well_ids |= BIT_ULL(id);
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 08/10] drm/i915: Make power well ID names more uniform
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
` (6 preceding siblings ...)
2018-08-06 9:58 ` [PATCH v2 07/10] drm/i915: Remove redundant power well IDs Imre Deak
@ 2018-08-06 9:58 ` Imre Deak
2018-08-06 9:58 ` [PATCH v2 09/10] drm/i915: Use existing power well IDs where possible Imre Deak
` (4 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2018-08-06 9:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni
The format for the ID names is <platform>_DISP_PW_* so rename the IDs
not following this accordingly. Leave BXT_DPIO_CMN_BC as-is since we'll
change that to use another existing ID in the next patch.
v2:
- Fix line over 80 chars checkpatch warning.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++++----
drivers/gpu/drm/i915/intel_runtime_pm.c | 45 +++++++++++++++++----------------
2 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4568adc8369a..ef1fa5054e88 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1036,16 +1036,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
enum i915_power_well_id {
DISP_PW_ID_NONE,
- PUNIT_POWER_WELL_DISP2D,
- PUNIT_POWER_WELL_DPIO_CMN_BC,
- PUNIT_POWER_WELL_DPIO_CMN_D,
+ VLV_DISP_PW_DISP2D,
+ BXT_DISP_PW_DPIO_CMN_A,
+ VLV_DISP_PW_DPIO_CMN_BC,
+ GLK_DISP_PW_DPIO_CMN_C,
+ CHV_DISP_PW_DPIO_CMN_D,
HSW_DISP_PW_GLOBAL,
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
- BXT_DPIO_CMN_A,
BXT_DPIO_CMN_BC,
- GLK_DPIO_CMN_C,
ICL_DISP_PW_1,
ICL_DISP_PW_2,
};
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6aec980cea07..ae08f7824204 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -768,7 +768,7 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
{
struct i915_power_well *power_well;
- power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
+ power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
if (power_well->count > 0)
bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
@@ -777,7 +777,8 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
if (IS_GEMINILAKE(dev_priv)) {
- power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C);
+ power_well = lookup_power_well(dev_priv,
+ GLK_DISP_PW_DPIO_CMN_C);
if (power_well->count > 0)
bxt_ddi_phy_verify_state(dev_priv,
power_well->desc->bxt.phy);
@@ -1129,9 +1130,9 @@ lookup_power_well(struct drm_i915_private *dev_priv,
static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
{
struct i915_power_well *cmn_bc =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
+ lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
+ lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
u32 phy_control = dev_priv->chv_phy_control;
u32 phy_status = 0;
u32 phy_status_mask = 0xffffffff;
@@ -1241,10 +1242,10 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
enum pipe pipe;
uint32_t tmp;
- WARN_ON_ONCE(power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
- power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_D);
+ WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
+ power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
- if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
pipe = PIPE_A;
phy = DPIO_PHY0;
} else {
@@ -1272,7 +1273,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
- if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
tmp |= DPIO_DYNPWRDOWNEN_CH1;
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
@@ -1303,10 +1304,10 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
{
enum dpio_phy phy;
- WARN_ON_ONCE(power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
- power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_D);
+ WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
+ power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
- if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
phy = DPIO_PHY0;
assert_pll_disabled(dev_priv, PIPE_A);
assert_pll_disabled(dev_priv, PIPE_B);
@@ -2198,7 +2199,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
.name = "display",
.domains = VLV_DISPLAY_POWER_DOMAINS,
.ops = &vlv_display_power_well_ops,
- .id = PUNIT_POWER_WELL_DISP2D,
+ .id = VLV_DISP_PW_DISP2D,
{
.vlv.idx = PUNIT_PWGT_IDX_DISP2D,
},
@@ -2255,7 +2256,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
.name = "dpio-common",
.domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
.ops = &vlv_dpio_cmn_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
},
@@ -2285,7 +2286,7 @@ static const struct i915_power_well_desc chv_power_wells[] = {
.name = "dpio-common-bc",
.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
.ops = &chv_dpio_cmn_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
},
@@ -2294,7 +2295,7 @@ static const struct i915_power_well_desc chv_power_wells[] = {
.name = "dpio-common-d",
.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
.ops = &chv_dpio_cmn_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_CMN_D,
+ .id = CHV_DISP_PW_DPIO_CMN_D,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
},
@@ -2447,7 +2448,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.name = "dpio-common-a",
.domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DPIO_CMN_A,
+ .id = BXT_DISP_PW_DPIO_CMN_A,
{
.bxt.phy = DPIO_PHY1,
},
@@ -2506,7 +2507,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "dpio-common-a",
.domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DPIO_CMN_A,
+ .id = BXT_DISP_PW_DPIO_CMN_A,
{
.bxt.phy = DPIO_PHY1,
},
@@ -2524,7 +2525,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "dpio-common-c",
.domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = GLK_DPIO_CMN_C,
+ .id = GLK_DISP_PW_DPIO_CMN_C,
{
.bxt.phy = DPIO_PHY2,
},
@@ -3626,9 +3627,9 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
static void chv_phy_control_init(struct drm_i915_private *dev_priv)
{
struct i915_power_well *cmn_bc =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
+ lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
+ lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
/*
* DISPLAY_PHY_CONTROL can get corrupted if read. As a
@@ -3713,9 +3714,9 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
{
struct i915_power_well *cmn =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
+ lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *disp2d =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
+ lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
/* If the display might be already active skip this */
if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&
--
2.13.2
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 09/10] drm/i915: Use existing power well IDs where possible
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
` (7 preceding siblings ...)
2018-08-06 9:58 ` [PATCH v2 08/10] drm/i915: Make power well ID names more uniform Imre Deak
@ 2018-08-06 9:58 ` Imre Deak
2018-08-06 23:05 ` Paulo Zanoni
2018-08-06 9:58 ` [PATCH v2 10/10] drm/i915/icl: Add missing power gate enums Imre Deak
` (3 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2018-08-06 9:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni
There is no need for separate IDs for power wells on a new platform with
the same functionality as an other power well on a previous platform, we
can just reuse the ID from the previous platform. This is only possible
after the previous patches where we removed dependence on the actual
enum values.
v2:
- Keep an ID assigned for the ICL PW#2 power well too. (Paulo)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 ---
drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +++++++-------
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ef1fa5054e88..77b031874ee3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1045,9 +1045,6 @@ enum i915_power_well_id {
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
- BXT_DPIO_CMN_BC,
- ICL_DISP_PW_1,
- ICL_DISP_PW_2,
};
#define PUNIT_REG_PWRGT_CTRL 0x60
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ae08f7824204..810695a71cc8 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -772,7 +772,7 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
if (power_well->count > 0)
bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
- power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
+ power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
if (power_well->count > 0)
bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
@@ -2457,7 +2457,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.name = "dpio-common-bc",
.domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DPIO_CMN_BC,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
{
.bxt.phy = DPIO_PHY0,
},
@@ -2516,7 +2516,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "dpio-common-b",
.domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DPIO_CMN_BC,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
{
.bxt.phy = DPIO_PHY0,
},
@@ -2765,7 +2765,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_1,
+ .id = SKL_DISP_PW_1,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
@@ -2776,7 +2776,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "power well 2",
.domains = ICL_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_2,
+ .id = SKL_DISP_PW_2,
{
.hsw.regs = &hsw_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
@@ -3575,7 +3575,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
* The AUX IO power wells will be enabled on demand.
*/
mutex_lock(&power_domains->lock);
- well = lookup_power_well(dev_priv, ICL_DISP_PW_1);
+ well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
intel_power_well_enable(dev_priv, well);
mutex_unlock(&power_domains->lock);
@@ -3612,7 +3612,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
* disabled at this point.
*/
mutex_lock(&power_domains->lock);
- well = lookup_power_well(dev_priv, ICL_DISP_PW_1);
+ well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
intel_power_well_disable(dev_priv, well);
mutex_unlock(&power_domains->lock);
--
2.13.2
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 09/10] drm/i915: Use existing power well IDs where possible
2018-08-06 9:58 ` [PATCH v2 09/10] drm/i915: Use existing power well IDs where possible Imre Deak
@ 2018-08-06 23:05 ` Paulo Zanoni
0 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-08-06 23:05 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: Jani Nikula
Em Seg, 2018-08-06 às 12:58 +0300, Imre Deak escreveu:
> There is no need for separate IDs for power wells on a new platform
> with
> the same functionality as an other power well on a previous platform,
> we
> can just reuse the ID from the previous platform. This is only
> possible
> after the previous patches where we removed dependence on the actual
> enum values.
>
> v2:
> - Keep an ID assigned for the ICL PW#2 power well too. (Paulo)
A brief mention in the commit message that this actually fixes a bug on
ICL may be good.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +++++++-------
> 2 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index ef1fa5054e88..77b031874ee3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1045,9 +1045,6 @@ enum i915_power_well_id {
> SKL_DISP_PW_MISC_IO,
> SKL_DISP_PW_1,
> SKL_DISP_PW_2,
> - BXT_DPIO_CMN_BC,
> - ICL_DISP_PW_1,
> - ICL_DISP_PW_2,
> };
>
> #define PUNIT_REG_PWRGT_CTRL 0x60
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index ae08f7824204..810695a71cc8 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -772,7 +772,7 @@ static void bxt_verify_ddi_phy_power_wells(struct
> drm_i915_private *dev_priv)
> if (power_well->count > 0)
> bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
> >bxt.phy);
>
> - power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
> + power_well = lookup_power_well(dev_priv,
> VLV_DISP_PW_DPIO_CMN_BC);
> if (power_well->count > 0)
> bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
> >bxt.phy);
>
> @@ -2457,7 +2457,7 @@ static const struct i915_power_well_desc
> bxt_power_wells[] = {
> .name = "dpio-common-bc",
> .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
> .ops = &bxt_dpio_cmn_power_well_ops,
> - .id = BXT_DPIO_CMN_BC,
> + .id = VLV_DISP_PW_DPIO_CMN_BC,
> {
> .bxt.phy = DPIO_PHY0,
> },
> @@ -2516,7 +2516,7 @@ static const struct i915_power_well_desc
> glk_power_wells[] = {
> .name = "dpio-common-b",
> .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
> .ops = &bxt_dpio_cmn_power_well_ops,
> - .id = BXT_DPIO_CMN_BC,
> + .id = VLV_DISP_PW_DPIO_CMN_BC,
> {
> .bxt.phy = DPIO_PHY0,
> },
> @@ -2765,7 +2765,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> /* Handled by the DMC firmware */
> .domains = 0,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_1,
> + .id = SKL_DISP_PW_1,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> @@ -2776,7 +2776,7 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> .name = "power well 2",
> .domains = ICL_PW_2_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_2,
> + .id = SKL_DISP_PW_2,
> {
> .hsw.regs = &hsw_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> @@ -3575,7 +3575,7 @@ static void icl_display_core_init(struct
> drm_i915_private *dev_priv,
> * The AUX IO power wells will be enabled on demand.
> */
> mutex_lock(&power_domains->lock);
> - well = lookup_power_well(dev_priv, ICL_DISP_PW_1);
> + well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> intel_power_well_enable(dev_priv, well);
> mutex_unlock(&power_domains->lock);
>
> @@ -3612,7 +3612,7 @@ static void icl_display_core_uninit(struct
> drm_i915_private *dev_priv)
> * disabled at this point.
> */
> mutex_lock(&power_domains->lock);
> - well = lookup_power_well(dev_priv, ICL_DISP_PW_1);
> + well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> intel_power_well_disable(dev_priv, well);
> mutex_unlock(&power_domains->lock);
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 10/10] drm/i915/icl: Add missing power gate enums
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
` (8 preceding siblings ...)
2018-08-06 9:58 ` [PATCH v2 09/10] drm/i915: Use existing power well IDs where possible Imre Deak
@ 2018-08-06 9:58 ` Imre Deak
2018-08-06 10:09 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up power well descriptors (rev2) Patchwork
` (2 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2018-08-06 9:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Paulo Zanoni
On ICL there are 5 fused power gates, so add the two missing ones for
clarity.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77b031874ee3..17575cfc22b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8913,6 +8913,8 @@ enum skl_power_gate {
SKL_PG0,
SKL_PG1,
SKL_PG2,
+ ICL_PG3,
+ ICL_PG4,
};
#define SKL_FUSE_STATUS _MMIO(0x42000)
--
2.13.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up power well descriptors (rev2)
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
` (9 preceding siblings ...)
2018-08-06 9:58 ` [PATCH v2 10/10] drm/i915/icl: Add missing power gate enums Imre Deak
@ 2018-08-06 10:09 ` Patchwork
2018-08-06 10:14 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-08-08 11:50 ` [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
12 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-08-06 10:09 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up power well descriptors (rev2)
URL : https://patchwork.freedesktop.org/series/46952/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6c5eac3775d7 drm/i915/icl: Fix power well anonymous union initializers
69d41b65c165 drm/i915: Rename intel_power_domains_fini() to intel_power_domains_fini_hw()
26c9786d1d90 drm/i915/vlv: Remove redundant power well ID asserts
91d740c8b8c3 drm/i915: Constify power well descriptors
-:548: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#548: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:2821:
+ power_domains->power_wells = kcalloc(power_well_count,
+ sizeof(*power_domains->power_wells),
-:570: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well_descs' - possible side-effects?
#570: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:2839:
+#define set_power_wells(power_domains, __power_well_descs) \
+ __set_power_wells(power_domains, __power_well_descs, \
+ ARRAY_SIZE(__power_well_descs))
total: 0 errors, 0 warnings, 2 checks, 643 lines checked
b9b4129e0c4b drm/i915/vlv: Use power well CTL IDX instead of ID
63bb461d5477 drm/i915/ddi: Use power well CTL IDX instead of ID
-:270: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#270: FILE: drivers/gpu/drm/i915/i915_reg.h:9034:
+#define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
_CNL_AUX_ANAOVRD1_B, \
_CNL_AUX_ANAOVRD1_C, \
_CNL_AUX_ANAOVRD1_D, \
total: 1 errors, 0 warnings, 0 checks, 970 lines checked
084bb4517662 drm/i915: Remove redundant power well IDs
7dbcf6a6c869 drm/i915: Make power well ID names more uniform
140918e2ab61 drm/i915: Use existing power well IDs where possible
6fc28e2d1537 drm/i915/icl: Add missing power gate enums
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^ permalink raw reply [flat|nested] 17+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up power well descriptors (rev2)
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
` (10 preceding siblings ...)
2018-08-06 10:09 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up power well descriptors (rev2) Patchwork
@ 2018-08-06 10:14 ` Patchwork
2018-08-08 11:50 ` [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
12 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-08-06 10:14 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up power well descriptors (rev2)
URL : https://patchwork.freedesktop.org/series/46952/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Fix power well anonymous union initializers
Okay!
Commit: drm/i915: Rename intel_power_domains_fini() to intel_power_domains_fini_hw()
Okay!
Commit: drm/i915/vlv: Remove redundant power well ID asserts
Okay!
Commit: drm/i915: Constify power well descriptors
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3653:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3657:16: warning: expression using sizeof(void)
+./include/linux/slab.h:631:13: error: undefined identifier '__builtin_mul_overflow'
+./include/linux/slab.h:631:13: warning: call with no type!
Commit: drm/i915/vlv: Use power well CTL IDX instead of ID
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3657:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3664:16: warning: expression using sizeof(void)
Commit: drm/i915/ddi: Use power well CTL IDX instead of ID
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3664:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3677:16: warning: expression using sizeof(void)
Commit: drm/i915: Remove redundant power well IDs
Okay!
Commit: drm/i915: Make power well ID names more uniform
Okay!
Commit: drm/i915: Use existing power well IDs where possible
Okay!
Commit: drm/i915/icl: Add missing power gate enums
Okay!
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v2 00/10] drm/i915: Clean up power well descriptors
2018-08-06 9:58 [PATCH v2 00/10] drm/i915: Clean up power well descriptors Imre Deak
` (11 preceding siblings ...)
2018-08-06 10:14 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-08-08 11:50 ` Imre Deak
12 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2018-08-08 11:50 UTC (permalink / raw)
To: intel-gfx, Paulo R Zanoni, Rodrigo Vivi; +Cc: Jani Nikula
On Mon, Aug 06, 2018 at 12:58:33PM +0300, Imre Deak wrote:
> This is v2 of [1], fixing the issues Paulo noticed.
>
> [1] https://patchwork.freedesktop.org/series/46952/
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Pushed the series to -dinq thanks for the reviews.
>
> Imre Deak (10):
> drm/i915/icl: Fix power well anonymous union initializers
> drm/i915: Rename intel_power_domains_fini() to
> intel_power_domains_fini_hw()
> drm/i915/vlv: Remove redundant power well ID asserts
> drm/i915: Constify power well descriptors
> drm/i915/vlv: Use power well CTL IDX instead of ID
> drm/i915/ddi: Use power well CTL IDX instead of ID
> drm/i915: Remove redundant power well IDs
> drm/i915: Make power well ID names more uniform
> drm/i915: Use existing power well IDs where possible
> drm/i915/icl: Add missing power gate enums
>
> drivers/gpu/drm/i915/gvt/handlers.c | 31 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.c | 12 +-
> drivers/gpu/drm/i915/i915_drv.h | 34 +-
> drivers/gpu/drm/i915/i915_reg.h | 271 +++++------
> drivers/gpu/drm/i915/intel_display.c | 5 +-
> drivers/gpu/drm/i915/intel_display.h | 4 +-
> drivers/gpu/drm/i915/intel_drv.h | 3 +-
> drivers/gpu/drm/i915/intel_hdcp.c | 6 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 788 +++++++++++++++++++++-----------
> 10 files changed, 694 insertions(+), 464 deletions(-)
>
> --
> 2.13.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread