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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 07/28] drm/i915: Lift i915_request_show()
Date: Tue, 17 Nov 2020 12:51:22 +0000	[thread overview]
Message-ID: <1d6c5192-cdf5-0550-1c98-acc4f3abca13@linux.intel.com> (raw)
In-Reply-To: <20201117113103.21480-7-chris@chris-wilson.co.uk>


On 17/11/2020 11:30, Chris Wilson wrote:
> Extract i915_request_show for reuse in other request chain pretty
> printers.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/gt/intel_engine_cs.c | 47 ++---------------------
>   drivers/gpu/drm/i915/gt/intel_lrc.c       |  2 +-
>   drivers/gpu/drm/i915/gt/intel_lrc.h       |  2 +-
>   drivers/gpu/drm/i915/i915_request.c       | 39 +++++++++++++++++++
>   drivers/gpu/drm/i915/i915_request.h       |  5 +++
>   5 files changed, 50 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 1ed84ee8ce41..c3bb2e9546e6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1294,45 +1294,6 @@ bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
>   	}
>   }
>   
> -static int print_sched_attr(const struct i915_sched_attr *attr,
> -			    char *buf, int x, int len)
> -{
> -	if (attr->priority == I915_PRIORITY_INVALID)
> -		return x;
> -
> -	x += snprintf(buf + x, len - x,
> -		      " prio=%d", attr->priority);
> -
> -	return x;
> -}
> -
> -static void print_request(struct drm_printer *m,
> -			  struct i915_request *rq,
> -			  const char *prefix)
> -{
> -	const char *name = rq->fence.ops->get_timeline_name(&rq->fence);
> -	char buf[80] = "";
> -	int x = 0;
> -
> -	x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf));
> -
> -	drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n",
> -		   prefix,
> -		   rq->fence.context, rq->fence.seqno,
> -		   i915_request_completed(rq) ? "!" :
> -		   i915_request_started(rq) ? "*" :
> -		   !i915_sw_fence_signaled(&rq->semaphore) ? "&" :
> -		   "",
> -		   test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
> -			    &rq->fence.flags) ? "+" :
> -		   test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
> -			    &rq->fence.flags) ? "-" :
> -		   "",
> -		   buf,
> -		   jiffies_to_msecs(jiffies - rq->emitted_jiffies),
> -		   name);
> -}
> -
>   static struct intel_timeline *get_timeline(struct i915_request *rq)
>   {
>   	struct intel_timeline *tl;
> @@ -1530,7 +1491,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>   					intel_context_is_banned(rq->context) ? "*" : "");
>   			len += print_ring(hdr + len, sizeof(hdr) - len, rq);
>   			scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
> -			print_request(m, rq, hdr);
> +			i915_request_show(m, rq, hdr);
>   		}
>   		for (port = execlists->pending; (rq = *port); port++) {
>   			char hdr[160];
> @@ -1544,7 +1505,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>   					intel_context_is_banned(rq->context) ? "*" : "");
>   			len += print_ring(hdr + len, sizeof(hdr) - len, rq);
>   			scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
> -			print_request(m, rq, hdr);
> +			i915_request_show(m, rq, hdr);
>   		}
>   		rcu_read_unlock();
>   		execlists_active_unlock_bh(execlists);
> @@ -1688,7 +1649,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>   	if (rq) {
>   		struct intel_timeline *tl = get_timeline(rq);
>   
> -		print_request(m, rq, "\t\tactive ");
> +		i915_request_show(m, rq, "\t\tactive ");
>   
>   		drm_printf(m, "\t\tring->start:  0x%08x\n",
>   			   i915_ggtt_offset(rq->ring->vma));
> @@ -1726,7 +1687,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>   		drm_printf(m, "\tDevice is asleep; skipping register dump\n");
>   	}
>   
> -	intel_execlists_show_requests(engine, m, print_request, 8);
> +	intel_execlists_show_requests(engine, m, i915_request_show, 8);
>   
>   	drm_printf(m, "HWSP:\n");
>   	hexdump(m, engine->status_page.addr, PAGE_SIZE);
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 52b84474f93a..a4b8c20d12a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -5980,7 +5980,7 @@ int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine,
>   void intel_execlists_show_requests(struct intel_engine_cs *engine,
>   				   struct drm_printer *m,
>   				   void (*show_request)(struct drm_printer *m,
> -							struct i915_request *rq,
> +							const struct i915_request *rq,
>   							const char *prefix),
>   				   unsigned int max)
>   {
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
> index c2d287f25497..32e6e204f544 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
> @@ -106,7 +106,7 @@ void intel_lr_context_reset(struct intel_engine_cs *engine,
>   void intel_execlists_show_requests(struct intel_engine_cs *engine,
>   				   struct drm_printer *m,
>   				   void (*show_request)(struct drm_printer *m,
> -							struct i915_request *rq,
> +							const struct i915_request *rq,
>   							const char *prefix),
>   				   unsigned int max);
>   
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index 0e813819b041..cebe07a85625 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -1855,6 +1855,45 @@ long i915_request_wait(struct i915_request *rq,
>   	return timeout;
>   }
>   
> +static int print_sched_attr(const struct i915_sched_attr *attr,
> +			    char *buf, int x, int len)
> +{
> +	if (attr->priority == I915_PRIORITY_INVALID)
> +		return x;
> +
> +	x += snprintf(buf + x, len - x,
> +		      " prio=%d", attr->priority);
> +
> +	return x;
> +}
> +
> +void i915_request_show(struct drm_printer *m,
> +		       const struct i915_request *rq,
> +		       const char *prefix)
> +{
> +	const char *name = rq->fence.ops->get_timeline_name((struct dma_fence *)&rq->fence);
> +	char buf[80] = "";
> +	int x = 0;
> +
> +	x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf));
> +
> +	drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n",

$ grep "llx:%lld" . -r | wc -l
20
$ grep "llx:%llx" . -r | wc -l
3

Bonus points if you make the seqno lld making it 21 to 2, one step 
closer to bliss. ;)

> +		   prefix,
> +		   rq->fence.context, rq->fence.seqno,
> +		   i915_request_completed(rq) ? "!" :
> +		   i915_request_started(rq) ? "*" :
> +		   !i915_sw_fence_signaled(&rq->semaphore) ? "&" :
> +		   "",
> +		   test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
> +			    &rq->fence.flags) ? "+" :
> +		   test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
> +			    &rq->fence.flags) ? "-" :
> +		   "",
> +		   buf,
> +		   jiffies_to_msecs(jiffies - rq->emitted_jiffies),
> +		   name);
> +}
> +
>   #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
>   #include "selftests/mock_request.c"
>   #include "selftests/i915_request.c"
> diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
> index 16b721080195..09609071b725 100644
> --- a/drivers/gpu/drm/i915/i915_request.h
> +++ b/drivers/gpu/drm/i915/i915_request.h
> @@ -43,6 +43,7 @@
>   
>   struct drm_file;
>   struct drm_i915_gem_object;
> +struct drm_printer;
>   struct i915_request;
>   
>   struct i915_capture_list {
> @@ -369,6 +370,10 @@ long i915_request_wait(struct i915_request *rq,
>   #define I915_WAIT_PRIORITY	BIT(1) /* small priority bump for the request */
>   #define I915_WAIT_ALL		BIT(2) /* used by i915_gem_object_wait() */
>   
> +void i915_request_show(struct drm_printer *m,
> +		       const struct i915_request *rq,
> +		       const char *prefix);
> +
>   static inline bool i915_request_signaled(const struct i915_request *rq)
>   {
>   	/* The request may live longer than its HWSP, so check flags first! */
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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  reply	other threads:[~2020-11-17 12:51 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-17 11:30 [Intel-gfx] [PATCH 01/28] drm/i915/selftests: Improve granularity for mocs reset checks Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 02/28] drm/i915/selftests: Small tweak to put the termination conditions together Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 03/28] drm/i915/gem: Drop free_work for GEM contexts Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 04/28] drm/i915/gt: Ignore dt==0 for reporting underflows Chris Wilson
2020-11-17 11:42   ` Tvrtko Ursulin
2020-11-17 11:30 ` [Intel-gfx] [PATCH 05/28] drm/i915/gt: Track the overall busy time Chris Wilson
2020-11-17 12:44   ` Tvrtko Ursulin
2020-11-17 13:05     ` Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 06/28] drm/i915/gt: Include semaphore status in print_request() Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 07/28] drm/i915: Lift i915_request_show() Chris Wilson
2020-11-17 12:51   ` Tvrtko Ursulin [this message]
2020-11-17 11:30 ` [Intel-gfx] [PATCH 08/28] drm/i915/gt: Show all active timelines for debugging Chris Wilson
2020-11-17 12:59   ` Tvrtko Ursulin
2020-11-17 13:25     ` Chris Wilson
2020-11-18 15:51       ` Tvrtko Ursulin
2020-11-19 10:47         ` Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 09/28] drm/i915: Lift waiter/signaler iterators Chris Wilson
2020-11-17 13:00   ` Tvrtko Ursulin
2020-11-17 11:30 ` [Intel-gfx] [PATCH 10/28] drm/i915: Show timeline dependencies for debug Chris Wilson
2020-11-17 13:06   ` Tvrtko Ursulin
2020-11-17 13:30     ` Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 11/28] drm/i915/gt: Defer enabling the breadcrumb interrupt to after submission Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 12/28] drm/i915/gt: Track signaled breadcrumbs outside of the breadcrumb spinlock Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 13/28] drm/i915/gt: Don't cancel the interrupt shadow too early Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 14/28] drm/i915/gt: Free stale request on destroying the virtual engine Chris Wilson
2020-11-18 11:05   ` Tvrtko Ursulin
2020-11-18 11:24     ` Chris Wilson
2020-11-18 11:38       ` Tvrtko Ursulin
2020-11-18 12:10         ` Chris Wilson
2020-11-19 14:06           ` Tvrtko Ursulin
2020-11-19 14:22             ` Chris Wilson
2020-11-19 16:17               ` Tvrtko Ursulin
2020-11-17 11:30 ` [Intel-gfx] [PATCH 15/28] drm/i915/gt: Protect context lifetime with RCU Chris Wilson
2020-11-18 11:36   ` Tvrtko Ursulin
2020-11-17 11:30 ` [Intel-gfx] [PATCH 16/28] drm/i915/gt: Split the breadcrumb spinlock between global and contexts Chris Wilson
2020-11-18 11:35   ` Tvrtko Ursulin
2020-11-17 11:30 ` [Intel-gfx] [PATCH 17/28] drm/i915/gt: Move the breadcrumb to the signaler if completed upon cancel Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 18/28] drm/i915/gt: Decouple completed requests on unwind Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 19/28] drm/i915/gt: Check for a completed last request once Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 20/28] drm/i915/gt: Replace direct submit with direct call to tasklet Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 21/28] drm/i915/gt: ce->inflight updates are now serialised Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 22/28] drm/i915/gt: Use virtual_engine during execlists_dequeue Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 23/28] drm/i915/gt: Decouple inflight virtual engines Chris Wilson
2020-11-17 11:30 ` [Intel-gfx] [PATCH 24/28] drm/i915/gt: Defer schedule_out until after the next dequeue Chris Wilson
2020-11-17 11:31 ` [Intel-gfx] [PATCH 25/28] drm/i915/gt: Remove virtual breadcrumb before transfer Chris Wilson
2020-11-17 11:31 ` [Intel-gfx] [PATCH 26/28] drm/i915/gt: Shrink the critical section for irq signaling Chris Wilson
2020-11-17 11:31 ` [Intel-gfx] [PATCH 27/28] drm/i915/gt: Resubmit the virtual engine on schedule-out Chris Wilson
2020-11-17 11:31 ` [Intel-gfx] [PATCH 28/28] drm/i915/gt: Simplify virtual engine handling for execlists_hold() Chris Wilson
2020-11-17 18:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/28] drm/i915/selftests: Improve granularity for mocs reset checks Patchwork
2020-11-17 18:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-17 19:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-17 22:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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