From: "Shankar, Uma" <uma.shankar@intel.com>
To: "Nikula, Jani" <jani.nikula@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
"Nikula, Jani" <jani.nikula@intel.com>
Subject: Re: [Intel-gfx] [PATCH v2 1/6] drm/displayid: re-align data block macros
Date: Mon, 13 Sep 2021 05:31:49 +0000 [thread overview]
Message-ID: <1e6e31e240cd48888c3fcd08db20c523@intel.com> (raw)
In-Reply-To: <b73d3ff2d5e4b23834ed0005186c5cf3a9de5c9e.1630419362.git.jani.nikula@intel.com>
> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [PATCH v2 1/6] drm/displayid: re-align data block macros
>
> Make the values easier to read. Also add DisplayID Structure version and revision
> information (this is different from the spec version).
Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/drm/drm_displayid.h | 57 +++++++++++++++++++------------------
> 1 file changed, 29 insertions(+), 28 deletions(-)
>
> diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h index
> ec64d141f578..0ed9445b5482 100644
> --- a/include/drm/drm_displayid.h
> +++ b/include/drm/drm_displayid.h
> @@ -26,35 +26,36 @@
>
> struct edid;
>
> -#define DATA_BLOCK_PRODUCT_ID 0x00
> -#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01 -#define
> DATA_BLOCK_COLOR_CHARACTERISTICS 0x02 -#define
> DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03 -#define
> DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04 -#define
> DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05 -#define
> DATA_BLOCK_TYPE_4_DMT_TIMING 0x06 -#define DATA_BLOCK_VESA_TIMING
> 0x07 -#define DATA_BLOCK_CEA_TIMING 0x08 -#define
> DATA_BLOCK_VIDEO_TIMING_RANGE 0x09 -#define
> DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a -#define
> DATA_BLOCK_GP_ASCII_STRING 0x0b -#define
> DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c -#define
> DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d -#define
> DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e -#define
> DATA_BLOCK_DISPLAY_INTERFACE 0x0f -#define
> DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10 -#define
> DATA_BLOCK_TILED_DISPLAY 0x12 -#define DATA_BLOCK_CTA 0x81
> +/* DisplayID Structure v1r2 Data Blocks */
> +#define DATA_BLOCK_PRODUCT_ID 0x00
> +#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01
> +#define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02
> +#define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03
> +#define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04
> +#define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05
> +#define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06
> +#define DATA_BLOCK_VESA_TIMING 0x07
> +#define DATA_BLOCK_CEA_TIMING 0x08
> +#define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09
> +#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a
> +#define DATA_BLOCK_GP_ASCII_STRING 0x0b
> +#define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c
> +#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d
> +#define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e
> +#define DATA_BLOCK_DISPLAY_INTERFACE 0x0f
> +#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10
> +#define DATA_BLOCK_TILED_DISPLAY 0x12
> +#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
> +#define DATA_BLOCK_CTA 0x81
>
> -#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
> -
> -#define PRODUCT_TYPE_EXTENSION 0
> -#define PRODUCT_TYPE_TEST 1
> -#define PRODUCT_TYPE_PANEL 2
> -#define PRODUCT_TYPE_MONITOR 3
> -#define PRODUCT_TYPE_TV 4
> -#define PRODUCT_TYPE_REPEATER 5
> -#define PRODUCT_TYPE_DIRECT_DRIVE 6
> +/* DisplayID Structure v1r2 Product Type */
> +#define PRODUCT_TYPE_EXTENSION 0
> +#define PRODUCT_TYPE_TEST 1
> +#define PRODUCT_TYPE_PANEL 2
> +#define PRODUCT_TYPE_MONITOR 3
> +#define PRODUCT_TYPE_TV 4
> +#define PRODUCT_TYPE_REPEATER 5
> +#define PRODUCT_TYPE_DIRECT_DRIVE 6
>
> struct displayid_header {
> u8 rev;
> --
> 2.30.2
next prev parent reply other threads:[~2021-09-13 5:31 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-31 14:17 [Intel-gfx] [PATCH v2 0/6] drm/displayid: VESA vendor block and drm/i915 MSO use of it Jani Nikula
2021-08-31 14:17 ` [Intel-gfx] [PATCH v2 1/6] drm/displayid: re-align data block macros Jani Nikula
2021-09-13 5:31 ` Shankar, Uma [this message]
2021-08-31 14:17 ` [Intel-gfx] [PATCH v2 2/6] drm/displayid: add DisplayID v2.0 data blocks and primary use cases Jani Nikula
2021-09-13 5:33 ` Shankar, Uma
2021-08-31 14:17 ` [Intel-gfx] [PATCH v2 3/6] drm/edid: abstract OUI conversion to 24-bit int Jani Nikula
2021-09-13 5:35 ` Shankar, Uma
2021-08-31 14:17 ` [Intel-gfx] [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO Jani Nikula
2021-09-13 6:23 ` Shankar, Uma
2021-09-13 9:30 ` Jani Nikula
2021-09-13 11:21 ` Shankar, Uma
2021-08-31 14:17 ` [Intel-gfx] [PATCH v2 5/6] drm/i915/edp: postpone MSO init until after EDID read Jani Nikula
2021-09-13 6:24 ` Shankar, Uma
2021-08-31 14:17 ` [Intel-gfx] [PATCH v2 6/6] drm/i915/edp: use MSO pixel overlap from DisplayID data Jani Nikula
2021-09-13 6:26 ` Shankar, Uma
2021-08-31 15:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/displayid: VESA vendor block and drm/i915 MSO use of it (rev2) Patchwork
2021-08-31 15:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-31 19:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-09-13 16:45 ` [Intel-gfx] [PATCH v2 0/6] drm/displayid: VESA vendor block and drm/i915 MSO use of it Jani Nikula
2021-09-14 8:29 ` Maxime Ripard
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