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From: Zhenyu Wang <zhenyuw@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Fix KMS regression on Sandybridge/CPT
Date: Tue, 2 Nov 2010 14:24:22 +0800	[thread overview]
Message-ID: <20101102062422.GA6369@zhen-devel.sh.intel.com> (raw)
In-Reply-To: <849307$a66648@azsmga001.ch.intel.com>


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On 2010.10.29 09:52:31 +0100, Chris Wilson wrote:
> On Fri, 29 Oct 2010 10:34:51 +0800, Zhenyu Wang <zhenyuw@linux.intel.com> wrote:
> > On 2010.10.28 10:50:04 +0100, Chris Wilson wrote:
> > > I've shrunk the patch to just the FDI portion, pushed to staging for
> > > review. 
> > 
> > Current drm-intel-staging still fails unfortunately..
> 
> I'm very interested to know which was the magic bit then. :)
> 
> Did we lose the transcoder bpc setting? Is an extra READ masking a missing
> delay? Is the break-scanline-wait fouling gen6?

I don't think transcoder bpc setting should matter, but sorry that I'm short
of time to track down which one extra read made the difference, my sandybridge
laptop normally refuse to boot on first time.. ;)

The code operation is same as what we have in .36 kernel, so could you restore 
behavior back first?

thanks.

-- 
Open Source Technology Center, Intel ltd.

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  reply	other threads:[~2010-11-02  6:24 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-10-28  8:38 [PATCH] drm/i915: Fix KMS regression on Sandybridge/CPT Zhenyu Wang
2010-10-28  9:50 ` Chris Wilson
2010-10-29  2:34   ` Zhenyu Wang
2010-10-29  8:52     ` Chris Wilson
2010-11-02  6:24       ` Zhenyu Wang [this message]
2010-11-04  2:23         ` Chris Wilson
     [not found]           ` <20101104055024.GJ6369@zhen-devel.sh.intel.com>
2010-11-04  6:26             ` Zhenyu Wang
2010-11-04  9:08             ` Chris Wilson

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