From: Wu Fengguang <fengguang.wu@intel.com>
To: Christopher White <c.white@pulseforce.com>
Cc: Jeremy Bush <contractfrombelow@gmail.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Wang, Zhenyu Z" <zhenyu.z.wang@intel.com>,
"Bossart, Pierre-louis" <pierre-louis.bossart@intel.com>
Subject: Re: [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver
Date: Thu, 10 Nov 2011 15:55:22 +0800 [thread overview]
Message-ID: <20111110075522.GA18260@localhost> (raw)
In-Reply-To: <20111110073350.GA14569@localhost>
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On Thu, Nov 10, 2011 at 03:33:50PM +0800, Wu Fengguang wrote:
> Wow I reproduced the bug and got a very interesting dmesg:
>
> gfx => [ 4561.287980] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-2], [ENCODER:11:TMDS-11]
> gfx => [ 4561.291730] [drm:ironlake_write_eld], ELD on pipe B
> gfx => [ 4561.293804] [drm:ironlake_write_eld], Audio directed to unknown port
> gfx => [ 4561.295273] [drm:ironlake_write_eld],
> alsa => [ 4561.295486] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=0
> alsa => [ 4561.295564] HDMI status: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=0
> gfx => [ 4561.300020] ELD size 13
> alsa => [ 4561.300697] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=1
> alsa => [ 4561.303322] HDMI status: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=1
> alsa => [ 4561.311120] ALSA hda_eld.c:259 HDMI: Unknown ELD version 0
>
> Hey the two parts are interleaved!
>
> But still it should work all fine, since the gfx driver does
>
> set ELD_Valid = 0
> write ELD
> set ELD_Valid = 1
>
> So the audio driver would read the correct ELD unless the ELD content
> and flag writes are somehow _reordered_ underneath. Or the ELD content
> writes take some time to take effect?
Just confirmed that adding 1s delay can fix it!
New dmesg is:
[ 48.564923] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TMDS-11] set [MODE:34:]
[ 48.567481] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe B
[ 48.568975] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-2], [ENCODER:11:TMDS-11]
[ 48.571728] [drm:ironlake_write_eld], ELD on pipe B
[ 48.572882] [drm:ironlake_write_eld], Audio directed to unknown port
[ 48.575252] [drm:ironlake_write_eld],
[ 48.575400] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=0
[ 48.575487] HDMI status: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=0
[ 48.580116] ELD size 13
[ 48.580795] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=1
[ 48.583340] HDMI status: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=1
[ 48.632514] [drm:intel_wait_for_vblank], vblank wait timed out
[ 48.685322] [drm:intel_wait_for_vblank], vblank wait timed out
[ 48.687438] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
[ 48.687438] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
[ 48.690106] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 42, cursor: 6
[ 48.745204] [drm:intel_wait_for_vblank], vblank wait timed out
[ 48.798035] [drm:intel_wait_for_vblank], vblank wait timed out
[ 48.799633] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[ 48.802686] [drm:ironlake_fdi_link_train], FDI train 1 done.
[ 48.805103] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[ 48.807246] [drm:ironlake_fdi_link_train], FDI train 2 done.
[ 48.809426] [drm:ironlake_fdi_link_train], FDI train done
[ 48.813960] [drm:intel_update_fbc],
[ 48.814782] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[ 48.818093] [drm:drm_crtc_helper_set_config], [CONNECTOR:12:HDMI-A-2] set DPMS on
[ 48.828633] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[ 49.618962] HDMI: detected monitor RX-V1800 at connection type HDMI
[ 49.621013] HDMI: available speakers: FL/FR LFE FC RL/RR RC RLC/RRC
[ 49.622304] HDMI: supports coding type LPCM: channels = 2, rates = 32000 44100 48000 96000 176400 192000 384000, bits = 16 20 24
[ 49.625069] HDMI: supports coding type LPCM: channels = 8, rates = 32000 44100 48000 96000 176400 192000 384000, bits = 16 20 24
[ 49.628535] HDMI: supports coding type AC-3: channels = 6, rates = 32000 44100 48000, max bitrate = 640000
[ 49.630810] HDMI: supports coding type DTS: channels = 7, rates = 32000 44100 48000 96000 176400, max bitrate = 1536000
[ 49.633148] HDMI: supports coding type DSD (One Bit Audio): channels = 6, rates = 44100
[ 49.635039] HDMI: supports coding type E-AC-3/DD+ (Dolby Digital Plus): channels = 8, rates = 44100 48000
[ 49.637130] HDMI: supports coding type MLP (Dolby TrueHD): channels = 8, rates = 48000 176400 384000
[ 49.639172] HDMI: supports coding type DTS-HD: channels = 8, rates = 48000 176400 384000
Thanks,
Fengguang
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Subject:
Date: Thu Nov 10 15:41:11 CST 2011
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
---
sound/pci/hda/hda_eld.c | 3 +++
1 file changed, 3 insertions(+)
--- linux.orig/sound/pci/hda/hda_eld.c 2011-11-10 15:39:43.000000000 +0800
+++ linux/sound/pci/hda/hda_eld.c 2011-11-10 15:52:09.000000000 +0800
@@ -23,6 +23,7 @@
#include <linux/init.h>
#include <linux/slab.h>
+#include <linux/delay.h>
#include <sound/core.h>
#include <asm/unaligned.h>
#include "hda_codec.h"
@@ -326,6 +327,8 @@ int snd_hdmi_get_eld(struct hdmi_eld *el
if (!eld->eld_valid)
return -ENOENT;
+ msleep(1000);
+
size = snd_hdmi_get_eld_size(codec, nid);
if (size == 0) {
/* wfg: workaround for ASUS P5E-VM HDMI board */
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
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next prev parent reply other threads:[~2011-11-10 7:55 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-02 8:14 [PATCH v4] drm/i915: pass ELD to HDMI/DP audio driver Wu Fengguang
2011-09-02 8:29 ` Wu Fengguang
2011-09-03 21:15 ` [PATCH v5] " Wu Fengguang
2011-09-04 10:57 ` James Cloos
2011-09-05 1:19 ` Wu Fengguang
2011-09-04 11:11 ` [Intel-gfx] " Paul Menzel
2011-09-05 1:06 ` Wu Fengguang
2011-09-04 12:08 ` Chris Wilson
2011-09-05 1:14 ` Wu Fengguang
2011-09-05 11:04 ` Chris Wilson
2011-09-05 12:31 ` Wu Fengguang
[not found] ` <4E64C41B.5090309@pulseforce.com>
[not found] ` <20110905124730.GB794@localhost>
[not found] ` <4EA82DBD.9020301@pulseforce.com>
2011-10-27 19:57 ` Christopher White
2011-11-09 6:59 ` Wu Fengguang
2011-11-09 9:00 ` Christopher White
2011-11-09 9:30 ` Christopher White
2011-11-09 13:01 ` Wu Fengguang
[not found] ` <4EA9B6EF.9040305@pulseforce.com>
2011-11-01 11:36 ` Wu Fengguang
2011-11-01 17:00 ` Christopher White
2011-11-02 1:45 ` Wu Fengguang
2011-11-02 6:10 ` Sander Jansen
2011-11-02 7:35 ` Paul Menzel
2011-11-02 11:17 ` Sander Jansen
2011-11-02 14:26 ` Sander Jansen
2011-11-02 8:52 ` Wu Fengguang
2011-11-02 17:41 ` Keith Packard
2011-11-04 0:21 ` Tony Olivo
2011-11-05 0:20 ` Christopher White
2011-11-09 13:12 ` Wu Fengguang
2011-11-10 2:25 ` Christopher White
2011-11-10 3:27 ` Wu Fengguang
2011-11-10 4:10 ` Christopher White
2011-11-10 7:06 ` Wu Fengguang
2011-11-10 7:33 ` Wu Fengguang
2011-11-10 7:55 ` Wu Fengguang [this message]
2011-11-10 8:50 ` Wu Fengguang
2011-11-10 8:55 ` Christopher White
2011-11-10 11:00 ` Christopher White
2011-11-10 11:22 ` Takashi Iwai
2011-11-10 11:50 ` Christopher White
2011-11-10 11:53 ` Takashi Iwai
2011-11-10 12:39 ` Christopher White
2011-11-10 13:01 ` Takashi Iwai
2011-11-10 12:56 ` Wu Fengguang
2011-11-10 13:01 ` Christopher White
2011-11-10 13:17 ` Wu Fengguang
2011-11-10 13:34 ` Christopher White
2011-11-10 13:47 ` Wu Fengguang
2011-11-10 14:12 ` Wu Fengguang
2011-11-10 13:41 ` Takashi Iwai
2011-11-10 13:51 ` Wu Fengguang
2011-11-10 13:53 ` Wu Fengguang
2011-11-10 14:28 ` Takashi Iwai
2011-11-11 2:29 ` Wu Fengguang
2011-11-11 7:40 ` Takashi Iwai
2011-11-11 8:22 ` Wu Fengguang
2011-11-11 8:49 ` Takashi Iwai
2011-11-11 9:24 ` Wu Fengguang
2011-11-11 10:17 ` Takashi Iwai
2011-11-11 11:12 ` Wu Fengguang
2011-11-11 11:23 ` Takashi Iwai
2011-11-11 11:32 ` Wu Fengguang
2011-11-12 2:27 ` Wu Fengguang
2011-11-14 9:45 ` Takashi Iwai
2011-11-14 13:25 ` Wu Fengguang
2011-11-15 17:18 ` Purushothaman, Vijay A
2011-11-10 6:59 ` Wu Fengguang
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