From: Wu Fengguang <fengguang.wu@intel.com>
To: Christopher White <c.white@pulseforce.com>
Cc: "Wang, Zhenyu Z" <zhenyu.z.wang@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Barnes, Jesse" <jesse.barnes@intel.com>,
Jeremy Bush <contractfrombelow@gmail.com>,
"Bossart, Pierre-louis" <pierre-louis.bossart@intel.com>
Subject: Re: [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver
Date: Thu, 10 Nov 2011 21:47:46 +0800 [thread overview]
Message-ID: <20111110134746.GA17079@localhost> (raw)
In-Reply-To: <4EBBD2FC.70601@pulseforce.com>
> > Got the delay - it's 72.986623-72.747632 = 239ms.
> >
> > [ 72.739944] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=0
> > [ 72.742541] HDMI status: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=0
> > [ 72.745082] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=1
> > [ 72.747632] HDMI status: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=1
> > [ 72.794240] [drm:intel_wait_for_vblank], vblank wait timed out
> > [ 72.848099] [drm:intel_wait_for_vblank], vblank wait timed out
> > [ 72.850507] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
> > [ 72.853244] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 42, cursor: 6
> > [ 72.907937] [drm:intel_wait_for_vblank], vblank wait timed out
> > [ 72.960790] [drm:intel_wait_for_vblank], vblank wait timed out
> > [ 72.962757] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
> > [ 72.964880] [drm:ironlake_fdi_link_train], FDI train 1 done.
> > [ 72.968341] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
> > [ 72.970274] [drm:ironlake_fdi_link_train], FDI train 2 done.
> > [ 72.972535] [drm:ironlake_fdi_link_train], FDI train done
> > [ 72.976751] [drm:intel_update_fbc],
> > [ 72.977558] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
> > ==> [ 72.981550] [drm:drm_crtc_helper_set_config], [CONNECTOR:12:HDMI-A-2] set DPMS on
> > [ 72.986623] HDMI: detected monitor RX-V1800 at connection type HDMI
> > [ 72.988260] HDMI: available speakers: FL/FR LFE FC RL/RR RC RLC/RRC
> >
> > I wonder if the DPMS line has anything to do with the delay...
> >
> > Thanks,
> > Fengguang
>
> Nice find! It does seem likely since the ELD read worked right after
> that. Hmm. I am not familiar with the event order for the Intel
> hardware, and what's calling your edid_to_eld code, etc. Is it possible
> to move the EDID read call to after the DPMS state is ready?
I added a dump_stack() at the very beginning of drm_crtc_helper_set_config().
Judging from drm_crtc_helper_set_config()'s comment and the below dmesg, it's
called by user space.
[ 84.470633] Pid: 2893, comm: Xorg Tainted: G W 3.2.0-rc1-eld+ #244
[ 84.472188] Call Trace:
[ 84.472795] [<ffffffff8195dfba>] ? printk+0x41/0x43
[ 84.474011] [<ffffffff8148aa04>] drm_crtc_helper_set_config+0x24/0x852
[ 84.476342] [<ffffffff81493e52>] ? drm_ut_debug_printk+0x57/0x5e
[ 84.477743] [<ffffffff8196052d>] ? mutex_unlock+0xe/0x10
[ 84.479015] [<ffffffff8149a403>] ? drm_mode_object_find+0x61/0x70
[ 84.481326] [<ffffffff8149b632>] drm_mode_setcrtc+0x35d/0x38e
[ 84.482679] [<ffffffff8196052d>] ? mutex_unlock+0xe/0x10
[ 84.483934] [<ffffffff8148efc6>] drm_ioctl+0x2c0/0x38c
[ 84.486033] [<ffffffff8149b2d5>] ? drm_mode_getencoder+0x9b/0x9b
[ 84.487463] [<ffffffff811567b0>] do_vfs_ioctl+0x490/0x4d1
[ 84.489657] [<ffffffff81156838>] sys_ioctl+0x47/0x6b
[ 84.490780] [<ffffffff8149a3cf>] ? drm_mode_object_find+0x2d/0x70
[ 84.492235] [<ffffffff81968a82>] system_call_fastpath+0x16/0x1b
[ 84.495536] [drm:drm_crtc_helper_set_config],
[ 84.496561] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:31] #connectors=1 (x y) (0 0)
[ 84.498323] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[ 84.499958] [drm:drm_mode_debug_printmodeline], Modeline 27:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
[ 84.502454] [drm:drm_mode_debug_printmodeline], Modeline 34:"" 0 27000 720 736 798 858 480 489 495 525 0x0 0xa
[ 84.504672] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:VGA-1] to [CRTC:3]
[ 84.506205] [drm:drm_crtc_helper_set_config], [CONNECTOR:12:HDMI-A-2] to [CRTC:4]
[ 84.507869] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[ 84.509699] [drm:drm_mode_debug_printmodeline], Modeline 34:"" 0 27000 720 736 798 858 480 489 495 525 0x0 0xa
[ 84.511903] [drm:drm_crtc_helper_set_mode], [CRTC:4]
[ 84.521961] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[ 84.564804] [drm:intel_wait_for_vblank], vblank wait timed out
[ 84.603175] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
[ 84.606681] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 42, cursor: 6
[ 84.610472] [drm:intel_update_fbc],
[ 84.611501] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
[ 84.613791] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
[ 84.616531] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
[ 84.617884] [drm:drm_mode_debug_printmodeline], Modeline 34:"" 0 27000 720 736 798 858 480 489 495 525 0x0 0xa
[ 84.622337] [drm:ironlake_crtc_mode_set], disabling CxSR downclocking
[ 84.676554] [drm:intel_wait_for_vblank], vblank wait timed out
[ 84.678981] [drm:ironlake_update_plane], Writing base 00343000 00000000 0 0 4096
[ 84.681384] [drm:intel_update_fbc],
[ 84.733441] [drm:intel_wait_for_vblank], vblank wait timed out
[ 84.735453] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
[ 84.737375] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 42, cursor: 6
[ 84.739922] [drm:drm_crtc_helper_set_mode], [ENCODER:11:TMDS-11] set [MODE:34:]
[ 84.742634] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe B
[ 84.745045] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-2], [ENCODER:11:TMDS-11]
[ 84.746797] [drm:ironlake_write_eld], ELD on pipe B
[ 84.747924] [drm:ironlake_write_eld], Audio directed to unknown port
[ 84.751387] [drm:ironlake_write_eld], ELD size 13
[ 84.752363] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=0
[ 84.753981] HDMI status: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=0
[ 84.756540] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=1
[ 84.759108] HDMI status: Codec=3 Pin=6 Presence_Detect=1 ELD_Valid=1
[ 84.804189] [drm:intel_wait_for_vblank], vblank wait timed out
[ 84.857035] [drm:intel_wait_for_vblank], vblank wait timed out
[ 84.859953] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
[ 84.862637] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 42, cursor: 6
[ 84.916878] [drm:intel_wait_for_vblank], vblank wait timed out
[ 84.969816] [drm:intel_wait_for_vblank], vblank wait timed out
[ 84.972300] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
[ 84.974200] [drm:ironlake_fdi_link_train], FDI train 1 done.
[ 84.975643] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
[ 84.977846] [drm:ironlake_fdi_link_train], FDI train 2 done.
[ 84.980021] [drm:ironlake_fdi_link_train], FDI train done
[ 84.983699] [drm:intel_update_fbc],
[ 84.984994] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[ 84.986531] [drm:drm_crtc_helper_set_config], [CONNECTOR:12:HDMI-A-2] set DPMS on
[ 84.999041] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
[ 85.006426] HDMI: detected monitor RX-V1800 at connection type HDMI
[ 85.008394] HDMI: available speakers: FL/FR LFE FC RL/RR RC RLC/RRC
So audio driver got the ELD right after drm_crtc_helper_set_config() returns.
It shows that ironlake_write_eld() is ultimately called by
drm_crtc_helper_set_config().
Thanks,
Fengguang
next prev parent reply other threads:[~2011-11-10 13:47 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-02 8:14 [PATCH v4] drm/i915: pass ELD to HDMI/DP audio driver Wu Fengguang
2011-09-02 8:29 ` Wu Fengguang
2011-09-03 21:15 ` [PATCH v5] " Wu Fengguang
2011-09-04 10:57 ` James Cloos
2011-09-05 1:19 ` Wu Fengguang
2011-09-04 11:11 ` [Intel-gfx] " Paul Menzel
2011-09-05 1:06 ` Wu Fengguang
2011-09-04 12:08 ` Chris Wilson
2011-09-05 1:14 ` Wu Fengguang
2011-09-05 11:04 ` Chris Wilson
2011-09-05 12:31 ` Wu Fengguang
[not found] ` <4E64C41B.5090309@pulseforce.com>
[not found] ` <20110905124730.GB794@localhost>
[not found] ` <4EA82DBD.9020301@pulseforce.com>
2011-10-27 19:57 ` Christopher White
2011-11-09 6:59 ` Wu Fengguang
2011-11-09 9:00 ` Christopher White
2011-11-09 9:30 ` Christopher White
2011-11-09 13:01 ` Wu Fengguang
[not found] ` <4EA9B6EF.9040305@pulseforce.com>
2011-11-01 11:36 ` Wu Fengguang
2011-11-01 17:00 ` Christopher White
2011-11-02 1:45 ` Wu Fengguang
2011-11-02 6:10 ` Sander Jansen
2011-11-02 7:35 ` Paul Menzel
2011-11-02 11:17 ` Sander Jansen
2011-11-02 14:26 ` Sander Jansen
2011-11-02 8:52 ` Wu Fengguang
2011-11-02 17:41 ` Keith Packard
2011-11-04 0:21 ` Tony Olivo
2011-11-05 0:20 ` Christopher White
2011-11-09 13:12 ` Wu Fengguang
2011-11-10 2:25 ` Christopher White
2011-11-10 3:27 ` Wu Fengguang
2011-11-10 4:10 ` Christopher White
2011-11-10 7:06 ` Wu Fengguang
2011-11-10 7:33 ` Wu Fengguang
2011-11-10 7:55 ` Wu Fengguang
2011-11-10 8:50 ` Wu Fengguang
2011-11-10 8:55 ` Christopher White
2011-11-10 11:00 ` Christopher White
2011-11-10 11:22 ` Takashi Iwai
2011-11-10 11:50 ` Christopher White
2011-11-10 11:53 ` Takashi Iwai
2011-11-10 12:39 ` Christopher White
2011-11-10 13:01 ` Takashi Iwai
2011-11-10 12:56 ` Wu Fengguang
2011-11-10 13:01 ` Christopher White
2011-11-10 13:17 ` Wu Fengguang
2011-11-10 13:34 ` Christopher White
2011-11-10 13:47 ` Wu Fengguang [this message]
2011-11-10 14:12 ` Wu Fengguang
2011-11-10 13:41 ` Takashi Iwai
2011-11-10 13:51 ` Wu Fengguang
2011-11-10 13:53 ` Wu Fengguang
2011-11-10 14:28 ` Takashi Iwai
2011-11-11 2:29 ` Wu Fengguang
2011-11-11 7:40 ` Takashi Iwai
2011-11-11 8:22 ` Wu Fengguang
2011-11-11 8:49 ` Takashi Iwai
2011-11-11 9:24 ` Wu Fengguang
2011-11-11 10:17 ` Takashi Iwai
2011-11-11 11:12 ` Wu Fengguang
2011-11-11 11:23 ` Takashi Iwai
2011-11-11 11:32 ` Wu Fengguang
2011-11-12 2:27 ` Wu Fengguang
2011-11-14 9:45 ` Takashi Iwai
2011-11-14 13:25 ` Wu Fengguang
2011-11-15 17:18 ` Purushothaman, Vijay A
2011-11-10 6:59 ` Wu Fengguang
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