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From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView
Date: Wed, 21 Mar 2012 14:36:47 -0700	[thread overview]
Message-ID: <20120321143647.2ecaeab9@jbarnes-desktop> (raw)
In-Reply-To: <20120321213343.GK9913@phenom.ffwll.local>


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On Wed, 21 Mar 2012 22:33:43 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Mar 21, 2012 at 12:48:40PM -0700, Jesse Barnes wrote:
> > Although internally the MMIO offsets for display regs haven't changed,
> > their visibility through the PCI BAR has been affected by the addition
> > of the Gunit, which occupies the low part of the address space.
> > 
> > Display regs on VLV are offset into the BAR by 0x180000, so we need to
> > add that for any display register offset.
> > 
> > This patch is a hack to do just that, but ultimately we need to split
> > our display and render code more cleanly and add accessor functions for
> > them.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> Gosh, is this horrible ;-) I think a dev_priv->display_mmio_base like
> you've proposed + I915_DISPLAY_READ/WRITE like we already have for the
> ring stuff is much better ...

I nearly got violent with the hw guys when they told me...

But yeah I think a display reg wrapper with an offset is probably the
least offensive.

-- 
Jesse Barnes, Intel Open Source Technology Center

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  reply	other threads:[~2012-03-21 21:36 UTC|newest]

Thread overview: 69+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-21 19:48 [RFC] ValleyView support Jesse Barnes
2012-03-21 19:48 ` [PATCH 01/25] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c Jesse Barnes
2012-03-21 20:40   ` Eugeni Dodonov
2012-03-21 19:48 ` [PATCH 02/25] drm/i915: add debug message when EDID fetch fails Jesse Barnes
2012-03-21 20:44   ` Eugeni Dodonov
2012-03-21 20:53     ` Jesse Barnes
2012-03-22  1:02       ` Ben Widawsky
2012-03-21 19:48 ` [PATCH 03/25] drm/i915: re-order GT IIR bit definitions Jesse Barnes
2012-03-22  1:10   ` Ben Widawsky
2012-03-22 18:40     ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block Jesse Barnes
2012-03-22  1:30   ` Ben Widawsky
2012-03-22 15:45     ` Jesse Barnes
2012-03-22 16:11       ` Ben Widawsky
2012-03-22 17:00         ` Jesse Barnes
2012-03-26 18:52           ` Rodrigo Vivi
2012-03-21 19:48 ` [PATCH 05/25] drm/i915: add DPIO read/write functions for ValleyView Jesse Barnes
2012-03-22  1:39   ` Ben Widawsky
2012-03-21 19:48 ` [PATCH 06/25] drm/i915: add ValleyView registers, stub code, and watermark support Jesse Barnes
2012-03-21 20:52   ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 07/25] drm/i915: split out DPLL update code from i9xx_crtc_mode_set Jesse Barnes
2012-03-21 20:55   ` Daniel Vetter
2012-03-21 21:29     ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 08/25] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes
2012-03-22  1:53   ` Ben Widawsky
2012-03-22 15:03     ` Purushothaman, Vijay A
2012-03-21 19:48 ` [PATCH 09/25] drm/915: program driain latency regs on ValleyView Jesse Barnes
2012-03-21 21:00   ` Daniel Vetter
2012-03-21 21:52     ` Adam Jackson
2012-03-21 19:48 ` [PATCH 10/25] drm/i915: Enable DP panel power sequencing for ValleyView Jesse Barnes
2012-03-22 18:31   ` Ben Widawsky
2012-03-21 19:48 ` [PATCH 11/25] drm/i915: Enable HDMI on ValleyView Jesse Barnes
2012-03-21 21:02   ` Daniel Vetter
2012-03-26  3:21     ` Shobhit Kumar
2012-03-21 19:48 ` [PATCH 12/25] agp/intel: map more registers for use by the GTT code Jesse Barnes
2012-03-21 21:04   ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 13/25] agp/intel: add Valleyview specific PTE entry function Jesse Barnes
2012-03-21 21:07   ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 14/25] agp/intel: always use uncached mappings on VLV Jesse Barnes
2012-03-21 21:09   ` Daniel Vetter
2012-03-21 21:23     ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 15/25] drm/i915: add ValleyView specific CRT detect function Jesse Barnes
2012-03-21 19:48 ` [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions Jesse Barnes
2012-03-21 21:11   ` Daniel Vetter
2012-03-21 21:32     ` Jesse Barnes
2012-03-21 21:55       ` Adam Jackson
2012-03-21 22:11         ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 17/25] drm/i915: ValleyView cacheability is different Jesse Barnes
2012-03-21 21:19   ` Daniel Vetter
2012-03-21 21:35     ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 18/25] drm/i915: ValleyView IRQ support Jesse Barnes
2012-03-21 19:48 ` [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView Jesse Barnes
2012-03-21 21:33   ` Daniel Vetter
2012-03-21 21:36     ` Jesse Barnes [this message]
2012-03-22 21:13       ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 20/25] drm/i915: check for disabled interrupts " Jesse Barnes
2012-03-21 19:48 ` [PATCH 21/25] drm/i915: add HDMI and DP port enumeration " Jesse Barnes
2012-03-21 19:48 ` [PATCH 22/25] drm/i915: remove some unneeded debug messages Jesse Barnes
2012-03-21 21:36   ` Daniel Vetter
2012-03-21 21:39     ` Daniel Vetter
2012-03-21 21:55     ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 23/25] drm/i915: add ValleyView clock gating init Jesse Barnes
2012-03-21 21:40   ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 24/25] drm/i915: add has_turbo bit to driver info struct Jesse Barnes
2012-03-21 21:43   ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 25/25] drm/i915: don't write ring regs until they're set up Jesse Barnes
2012-03-21 21:46   ` Daniel Vetter
2012-03-21 21:56     ` Jesse Barnes
2012-03-21 21:54 ` [RFC] ValleyView support Daniel Vetter

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