From: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/4] drm/i915: force CPU eDP onto pipe 3 on IVB
Date: Wed, 11 Apr 2012 09:53:04 -0700 [thread overview]
Message-ID: <20120411095304.01c5e320@jbarnes-desktop> (raw)
In-Reply-To: <1334161416-11775-4-git-send-email-jbarnes@virtuousgeek.org>
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On Wed, 11 Apr 2012 09:23:36 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> This is a hack to make sure CPU eDP mode sets avoid allocating a PCH PLL.
Ignore this one, it's too ugly to live. I'll put something better
together now...
--
Jesse Barnes, Intel Open Source Technology Center
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prev parent reply other threads:[~2012-04-11 16:53 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-11 16:23 [PATCH 1/4] drm/i915: disable turbo on ValleyView for now Jesse Barnes
2012-04-11 16:23 ` [PATCH 2/4] drm/i915: IBX+ doesn't have separate vsync/hsync controls on the VGA DAC Jesse Barnes
2012-04-11 18:36 ` Daniel Vetter
2012-04-17 22:06 ` Jesse Barnes
2012-04-17 22:18 ` Chris Wilson
2012-04-18 7:36 ` Daniel Vetter
2012-04-11 16:23 ` [PATCH 3/4] drm/i915: allow PCH PWM override on IVB Jesse Barnes
2012-04-11 16:23 ` [PATCH 4/4] drm/i915: force CPU eDP onto pipe 3 " Jesse Barnes
2012-04-11 16:53 ` Jesse Barnes [this message]
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