Re: [PATCH 1/2] drm/i915: Don't set a MBZ bit in gen2 MI_FLUSH

[Daniel Vetter <daniel@ffwll.ch>]

On Mon, Apr 16, 2012 at 09:53:16AM +0100, Chris Wilson wrote:
> On gen2, MI_EXE_FLUSH is actually an AGP flush bit and is documented as
> being must-be-zero. So obey the documentation, and separate the gen2
> flush into its own little routine.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

I've read up on docs, and additionally on gen3 bit1 (our EXE_FLUSH) is
marked mbz. The instruction/state cache invalidate flush seems to only
exist on gen4+. So I guess we need this new flush function also on gen3.
-Daniel
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c |   30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8e632a5..9b89d4a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -53,6 +53,32 @@ static inline int ring_space(struct intel_ring_buffer *ring)
>  }
>  
>  static int
> +gen2_render_ring_flush(struct intel_ring_buffer *ring,
> +		       u32	invalidate_domains,
> +		       u32	flush_domains)
> +{
> +	u32 cmd;
> +	int ret;
> +
> +	cmd = MI_FLUSH;
> +	if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
> +		cmd |= MI_NO_WRITE_FLUSH;
> +
> +	if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
> +		cmd |= MI_READ_FLUSH;
> +
> +	ret = intel_ring_begin(ring, 2);
> +	if (ret)
> +		return ret;
> +
> +	intel_ring_emit(ring, cmd);
> +	intel_ring_emit(ring, MI_NOOP);
> +	intel_ring_advance(ring);
> +
> +	return 0;
> +}
> +
> +static int
>  render_ring_flush(struct intel_ring_buffer *ring,
>  		  u32	invalidate_domains,
>  		  u32	flush_domains)
> @@ -1296,6 +1322,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
>  	} else {
>  		ring->add_request = i9xx_add_request;
>  		ring->flush = render_ring_flush;
> +		if (INTEL_INFO(dev)->gen == 2)
> +			ring->flush = gen2_render_ring_flush;
>  		ring->get_seqno = ring_get_seqno;
>  		ring->irq_get = i9xx_ring_get_irq;
>  		ring->irq_put = i9xx_ring_put_irq;
> @@ -1341,6 +1369,8 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
>  	 * the special gen5 functions. */
>  	ring->add_request = i9xx_add_request;
>  	ring->flush = render_ring_flush;
> +	if (INTEL_INFO(dev)->gen == 2)
> +		ring->flush = gen2_render_ring_flush;
>  	ring->get_seqno = ring_get_seqno;
>  	ring->irq_get = i9xx_ring_get_irq;
>  	ring->irq_put = i9xx_ring_put_irq;
> -- 
> 1.7.10
> 
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-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48