[PATCH 1/2] drm/i915: Don't set a MBZ bit in gen2 MI_FLUSH

[PATCH 1/2] drm/i915: Don't set a MBZ bit in gen2 MI_FLUSH

[Chris Wilson]

On gen2, MI_EXE_FLUSH is actually an AGP flush bit and is documented as
being must-be-zero. So obey the documentation, and separate the gen2
flush into its own little routine.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |   30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8e632a5..9b89d4a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -53,6 +53,32 @@ static inline int ring_space(struct intel_ring_buffer *ring)
 }
 
 static int
+gen2_render_ring_flush(struct intel_ring_buffer *ring,
+		       u32	invalidate_domains,
+		       u32	flush_domains)
+{
+	u32 cmd;
+	int ret;
+
+	cmd = MI_FLUSH;
+	if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
+		cmd |= MI_NO_WRITE_FLUSH;
+
+	if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
+		cmd |= MI_READ_FLUSH;
+
+	ret = intel_ring_begin(ring, 2);
+	if (ret)
+		return ret;
+
+	intel_ring_emit(ring, cmd);
+	intel_ring_emit(ring, MI_NOOP);
+	intel_ring_advance(ring);
+
+	return 0;
+}
+
+static int
 render_ring_flush(struct intel_ring_buffer *ring,
 		  u32	invalidate_domains,
 		  u32	flush_domains)
@@ -1296,6 +1322,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 	} else {
 		ring->add_request = i9xx_add_request;
 		ring->flush = render_ring_flush;
+		if (INTEL_INFO(dev)->gen == 2)
+			ring->flush = gen2_render_ring_flush;
 		ring->get_seqno = ring_get_seqno;
 		ring->irq_get = i9xx_ring_get_irq;
 		ring->irq_put = i9xx_ring_put_irq;
@@ -1341,6 +1369,8 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
 	 * the special gen5 functions. */
 	ring->add_request = i9xx_add_request;
 	ring->flush = render_ring_flush;
+	if (INTEL_INFO(dev)->gen == 2)
+		ring->flush = gen2_render_ring_flush;
 	ring->get_seqno = ring_get_seqno;
 	ring->irq_get = i9xx_ring_get_irq;
 	ring->irq_put = i9xx_ring_put_irq;
-- 
1.7.10

[PATCH 2/2] drm/i915: Force TLB invalidation for erratum on 830/845 BLT

[Chris Wilson]

On 830/845, the BLT unit invalidates the wrong PTE in its TLB after the
GATT is updated. A simple solution is then to always invalidate the TLB
of the BLT prior to each execbuffer.

This does appear to improve the stability slighty, but I am still seeing
spurious GPU deaths under memory pressure.

References: https://bugs.freedesktop.org/show_bug.cgi?id=26345
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 60fc132..b825c06 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -883,6 +883,13 @@ i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
 	int ret;
 
 	memset(&cd, 0, sizeof(cd));
+
+	/* We need to invalidate the BLT's prefetched entries after
+	 * updating the GATT (as the hardware invalidates the wrong PTEs).
+	 */
+	if (IS_I830(ring->dev) || IS_845G(ring->dev))
+		cd.invalidate_domains = I915_GEM_DOMAIN_RENDER;
+
 	list_for_each_entry(obj, objects, exec_list)
 		i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
 
-- 
1.7.10

Re: [PATCH 2/2] drm/i915: Force TLB invalidation for erratum on 830/845 BLT

[Daniel Vetter]

On Mon, Apr 16, 2012 at 09:53:17AM +0100, Chris Wilson wrote:
> On 830/845, the BLT unit invalidates the wrong PTE in its TLB after the
> GATT is updated. A simple solution is then to always invalidate the TLB
> of the BLT prior to each execbuffer.
> 
> This does appear to improve the stability slighty, but I am still seeing
> spurious GPU deaths under memory pressure.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=26345
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

In the light of the eventual gpu domain tracking removal, can't we just
unconditionally set these bit in the new gen2_render_ring_flush function?
Or is it indeed to expensive?
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |    7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 60fc132..b825c06 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -883,6 +883,13 @@ i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
>  	int ret;
>  
>  	memset(&cd, 0, sizeof(cd));
> +
> +	/* We need to invalidate the BLT's prefetched entries after
> +	 * updating the GATT (as the hardware invalidates the wrong PTEs).
> +	 */
> +	if (IS_I830(ring->dev) || IS_845G(ring->dev))
> +		cd.invalidate_domains = I915_GEM_DOMAIN_RENDER;
> +
>  	list_for_each_entry(obj, objects, exec_list)
>  		i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
>  
> -- 
> 1.7.10
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 2/2] drm/i915: Force TLB invalidation for erratum on 830/845 BLT

[Chris Wilson]

On Mon, 16 Apr 2012 11:02:13 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Apr 16, 2012 at 09:53:17AM +0100, Chris Wilson wrote:
> > On 830/845, the BLT unit invalidates the wrong PTE in its TLB after the
> > GATT is updated. A simple solution is then to always invalidate the TLB
> > of the BLT prior to each execbuffer.
> > 
> > This does appear to improve the stability slighty, but I am still seeing
> > spurious GPU deaths under memory pressure.
> > 
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=26345
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> 
> In the light of the eventual gpu domain tracking removal, can't we just
> unconditionally set these bit in the new gen2_render_ring_flush function?
> Or is it indeed to expensive?

Of course you can, I have done any measurements to see if any harm is
going to come from extra flushes between batches, as we invariably have
to flush anyway.

Just remember that invalidate+flush 2 step when removing the flush tracking...
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 1/2] drm/i915: Don't set a MBZ bit in gen2 MI_FLUSH

[Daniel Vetter]

On Mon, Apr 16, 2012 at 09:53:16AM +0100, Chris Wilson wrote:
> On gen2, MI_EXE_FLUSH is actually an AGP flush bit and is documented as
> being must-be-zero. So obey the documentation, and separate the gen2
> flush into its own little routine.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

I've read up on docs, and additionally on gen3 bit1 (our EXE_FLUSH) is
marked mbz. The instruction/state cache invalidate flush seems to only
exist on gen4+. So I guess we need this new flush function also on gen3.
-Daniel
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c |   30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8e632a5..9b89d4a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -53,6 +53,32 @@ static inline int ring_space(struct intel_ring_buffer *ring)
>  }
>  
>  static int
> +gen2_render_ring_flush(struct intel_ring_buffer *ring,
> +		       u32	invalidate_domains,
> +		       u32	flush_domains)
> +{
> +	u32 cmd;
> +	int ret;
> +
> +	cmd = MI_FLUSH;
> +	if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
> +		cmd |= MI_NO_WRITE_FLUSH;
> +
> +	if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
> +		cmd |= MI_READ_FLUSH;
> +
> +	ret = intel_ring_begin(ring, 2);
> +	if (ret)
> +		return ret;
> +
> +	intel_ring_emit(ring, cmd);
> +	intel_ring_emit(ring, MI_NOOP);
> +	intel_ring_advance(ring);
> +
> +	return 0;
> +}
> +
> +static int
>  render_ring_flush(struct intel_ring_buffer *ring,
>  		  u32	invalidate_domains,
>  		  u32	flush_domains)
> @@ -1296,6 +1322,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
>  	} else {
>  		ring->add_request = i9xx_add_request;
>  		ring->flush = render_ring_flush;
> +		if (INTEL_INFO(dev)->gen == 2)
> +			ring->flush = gen2_render_ring_flush;
>  		ring->get_seqno = ring_get_seqno;
>  		ring->irq_get = i9xx_ring_get_irq;
>  		ring->irq_put = i9xx_ring_put_irq;
> @@ -1341,6 +1369,8 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
>  	 * the special gen5 functions. */
>  	ring->add_request = i9xx_add_request;
>  	ring->flush = render_ring_flush;
> +	if (INTEL_INFO(dev)->gen == 2)
> +		ring->flush = gen2_render_ring_flush;
>  	ring->get_seqno = ring_get_seqno;
>  	ring->irq_get = i9xx_ring_get_irq;
>  	ring->irq_put = i9xx_ring_put_irq;
> -- 
> 1.7.10
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

[PATCH] drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH

[Chris Wilson]

On gen2 and gen4, MI_EXE_FLUSH is actually an AGP flush bit and is
documented as being must-be-zero. So obey the documentation, and separate
the gen2 flush into its own little routine and share with gen3.

This means that we can rename the existing render_ring_flush() to
reflect the generation from which it first applies and remove the code
for handling earlier generations from it.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |   53 ++++++++++++++++++++++---------
 1 file changed, 38 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 04330e3..9c6a937 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -53,9 +53,35 @@ static inline int ring_space(struct intel_ring_buffer *ring)
 }
 
 static int
-render_ring_flush(struct intel_ring_buffer *ring,
-		  u32	invalidate_domains,
-		  u32	flush_domains)
+gen2_render_ring_flush(struct intel_ring_buffer *ring,
+		       u32	invalidate_domains,
+		       u32	flush_domains)
+{
+	u32 cmd;
+	int ret;
+
+	cmd = MI_FLUSH;
+	if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
+		cmd |= MI_NO_WRITE_FLUSH;
+
+	if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
+		cmd |= MI_READ_FLUSH;
+
+	ret = intel_ring_begin(ring, 2);
+	if (ret)
+		return ret;
+
+	intel_ring_emit(ring, cmd);
+	intel_ring_emit(ring, MI_NOOP);
+	intel_ring_advance(ring);
+
+	return 0;
+}
+
+static int
+gen4_render_ring_flush(struct intel_ring_buffer *ring,
+		       u32	invalidate_domains,
+		       u32	flush_domains)
 {
 	struct drm_device *dev = ring->dev;
 	u32 cmd;
@@ -90,17 +116,8 @@ render_ring_flush(struct intel_ring_buffer *ring,
 	 */
 
 	cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
-	if ((invalidate_domains|flush_domains) &
-	    I915_GEM_DOMAIN_RENDER)
+	if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 		cmd &= ~MI_NO_WRITE_FLUSH;
-	if (INTEL_INFO(dev)->gen < 4) {
-		/*
-		 * On the 965, the sampler cache always gets flushed
-		 * and this bit is reserved.
-		 */
-		if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
-			cmd |= MI_READ_FLUSH;
-	}
 	if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 		cmd |= MI_EXE_FLUSH;
 
@@ -1295,7 +1312,10 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 		ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
 	} else {
 		ring->add_request = i9xx_add_request;
-		ring->flush = render_ring_flush;
+		if (INTEL_INFO(dev)->gen < 4)
+			ring->flush = gen2_render_ring_flush;
+		else
+			ring->flush = gen4_render_ring_flush;
 		ring->get_seqno = ring_get_seqno;
 		ring->irq_get = i9xx_ring_get_irq;
 		ring->irq_put = i9xx_ring_put_irq;
@@ -1340,7 +1360,10 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
 	 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
 	 * the special gen5 functions. */
 	ring->add_request = i9xx_add_request;
-	ring->flush = render_ring_flush;
+	if (INTEL_INFO(dev)->gen < 4)
+		ring->flush = gen2_render_ring_flush;
+	else
+		ring->flush = gen4_render_ring_flush;
 	ring->get_seqno = ring_get_seqno;
 	ring->irq_get = i9xx_ring_get_irq;
 	ring->irq_put = i9xx_ring_put_irq;
-- 
1.7.10

Re: [PATCH] drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH

[Daniel Vetter]

On Wed, Apr 18, 2012 at 10:25:05AM +0100, Chris Wilson wrote:
> On gen2 and gen4, MI_EXE_FLUSH is actually an AGP flush bit and is
> documented as being must-be-zero. So obey the documentation, and separate
> the gen2 flush into its own little routine and share with gen3.

MI_EXE_FLUSH on gen4 is actually to invalidate state/instruction caches.

> This means that we can rename the existing render_ring_flush() to
> reflect the generation from which it first applies and remove the code
> for handling earlier generations from it.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

... and it doesn't compile too well here, too ;-)
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c |   53 ++++++++++++++++++++++---------
>  1 file changed, 38 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 04330e3..9c6a937 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -53,9 +53,35 @@ static inline int ring_space(struct intel_ring_buffer *ring)
>  }
>  
>  static int
> -render_ring_flush(struct intel_ring_buffer *ring,
> -		  u32	invalidate_domains,
> -		  u32	flush_domains)
> +gen2_render_ring_flush(struct intel_ring_buffer *ring,
> +		       u32	invalidate_domains,
> +		       u32	flush_domains)
> +{
> +	u32 cmd;
> +	int ret;
> +
> +	cmd = MI_FLUSH;
> +	if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
> +		cmd |= MI_NO_WRITE_FLUSH;
> +
> +	if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
> +		cmd |= MI_READ_FLUSH;
> +
> +	ret = intel_ring_begin(ring, 2);
> +	if (ret)
> +		return ret;
> +
> +	intel_ring_emit(ring, cmd);
> +	intel_ring_emit(ring, MI_NOOP);
> +	intel_ring_advance(ring);
> +
> +	return 0;
> +}
> +
> +static int
> +gen4_render_ring_flush(struct intel_ring_buffer *ring,
> +		       u32	invalidate_domains,
> +		       u32	flush_domains)
>  {
>  	struct drm_device *dev = ring->dev;
>  	u32 cmd;
> @@ -90,17 +116,8 @@ render_ring_flush(struct intel_ring_buffer *ring,
>  	 */
>  
>  	cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
> -	if ((invalidate_domains|flush_domains) &
> -	    I915_GEM_DOMAIN_RENDER)
> +	if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
>  		cmd &= ~MI_NO_WRITE_FLUSH;
> -	if (INTEL_INFO(dev)->gen < 4) {
> -		/*
> -		 * On the 965, the sampler cache always gets flushed
> -		 * and this bit is reserved.
> -		 */
> -		if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
> -			cmd |= MI_READ_FLUSH;
> -	}
>  	if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
>  		cmd |= MI_EXE_FLUSH;
>  
> @@ -1295,7 +1312,10 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
>  		ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
>  	} else {
>  		ring->add_request = i9xx_add_request;
> -		ring->flush = render_ring_flush;
> +		if (INTEL_INFO(dev)->gen < 4)
> +			ring->flush = gen2_render_ring_flush;
> +		else
> +			ring->flush = gen4_render_ring_flush;
>  		ring->get_seqno = ring_get_seqno;
>  		ring->irq_get = i9xx_ring_get_irq;
>  		ring->irq_put = i9xx_ring_put_irq;
> @@ -1340,7 +1360,10 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
>  	 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
>  	 * the special gen5 functions. */
>  	ring->add_request = i9xx_add_request;
> -	ring->flush = render_ring_flush;
> +	if (INTEL_INFO(dev)->gen < 4)
> +		ring->flush = gen2_render_ring_flush;
> +	else
> +		ring->flush = gen4_render_ring_flush;
>  	ring->get_seqno = ring_get_seqno;
>  	ring->irq_get = i9xx_ring_get_irq;
>  	ring->irq_put = i9xx_ring_put_irq;
> -- 
> 1.7.10
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

[PATCH] drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH

[Chris Wilson]

On gen2 MI_EXE_FLUSH is actually an AGP flush bit and on gen3 marked as
reserved.  On both it is documented as being must-be-zero. So obey the
documentation, and separate the gen2 flush into its own little routine
and share with gen3.

This means that we can rename the existing render_ring_flush() to
reflect the generation from which it first applies and remove the code
for handling earlier generations from it.

v2: Applies to gen3 as well
v3: Make it compile and improve the commit message.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |   55 ++++++++++++++++++++++---------
 1 file changed, 39 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 04330e3..57fe20a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -53,9 +53,35 @@ static inline int ring_space(struct intel_ring_buffer *ring)
 }
 
 static int
-render_ring_flush(struct intel_ring_buffer *ring,
-		  u32	invalidate_domains,
-		  u32	flush_domains)
+gen2_render_ring_flush(struct intel_ring_buffer *ring,
+		       u32	invalidate_domains,
+		       u32	flush_domains)
+{
+	u32 cmd;
+	int ret;
+
+	cmd = MI_FLUSH;
+	if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
+		cmd |= MI_NO_WRITE_FLUSH;
+
+	if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
+		cmd |= MI_READ_FLUSH;
+
+	ret = intel_ring_begin(ring, 2);
+	if (ret)
+		return ret;
+
+	intel_ring_emit(ring, cmd);
+	intel_ring_emit(ring, MI_NOOP);
+	intel_ring_advance(ring);
+
+	return 0;
+}
+
+static int
+gen4_render_ring_flush(struct intel_ring_buffer *ring,
+		       u32	invalidate_domains,
+		       u32	flush_domains)
 {
 	struct drm_device *dev = ring->dev;
 	u32 cmd;
@@ -90,17 +116,8 @@ render_ring_flush(struct intel_ring_buffer *ring,
 	 */
 
 	cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
-	if ((invalidate_domains|flush_domains) &
-	    I915_GEM_DOMAIN_RENDER)
+	if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 		cmd &= ~MI_NO_WRITE_FLUSH;
-	if (INTEL_INFO(dev)->gen < 4) {
-		/*
-		 * On the 965, the sampler cache always gets flushed
-		 * and this bit is reserved.
-		 */
-		if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
-			cmd |= MI_READ_FLUSH;
-	}
 	if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 		cmd |= MI_EXE_FLUSH;
 
@@ -1288,14 +1305,17 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 		ring->signal_mbox[1] = GEN6_BRSYNC;
 	} else if (IS_GEN5(dev)) {
 		ring->add_request = pc_render_add_request;
-		ring->flush = render_ring_flush;
+		ring->flush = gen4_render_ring_flush;
 		ring->get_seqno = pc_render_get_seqno;
 		ring->irq_get = gen5_ring_get_irq;
 		ring->irq_put = gen5_ring_put_irq;
 		ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
 	} else {
 		ring->add_request = i9xx_add_request;
-		ring->flush = render_ring_flush;
+		if (INTEL_INFO(dev)->gen < 4)
+			ring->flush = gen2_render_ring_flush;
+		else
+			ring->flush = gen4_render_ring_flush;
 		ring->get_seqno = ring_get_seqno;
 		ring->irq_get = i9xx_ring_get_irq;
 		ring->irq_put = i9xx_ring_put_irq;
@@ -1340,7 +1360,10 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
 	 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
 	 * the special gen5 functions. */
 	ring->add_request = i9xx_add_request;
-	ring->flush = render_ring_flush;
+	if (INTEL_INFO(dev)->gen < 4)
+		ring->flush = gen2_render_ring_flush;
+	else
+		ring->flush = gen4_render_ring_flush;
 	ring->get_seqno = ring_get_seqno;
 	ring->irq_get = i9xx_ring_get_irq;
 	ring->irq_put = i9xx_ring_put_irq;
-- 
1.7.10

Re: [PATCH] drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH

[Daniel Vetter]

On Wed, Apr 18, 2012 at 11:12:11AM +0100, Chris Wilson wrote:
> On gen2 MI_EXE_FLUSH is actually an AGP flush bit and on gen3 marked as
> reserved.  On both it is documented as being must-be-zero. So obey the
> documentation, and separate the gen2 flush into its own little routine
> and share with gen3.
> 
> This means that we can rename the existing render_ring_flush() to
> reflect the generation from which it first applies and remove the code
> for handling earlier generations from it.
> 
> v2: Applies to gen3 as well
> v3: Make it compile and improve the commit message.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48