From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH
Date: Wed, 18 Apr 2012 12:40:37 +0200 [thread overview]
Message-ID: <20120418104037.GN5315@phenom.ffwll.local> (raw)
In-Reply-To: <1334743931-31100-1-git-send-email-chris@chris-wilson.co.uk>
On Wed, Apr 18, 2012 at 11:12:11AM +0100, Chris Wilson wrote:
> On gen2 MI_EXE_FLUSH is actually an AGP flush bit and on gen3 marked as
> reserved. On both it is documented as being must-be-zero. So obey the
> documentation, and separate the gen2 flush into its own little routine
> and share with gen3.
>
> This means that we can rename the existing render_ring_flush() to
> reflect the generation from which it first applies and remove the code
> for handling earlier generations from it.
>
> v2: Applies to gen3 as well
> v3: Make it compile and improve the commit message.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
prev parent reply other threads:[~2012-04-18 10:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-16 8:53 [PATCH 1/2] drm/i915: Don't set a MBZ bit in gen2 MI_FLUSH Chris Wilson
2012-04-16 8:53 ` [PATCH 2/2] drm/i915: Force TLB invalidation for erratum on 830/845 BLT Chris Wilson
2012-04-16 9:02 ` Daniel Vetter
2012-04-16 9:12 ` Chris Wilson
2012-04-18 9:18 ` [PATCH 1/2] drm/i915: Don't set a MBZ bit in gen2 MI_FLUSH Daniel Vetter
2012-04-18 9:25 ` [PATCH] drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH Chris Wilson
2012-04-18 9:41 ` Daniel Vetter
2012-04-18 10:12 ` Chris Wilson
2012-04-18 10:40 ` Daniel Vetter [this message]
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