From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 07/14] agp/intel: allow cacheable and GDFT PTEs on ValleyView
Date: Wed, 20 Jun 2012 08:35:08 -0700 [thread overview]
Message-ID: <20120620083508.4f3e150b@jbarnes-desktop> (raw)
In-Reply-To: <20120620125717.GG7170@phenom.ffwll.local>
On Wed, 20 Jun 2012 14:57:17 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:
> On Fri, Jun 15, 2012 at 11:55:19AM -0700, Jesse Barnes wrote:
> > The PTE format is similar to SNB, but we don't support an MLC and don't
> > need chipset flushing.
> >
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> I have my questions whether this is right, given that MLC died for snb &
> ivb, that ivb has grown a L3$ cache instead (which vlv seems to have, too)
> and that the LLC bit here isn't actually LLC, but just means 'snoop cpu
> caches'.
Yeah I dropped the MLC part and didn't rename the LLC bit which might
be a little confusing, but afaict from the VLV docs this is correct and
actually works here (i.e. my last "cacheability is different" patch is
unneeded).
--
Jesse Barnes, Intel Open Source Technology Center
next prev parent reply other threads:[~2012-06-20 15:41 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-15 18:55 [PATCH 01/14] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes
2012-06-15 18:55 ` [PATCH 02/14] drm/i915: Enable DP panel power sequencing for ValleyView Jesse Barnes
2012-06-20 12:50 ` Daniel Vetter
2012-06-20 15:33 ` Jesse Barnes
2012-06-15 18:55 ` [PATCH 03/14] drm/i915: add ValleyView specific CRT detect function Jesse Barnes
2012-06-15 18:55 ` [PATCH 04/14] drm/i915: add HDMI and DP port enumeration on ValleyView Jesse Barnes
2012-06-15 18:55 ` [PATCH 05/14] drm/i915: access VLV regs through read/write switch Jesse Barnes
2012-06-15 18:55 ` [PATCH 06/14] drm/i915: VLV VGA port only handles on & off, like PCH VGA Jesse Barnes
2012-06-15 18:55 ` [PATCH 07/14] agp/intel: allow cacheable and GDFT PTEs on ValleyView Jesse Barnes
2012-06-20 12:57 ` Daniel Vetter
2012-06-20 15:35 ` Jesse Barnes [this message]
2012-06-15 18:55 ` [PATCH 08/14] drm/i915: support page flipping " Jesse Barnes
2012-06-15 18:55 ` [PATCH 09/14] drm/i915: enable display messages to GT " Jesse Barnes
2012-06-20 13:12 ` Daniel Vetter
2012-06-15 18:55 ` [PATCH 10/14] agp/intel: use correct GTT offset on VLV Jesse Barnes
2012-06-15 18:55 ` [PATCH 11/14] drm/i915: don't enable PPGTT on VLV yet Jesse Barnes
2012-06-15 18:55 ` [PATCH 12/14] drm/i915: don't account for shared interrupts on VLV Jesse Barnes
2012-06-20 13:18 ` Daniel Vetter
[not found] ` <15842_1340198260_4FE1CD73_15842_15371_1_20120620131831.GJ7170@phenom.ffwll.local>
2012-06-20 17:41 ` [PATCH v4] Added support for the ns2501 DVO Thomas Richter
2012-06-20 18:03 ` Daniel Vetter
2012-06-20 22:35 ` Paul Menzel
2012-06-15 18:55 ` [PATCH 13/14] drm/i915: fix initial IRQ masking on VLV Jesse Barnes
2012-06-20 13:12 ` Daniel Vetter
2012-06-15 18:55 ` [PATCH 14/14] drm/i915: bind driver to ValleyView chipsets Jesse Barnes
2012-06-20 13:20 ` Daniel Vetter
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