From: Daniel Vetter <daniel@ffwll.ch>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 12/14] drm/i915: don't account for shared interrupts on VLV
Date: Wed, 20 Jun 2012 15:18:31 +0200 [thread overview]
Message-ID: <20120620131831.GJ7170@phenom.ffwll.local> (raw)
In-Reply-To: <1339786526-16747-12-git-send-email-jbarnes@virtuousgeek.org>
On Fri, Jun 15, 2012 at 11:55:24AM -0700, Jesse Barnes wrote:
> Only count interrupts we find came from the GPU.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
We have this on every generation's irq handler this way. I guess we should
either fix this everywhere or not bother with it. Dropped for now.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_irq.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 453ea7c..36732f7 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -515,8 +515,6 @@ static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
> u32 pipe_stats[I915_MAX_PIPES];
> bool blc_event;
>
> - atomic_inc(&dev_priv->irq_received);
> -
> while (true) {
> iir = I915_READ(VLV_IIR);
> gt_iir = I915_READ(GTIIR);
> @@ -525,6 +523,8 @@ static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
> if (gt_iir == 0 && pm_iir == 0 && iir == 0)
> goto out;
>
> + atomic_inc(&dev_priv->irq_received);
> +
> ret = IRQ_HANDLED;
>
> snb_gt_irq_handler(dev, dev_priv, gt_iir);
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
next prev parent reply other threads:[~2012-06-20 13:16 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-15 18:55 [PATCH 01/14] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes
2012-06-15 18:55 ` [PATCH 02/14] drm/i915: Enable DP panel power sequencing for ValleyView Jesse Barnes
2012-06-20 12:50 ` Daniel Vetter
2012-06-20 15:33 ` Jesse Barnes
2012-06-15 18:55 ` [PATCH 03/14] drm/i915: add ValleyView specific CRT detect function Jesse Barnes
2012-06-15 18:55 ` [PATCH 04/14] drm/i915: add HDMI and DP port enumeration on ValleyView Jesse Barnes
2012-06-15 18:55 ` [PATCH 05/14] drm/i915: access VLV regs through read/write switch Jesse Barnes
2012-06-15 18:55 ` [PATCH 06/14] drm/i915: VLV VGA port only handles on & off, like PCH VGA Jesse Barnes
2012-06-15 18:55 ` [PATCH 07/14] agp/intel: allow cacheable and GDFT PTEs on ValleyView Jesse Barnes
2012-06-20 12:57 ` Daniel Vetter
2012-06-20 15:35 ` Jesse Barnes
2012-06-15 18:55 ` [PATCH 08/14] drm/i915: support page flipping " Jesse Barnes
2012-06-15 18:55 ` [PATCH 09/14] drm/i915: enable display messages to GT " Jesse Barnes
2012-06-20 13:12 ` Daniel Vetter
2012-06-15 18:55 ` [PATCH 10/14] agp/intel: use correct GTT offset on VLV Jesse Barnes
2012-06-15 18:55 ` [PATCH 11/14] drm/i915: don't enable PPGTT on VLV yet Jesse Barnes
2012-06-15 18:55 ` [PATCH 12/14] drm/i915: don't account for shared interrupts on VLV Jesse Barnes
2012-06-20 13:18 ` Daniel Vetter [this message]
[not found] ` <15842_1340198260_4FE1CD73_15842_15371_1_20120620131831.GJ7170@phenom.ffwll.local>
2012-06-20 17:41 ` [PATCH v4] Added support for the ns2501 DVO Thomas Richter
2012-06-20 18:03 ` Daniel Vetter
2012-06-20 22:35 ` Paul Menzel
2012-06-15 18:55 ` [PATCH 13/14] drm/i915: fix initial IRQ masking on VLV Jesse Barnes
2012-06-20 13:12 ` Daniel Vetter
2012-06-15 18:55 ` [PATCH 14/14] drm/i915: bind driver to ValleyView chipsets Jesse Barnes
2012-06-20 13:20 ` Daniel Vetter
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