From: Ben Widawsky <ben@bwidawsk.net>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op
Date: Tue, 2 Oct 2012 17:14:53 -0700 [thread overview]
Message-ID: <20121002171453.3a201ac1@bwidawsk.net> (raw)
In-Reply-To: <1349217826-2538-11-git-send-email-jbarnes@virtuousgeek.org>
s/MI_FLUSH_SW/MI_FLUSH_DW/
On Tue, 2 Oct 2012 17:43:44 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> So store into the scratch space of the HWS to make sure the invalidate
> occurs.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++++++++++++++++++----
> 2 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3ceeb68..d98c989 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -241,8 +241,10 @@
> */
> #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
> #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
> -#define MI_INVALIDATE_TLB (1<<18)
> -#define MI_INVALIDATE_BSD (1<<7)
> +#define MI_FLUSH_DW_STORE_INDEX (1<<21)
> +#define MI_INVALIDATE_TLB (1<<18)
> +#define MI_FLUSH_DW_OP_STOREDW (1<<14)
> +#define MI_INVALIDATE_BSD (1<<7)
> #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
> #define MI_BATCH_NON_SECURE (1)
> #define MI_BATCH_NON_SECURE_I965 (1<<8)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1718c54..d3b7129 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1395,10 +1395,17 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
> return ret;
>
> cmd = MI_FLUSH_DW;
> + /*
> + * Bspec vol 1c.5 - video engine command streamer:
> + * "If ENABLED, all TLBs will be invalidated once the flush
> + * operation is complete. This bit is only valid when the
> + * Post-Sync Operation field is a value of 1h or 3h."
> + */
> if (invalidate & I915_GEM_GPU_DOMAINS)
> - cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
> + cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
> + MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
> intel_ring_emit(ring, cmd);
> - intel_ring_emit(ring, 0);
> + intel_ring_emit(ring, I915_GEM_SCRATCH_INDEX << 3);
> intel_ring_emit(ring, 0);
> intel_ring_emit(ring, MI_NOOP);
> intel_ring_advance(ring);
> @@ -1436,10 +1443,17 @@ static int blt_ring_flush(struct intel_ring_buffer *ring,
> return ret;
>
> cmd = MI_FLUSH_DW;
> + /*
> + * Bspec vol 1c.3 - blitter engine command streamer:
> + * "If ENABLED, all TLBs will be invalidated once the flush
> + * operation is complete. This bit is only valid when the
> + * Post-Sync Operation field is a value of 1h or 3h."
> + */
> if (invalidate & I915_GEM_DOMAIN_RENDER)
> - cmd |= MI_INVALIDATE_TLB;
> + cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
> + MI_FLUSH_DW_OP_STOREDW;
> intel_ring_emit(ring, cmd);
> - intel_ring_emit(ring, 0);
> + intel_ring_emit(ring, I915_GEM_SCRATCH_INDEX << 3);
> intel_ring_emit(ring, 0);
> intel_ring_emit(ring, MI_NOOP);
> intel_ring_advance(ring);
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
--
Ben Widawsky, Intel Open Source Technology Center
next prev parent reply other threads:[~2012-10-03 0:15 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-02 22:43 Updated workaround & VLV fixes Jesse Barnes
2012-10-02 22:43 ` [PATCH 01/12] drm/i915: add more clock gating regs for gen7, make sure writes happen Jesse Barnes
2012-10-02 23:14 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-02 23:01 ` Daniel Vetter
2012-10-02 23:09 ` Ben Widawsky
2012-10-02 23:14 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 03/12] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB Jesse Barnes
2012-10-02 23:28 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 04/12] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-10-02 23:32 ` Ben Widawsky
2012-10-03 7:24 ` Daniel Vetter
2012-10-02 22:43 ` [PATCH 05/12] drm/i915: implement WaGTEnableMiFlush on VLV Jesse Barnes
2012-10-02 23:35 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 06/12] drm/i915: implement WaDisableVLVClockGating_VBIIssue " Jesse Barnes
2012-10-02 23:38 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB Jesse Barnes
2012-10-02 23:44 ` Ben Widawsky
2012-10-03 7:23 ` Daniel Vetter
2012-10-10 20:04 ` Paulo Zanoni
2012-10-10 21:13 ` Lespiau, Damien
2012-10-02 22:43 ` [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB Jesse Barnes
2012-10-02 23:51 ` Ben Widawsky
2012-10-02 23:58 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 09/12] drm/i915: limit VLV IRQ enables to those we use Jesse Barnes
2012-10-02 23:53 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Jesse Barnes
2012-10-03 0:14 ` Ben Widawsky [this message]
2012-10-03 7:20 ` Daniel Vetter
2012-10-04 8:32 ` Daniel Vetter
2012-10-04 14:39 ` Jesse Barnes
2012-10-04 14:49 ` Daniel Vetter
2012-10-04 14:54 ` Jesse Barnes
2012-10-02 22:43 ` [PATCH 11/12] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-02 22:43 ` [PATCH 12/12] drm/i915: set swizzling to none on VLV Jesse Barnes
2012-10-03 7:15 ` Daniel Vetter
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