From: Ben Widawsky <ben@bwidawsk.net>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB
Date: Tue, 2 Oct 2012 16:51:39 -0700 [thread overview]
Message-ID: <20121002165139.6e106276@bwidawsk.net> (raw)
In-Reply-To: <1349217826-2538-9-git-send-email-jbarnes@virtuousgeek.org>
On Tue, 2 Oct 2012 17:43:42 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Workaround for dual port PS dispatch on GT1.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 400dd05..ce8d7b2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3541,6 +3541,16 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> + /* WaDisablePSDDualDispatchEnable */
> + if (IS_MOBILE(dev))
> + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> + I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> + else
> + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB,
> + I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> +
> /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
> I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
Seems like we need this on VLV too. Also, I can't find this register in
the bspec, which is annoying - but I see the w/a.
--
Ben Widawsky, Intel Open Source Technology Center
next prev parent reply other threads:[~2012-10-02 23:51 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-02 22:43 Updated workaround & VLV fixes Jesse Barnes
2012-10-02 22:43 ` [PATCH 01/12] drm/i915: add more clock gating regs for gen7, make sure writes happen Jesse Barnes
2012-10-02 23:14 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-02 23:01 ` Daniel Vetter
2012-10-02 23:09 ` Ben Widawsky
2012-10-02 23:14 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 03/12] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB Jesse Barnes
2012-10-02 23:28 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 04/12] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-10-02 23:32 ` Ben Widawsky
2012-10-03 7:24 ` Daniel Vetter
2012-10-02 22:43 ` [PATCH 05/12] drm/i915: implement WaGTEnableMiFlush on VLV Jesse Barnes
2012-10-02 23:35 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 06/12] drm/i915: implement WaDisableVLVClockGating_VBIIssue " Jesse Barnes
2012-10-02 23:38 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB Jesse Barnes
2012-10-02 23:44 ` Ben Widawsky
2012-10-03 7:23 ` Daniel Vetter
2012-10-10 20:04 ` Paulo Zanoni
2012-10-10 21:13 ` Lespiau, Damien
2012-10-02 22:43 ` [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB Jesse Barnes
2012-10-02 23:51 ` Ben Widawsky [this message]
2012-10-02 23:58 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 09/12] drm/i915: limit VLV IRQ enables to those we use Jesse Barnes
2012-10-02 23:53 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Jesse Barnes
2012-10-03 0:14 ` Ben Widawsky
2012-10-03 7:20 ` Daniel Vetter
2012-10-04 8:32 ` Daniel Vetter
2012-10-04 14:39 ` Jesse Barnes
2012-10-04 14:49 ` Daniel Vetter
2012-10-04 14:54 ` Jesse Barnes
2012-10-02 22:43 ` [PATCH 11/12] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-02 22:43 ` [PATCH 12/12] drm/i915: set swizzling to none on VLV Jesse Barnes
2012-10-03 7:15 ` Daniel Vetter
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