From: Daniel Vetter <daniel@ffwll.ch>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV
Date: Wed, 3 Oct 2012 01:01:07 +0200 [thread overview]
Message-ID: <20121002230107.GF5679@phenom.ffwll.local> (raw)
In-Reply-To: <1349217826-2538-3-git-send-email-jbarnes@virtuousgeek.org>
On Tue, Oct 02, 2012 at 05:43:36PM -0500, Jesse Barnes wrote:
> Needs to be set on every context restore as well, so set it as part of
> the initial state so we can save/restore it.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7d133a1..58935a3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3442,6 +3442,7 @@
>
> #define GEN7_L3CNTLREG1 0xB01C
> #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
> +#define GEN7_L3AGDIS (1<<19)
>
> #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
> #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 82ca172..f7344c9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3614,7 +3614,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
>
> /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
> - I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
> + I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
tbh I don't like rmw magic register values, since that essentially means
that for suspend resume support we need either
- the bios restoring these magic values for us
- have a separate piece of save/restore code
- actually the read isn't required and there's nothing to restore in
additions to the bits we're setting
All of which are a royal pain for long-term maintaince, especially since
our current suspend/resume code is already a fragile mess.
Can we do better and just write the right settings to this register
unconditionally?
-Daniel
> I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
>
> /* This is required by WaCatErrorRejectionIssue */
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2012-10-02 23:00 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-02 22:43 Updated workaround & VLV fixes Jesse Barnes
2012-10-02 22:43 ` [PATCH 01/12] drm/i915: add more clock gating regs for gen7, make sure writes happen Jesse Barnes
2012-10-02 23:14 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-02 23:01 ` Daniel Vetter [this message]
2012-10-02 23:09 ` Ben Widawsky
2012-10-02 23:14 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 03/12] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB Jesse Barnes
2012-10-02 23:28 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 04/12] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-10-02 23:32 ` Ben Widawsky
2012-10-03 7:24 ` Daniel Vetter
2012-10-02 22:43 ` [PATCH 05/12] drm/i915: implement WaGTEnableMiFlush on VLV Jesse Barnes
2012-10-02 23:35 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 06/12] drm/i915: implement WaDisableVLVClockGating_VBIIssue " Jesse Barnes
2012-10-02 23:38 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB Jesse Barnes
2012-10-02 23:44 ` Ben Widawsky
2012-10-03 7:23 ` Daniel Vetter
2012-10-10 20:04 ` Paulo Zanoni
2012-10-10 21:13 ` Lespiau, Damien
2012-10-02 22:43 ` [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB Jesse Barnes
2012-10-02 23:51 ` Ben Widawsky
2012-10-02 23:58 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 09/12] drm/i915: limit VLV IRQ enables to those we use Jesse Barnes
2012-10-02 23:53 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Jesse Barnes
2012-10-03 0:14 ` Ben Widawsky
2012-10-03 7:20 ` Daniel Vetter
2012-10-04 8:32 ` Daniel Vetter
2012-10-04 14:39 ` Jesse Barnes
2012-10-04 14:49 ` Daniel Vetter
2012-10-04 14:54 ` Jesse Barnes
2012-10-02 22:43 ` [PATCH 11/12] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-02 22:43 ` [PATCH 12/12] drm/i915: set swizzling to none on VLV Jesse Barnes
2012-10-03 7:15 ` Daniel Vetter
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