From: Daniel Vetter <daniel@ffwll.ch>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function
Date: Fri, 2 Nov 2012 16:34:26 +0100 [thread overview]
Message-ID: <20121102153426.GL5755@phenom.ffwll.local> (raw)
In-Reply-To: <1351192548-2992-8-git-send-email-jbarnes@virtuousgeek.org>
On Thu, Oct 25, 2012 at 12:15:48PM -0700, Jesse Barnes wrote:
> So we can write them properly.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Slurped in the entire series, thanks for the patches.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_drv.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d4b3507..fb4b816 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1129,8 +1129,17 @@ static bool IS_DISPLAYREG(u32 reg)
> return false;
>
> switch (reg) {
> + case _3D_CHICKEN3:
> + case IVB_CHICKEN3:
> + case GEN7_COMMON_SLICE_CHICKEN1:
> + case GEN7_L3CNTLREG1:
> + case GEN7_L3_CHICKEN_MODE_REGISTER:
> case GEN7_ROW_CHICKEN2:
> + case GEN7_L3SQCREG4:
> + case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
> case GEN7_HALF_SLICE_CHICKEN1:
> + case GEN6_MBCTL:
> + case GEN6_UCGCTL2:
> return false;
/me screams
> default:
> break;
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2012-11-02 15:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-25 19:15 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-25 19:15 ` [PATCH 2/8] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB Jesse Barnes
2012-10-25 19:15 ` [PATCH 3/8] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-10-25 19:15 ` [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV Jesse Barnes
2012-11-01 14:48 ` Antti Koskipää
2012-11-01 14:50 ` Jesse Barnes
2012-11-01 14:52 ` Antti Koskipää
2012-10-25 19:15 ` [PATCH 5/8] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV Jesse Barnes
2012-10-25 19:15 ` [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op Jesse Barnes
2012-10-26 11:13 ` Chris Wilson
2012-10-26 16:42 ` Jesse Barnes
2012-11-02 12:41 ` Chris Wilson
2012-10-25 19:15 ` [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-25 19:15 ` [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function Jesse Barnes
2012-11-02 15:34 ` Daniel Vetter [this message]
-- strict thread matches above, loose matches on Subject: below --
2012-10-18 18:07 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-18 18:07 ` [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function Jesse Barnes
2012-10-18 15:43 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-18 15:43 ` [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function Jesse Barnes
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