Re: [PATCH 0/8] lvds cleanup

[Daniel Vetter <daniel@ffwll.ch>]

On Fri, Nov 16, 2012 at 02:09:05PM -0200, Paulo Zanoni wrote:
> Hi
> 
> 2012/11/5 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > Hi all,
> >
> > This is the first cleanup from my next stab at reworking the modeset code, with
> > the ultimate goal that we can compute the entire configuration (fdi config, pll
> > config, sharing of global resources) up-front, before touching the hw at all.
> > Together with some neat hw state readout this should make fastboot much more
> > solid, and obviously it's a requirement to properly implement the check mode of
> > atomic modeset.
> >
> > Here I move some of the lvds stuff out of line, simple to better see through the
> > jungle. The newly-added pre_pll_enable callback might be unnecessary in the end,
> > since I think we should also move the pll enabling into the crtc_enable callback
> > and out of ->mode_set. Also, we need some notion of exclusive pch_pll (which the
> > lvds port needs to obey the modeset sequence) and stop disabling pch plls
> > unconditionally, since they might be in use by another active pipe. But that is
> > all stuff on top, once the entire clock handling rework settles.
> >
> > For context, my current wip (iow: where I am stuck atm ...):
> >
> > http://cgit.freedesktop.org/~danvet/drm/log/?h=modeset-rework
> >
> > Comments, flames and test reports highly welcome.
> 
> Since you're already touching LVDS, can I also volunteer you to take a
> look at the LVDS_CTL register description on our documentation and
> implement all the workarounds listed there? A quick look shows we are
> missing at least bit 31 in cpt/ppt.

tbh I'm not sure what we're supposed to do with that w/a: Since the clock
gating bits need to be set until we first enable the lvds in dual_link
mode, I think this is the BIOS' job. So would you be ok if I just add a
check that those bits are set when enabling the lvds output. And if that's
not the case, print a debug message? We can think harder about this once
we have an lvds panel with a black screen ...
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch