From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 9/9] drm/i915: set FORCE_ARB_IDLE_PLANES workaround
Date: Mon, 20 May 2013 16:37:18 +0300 [thread overview]
Message-ID: <20130520133718.GC14974@intel.com> (raw)
In-Reply-To: <1367612625-4823-10-git-send-email-przanoni@gmail.com>
On Fri, May 03, 2013 at 05:23:45PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Commit 1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a added a workaround
> inside haswell_init_clock_gating and mentioned it is "a workaround for
> early silicon revisions and should be removed later". This workaround
> is documented in bit 31 of PRI_CTL. I asked Arthur and he mentioned
> that setting FORCE_ARB_IDLE_PLANES replaces that workaround for the
> newer machines. So use the new one.
>
> Also notice that there's still another workaround for PRI_CTL that
> involves WM_DBG, but it's not the one we're reverting. And notice that
> we were previously setting WM_DBG_DISALLOW_MULTIPIPE_LP which disables
> the LP watermarks when more than one pipe is used, and we really don't
> want this because we need the LP watermarks if we want to reach deeper
> PC states.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 10 ++--------
> 2 files changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index aec569f..5879f23 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3697,6 +3697,9 @@
> # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
> # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
>
> +#define CHICKEN_PAR1_1 0x42080
> +#define FORCE_ARB_IDLE_PLANES (1 << 14)
> +
> #define DISP_ARB_CTL 0x45000
> #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
> #define DISP_FBC_WM_DIS (1<<15)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b56de92..2297476 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4042,14 +4042,8 @@ static void haswell_init_clock_gating(struct drm_device *dev)
> /* WaSwitchSolVfFArbitrationPriority */
> I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>
> - /* XXX: This is a workaround for early silicon revisions and should be
> - * removed later.
> - */
> - I915_WRITE(WM_DBG,
> - I915_READ(WM_DBG) |
> - WM_DBG_DISALLOW_MULTIPLE_LP |
> - WM_DBG_DISALLOW_SPRITE |
> - WM_DBG_DISALLOW_MAXFIFO);
> + I915_WRITE(CHICKEN_PAR1_1,
> + I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
>
> lpt_init_clock_gating(dev);
> }
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2013-05-20 13:37 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-03 20:23 [PATCH 0/9] Haswell watermarks, round 1 Paulo Zanoni
2013-05-03 20:23 ` [PATCH 1/9] drm/i915: ILK, SNB and IVB don't have linetime watermarks Paulo Zanoni
2013-05-20 13:41 ` Ville Syrjälä
2013-05-03 20:23 ` [PATCH 2/9] drm/i915: fix linetime_watermarks code Paulo Zanoni
2013-05-05 7:19 ` Chris Wilson
2013-05-06 13:13 ` Paulo Zanoni
2013-05-06 13:43 ` Chris Wilson
2013-05-09 19:55 ` [PATCH 2/9] drm/i915: remove intel_update_linetime_watermarks Paulo Zanoni
2013-05-20 13:48 ` Ville Syrjälä
2013-05-03 20:23 ` [PATCH 3/9] drm/i915: use the mode->htotal to calculate linetime watermarks Paulo Zanoni
2013-05-20 13:42 ` Ville Syrjälä
2013-05-21 9:26 ` Daniel Vetter
2013-05-21 14:33 ` Paulo Zanoni
2013-05-21 14:59 ` Daniel Vetter
2013-05-03 20:23 ` [PATCH 4/9] drm/i915: fix haswell linetime watermarks calculation Paulo Zanoni
2013-05-20 13:53 ` Ville Syrjälä
2013-05-03 20:23 ` [PATCH 5/9] drm/i915: use the correct clock when calculating linetime watermarks Paulo Zanoni
2013-05-20 14:00 ` Ville Syrjälä
2013-05-21 9:35 ` Daniel Vetter
2013-05-03 20:23 ` [PATCH 6/9] drm/i915: make intel_ddi_get_cdclk_freq return values in KHz Paulo Zanoni
2013-05-05 7:20 ` Chris Wilson
2013-05-06 13:53 ` Paulo Zanoni
2013-05-20 14:11 ` Ville Syrjälä
2013-05-03 20:23 ` [PATCH 7/9] drm/i915: set the IPS linetime watermark Paulo Zanoni
2013-05-20 14:05 ` Ville Syrjälä
2013-05-03 20:23 ` [PATCH 8/9] drm/i915: MCH_SSKPD is a 64 bit register on Haswell Paulo Zanoni
2013-05-20 13:38 ` Ville Syrjälä
2013-05-03 20:23 ` [PATCH 9/9] drm/i915: set FORCE_ARB_IDLE_PLANES workaround Paulo Zanoni
2013-05-20 13:37 ` Ville Syrjälä [this message]
2013-05-21 10:01 ` Daniel Vetter
2013-05-21 13:27 ` Paulo Zanoni
2013-05-23 10:36 ` Ville Syrjälä
2013-05-23 10:51 ` Daniel Vetter
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